fma simulation infrastructure

pipelined/src/fma/fma.do

@@ -0,0 +1,23 @@
+# fma.do 
+#
+# run with vsim -do "do fma.do"
+# add -c before -do for batch simulation
+
+onbreak {resume}
+
+# create library
+vlib worklib
+
+vlog -lint -work worklib fma16.sv testbench.sv
+vopt +acc worklib.testbench -work worklib -o testbenchopt
+vsim -lib worklib testbenchopt
+
+add wave sim:/testbench/clk
+add wave sim:/testbench/reset
+add wave sim:/testbench/x
+add wave sim:/testbench/y
+add wave sim:/testbench/z
+add wave sim:/testbench/result
+add wave sim:/testbench/rexpected
+
+run -all

pipelined/src/fma/fma16_testgen.c

@@ -0,0 +1,142 @@
+#include <stdio.h>
+#include <stdint.h>
+#include "softfloat.h"
+#include "softfloat_types.h"
+
+typedef union sp {
+  float32_t v;
+  float f;
+} sp;
+
+// lists of tests, terminated with 0x8000
+uint16_t easyExponents[] = {15, 0x8000};
+uint16_t medExponents[] = {1, 14, 15, 16, 20, 30, 0x8000};
+uint16_t easyFracts[] = {0, 0x200, 0x8000}; // 1.0 and 1.1
+uint16_t medFracts[] = {0, 0x200, 0x001, 0x3FF, 0x8000}; 
+uint16_t zeros[] = {0x0000, 0x8000};
+uint16_t infs[] = {0x7C00, 0xFC00};
+uint16_t nans[] = {0x7D00, 0x7D01};
+
+void softfloatInit(void) {
+    softfloat_roundingMode = softfloat_round_minMag; 
+    softfloat_exceptionFlags = 0;
+    softfloat_detectTininess = softfloat_tininess_beforeRounding;
+}
+
+float convFloat(float16_t f16) {
+    float32_t f32;
+    float res;
+    sp r;
+
+    f32 = f16_to_f32(f16);
+    r.v = f32;
+    res = r.f;
+    return res;
+}
+
+void genCase(FILE *fptr, float16_t x, float16_t y, float16_t z, int mul, int add, int negp, int negz, int zeroAllowed, int infAllowed, int nanAllowed) {
+    float16_t result;
+    int op;
+    char calc[80];
+    float32_t x32, y32, z32, r32;
+    float xf, yf, zf, rf;
+    float16_t smallest;
+
+    if (!mul) y.v = 0x3C00; // force y to 1 to avoid multiply
+    if (!add) z.v = 0x0000; // force z to 0 to avoid add
+    if (negp) x.v ^= 0x8000; // flip sign of x to negate p
+    if (negz) z.v ^= 0x8000; // flip sign of z to negate z
+    op = mul<<3 | add<<2 | negp<<1 | negz;
+    result = f16_mulAdd(x, y, z);
+
+    // convert to floats for printing
+    xf = convFloat(x);
+    yf = convFloat(y);
+    zf = convFloat(z);
+    rf = convFloat(result);
+    if (mul)
+        if (add) sprintf(calc, "%f * %f + %f = %f", xf, yf, zf, rf);
+        else     sprintf(calc, "%f * %f = %f", xf, yf, rf);
+    else         sprintf(calc, "%f + %f = %f", xf, zf, rf);
+
+    // omit denorms, which aren't required for this project
+    smallest.v = 0x0400;
+    float16_t resultmag = result;
+    resultmag.v &= 0x7FFF; // take absolute value
+    if (f16_lt(resultmag, smallest) && (resultmag.v != 0x0000)) fprintf (fptr, "// skip denorm: ");
+    if (resultmag.v == 0x0000 && !zeroAllowed) fprintf(fptr, "// skip zero: ");
+    if (resultmag.v == 0x7C00 && !infAllowed)  fprintf(fptr, "// Skip inf: ");
+    if (resultmag.v >  0x7C00 && !nanAllowed)  fprintf(fptr, "// Skip NaN: ");
+    fprintf(fptr, "%04x_%04x_%04x_%02x_%04x // %s\n", x.v, y.v, z.v, op, result.v, calc);
+}
+
+void prepTests(uint16_t *e, uint16_t *f, char *testName, char *desc, float16_t *cases, 
+               FILE *fptr, int *numCases) {
+    int i, j;
+
+    fprintf(fptr, desc); fprintf(fptr, "\n");
+    *numCases=0;
+    for (i=0; e[i] != 0x8000; i++)
+        for (j=0; f[j] != 0x8000; j++) {
+            cases[*numCases].v = f[j] | e[i]<<10;
+            *numCases = *numCases + 1;
+        }
+}
+
+void genMulTests(uint16_t *e, uint16_t *f, int sgn, char *testName, char *desc, int zeroAllowed, int infAllowed, int nanAllowed) {
+    int i, j, k, numCases;
+    float16_t x, y, z;
+    float16_t cases[100000];
+    FILE *fptr;
+    char fn[80];
+ 
+    sprintf(fn, "work/%s.tv", testName);
+    fptr = fopen(fn, "w");
+    prepTests(e, f, testName, desc, cases, fptr, &numCases);
+    z.v = 0x0000;
+    for (i=0; i < numCases; i++) { 
+        x.v = cases[i].v;
+        for (j=0; j<numCases; j++) {
+            y.v = cases[j].v;
+            for (k=0; k<=sgn; k++) {
+                y.v ^= (k<<15);
+                genCase(fptr, x, y, z, 1, 0, 0, 0, zeroAllowed, infAllowed, nanAllowed);
+            }
+        }
+    }
+    fclose(fptr);
+}
+
+void genAddTests(uint16_t *e, uint16_t *f, int sgn, char *testName, char *desc) {
+    int i, j, numCases;
+    float16_t x, y, z;
+    float16_t cases[100000];
+    FILE *fptr;
+    char fn[80];
+ 
+    sprintf(fn, "work/%s.tv", testName);
+    fptr = fopen(fn, "w");
+    prepTests(e, f, testName, desc, cases, fptr, &numCases);
+    y.v = 0x0000;
+    for (i=0; i < numCases; i++) {
+        x.v = cases[i].v;
+        for (j=0; j<numCases; j++) {
+            z.v = cases[j].v;
+            //genCase(fptr, x, y, z, 0, 1, 0, 0);
+        }
+    }
+    fclose(fptr);
+}
+
+
+int main()
+{
+    softfloatInit(); // configure softfloat modes
+ 
+    // Test cases: multiplication
+    genMulTests(easyExponents, easyFracts, 0, "fmul_0", "// Multiply with exponent of 0, significand of 1.0 and 1.1, RZ", 0, 0, 0);
+    genMulTests(medExponents, medFracts, 0, "fmul_1", "// Multiply with various exponents and unsigned fractions, RZ", 0, 0, 0);
+    genMulTests(medExponents, medFracts, 1, "fmul_2", "// Multiply with various exponents and signed fractions, RZ", 0, 0, 0);
+
+    return 0;
+}

pipelined/src/fma/lint-fma

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+#!/bin/bash
+# check for warnings in Verilog code
+# The verilator lint tool is faster and better than Modelsim so it is best to run this first.
+export PATH=$PATH:/usr/local/bin/
+verilator=`which verilator`
+
+basepath=$(dirname $0)/..
+$verilator --lint-only --top-module fma16 fma16.sv

pipelined/src/fma/sim-fma

@@ -0,0 +1,2 @@
+vsim -do "do fma.do"
+

pipelined/src/fma/testbench.sv

@@ -0,0 +1,50 @@
+/* verilator lint_off STMTDLY */
+module testbench;
+  logic        clk, reset;
+  logic [15:0] x, y, z, rexpected, result;
+  logic [7:0]  ctrl;
+  logic        mul, add, negp, negz;
+  logic [1:0]  roundmode;
+  logic [31:0] vectornum, errors;
+  logic [71:0] testvectors[10000:0];
+
+  // instantiate device under test
+  fma16 dut(x, y, z, mul, add, negp, negz, roundmode, result);
+
+  // generate clock
+  always 
+    begin
+      clk = 1; #5; clk = 0; #5;
+    end
+
+  // at start of test, load vectors and pulse reset
+  initial
+    begin
+      $readmemh("work/fmul_1.tv", testvectors);
+      vectornum = 0; errors = 0;
+      reset = 1; #22; reset = 0;
+    end
+
+  // apply test vectors on rising edge of clk
+  always @(posedge clk)
+    begin
+      #1; {x, y, z, ctrl, rexpected} = testvectors[vectornum];
+      {roundmode, mul, add, negp, negz} = ctrl[5:0];
+    end
+
+  // check results on falling edge of clk
+  always @(negedge clk)
+    if (~reset) begin // skip during reset
+      if (result !== rexpected) begin  // check result
+        $display("Error: inputs %h * %h + %h", x, y, z);
+        $display("  result = %h (%h expected)", result, rexpected);
+        errors = errors + 1;
+      end
+      vectornum = vectornum + 1;
+      if (testvectors[vectornum] === 'x) begin 
+        $display("%d tests completed with %d errors", 
+	           vectornum, errors);
+        $stop;
+      end
+    end
+endmodule