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Lowered arty a7 clock frequency to 15Mhz to meet timing. can probalby go faster.

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This commit is contained in:
Ross Thompson 2023-04-17 12:16:31 -05:00
parent a7a362f82e
commit 0be81fdfc8
1 changed files with 1 additions and 1 deletions
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fpga/generator/xlnx_mmcm.tcl
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@ -15,7 +15,7 @@ set_property -dict [list CONFIG.PRIM_IN_FREQ {100.000} \
CONFIG.CLKOUT4_USED {false} \
CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {166.66667} \
CONFIG.CLKOUT2_REQUESTED_OUT_FREQ {200} \
CONFIG.CLKOUT3_REQUESTED_OUT_FREQ {20} \
CONFIG.CLKOUT3_REQUESTED_OUT_FREQ {15} \
CONFIG.CLKIN1_JITTER_PS {10.0} \
] [get_ips $ipName]