forked from Github_Repos/cvw
Use FlushE to reset integer divider FSM
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@ -36,7 +36,7 @@ module intdivrestoring (
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input logic clk,
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input logic reset,
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input logic StallM,
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input logic TrapM,
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input logic FlushE,
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input logic DivSignedE, W64E,
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input logic DivE,
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//input logic [`XLEN-1:0] SrcAE, SrcBE,
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@ -122,7 +122,7 @@ module intdivrestoring (
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//////////////////////////////
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always_ff @(posedge clk)
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if (reset | TrapM) begin
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if (reset | FlushE) begin
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state <= IDLE;
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end else if (DivStartE) begin
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step <= 1;
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@ -42,7 +42,7 @@ module muldiv (
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// Divide Done
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output logic DivBusyE,
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// hazards
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input logic StallM, StallW, FlushM, FlushW, TrapM
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input logic StallM, StallW, FlushE, FlushM, FlushW
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);
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logic [`XLEN-1:0] MDUResultM;
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@ -67,7 +67,7 @@ module muldiv (
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end else begin
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assign DivE = MDUE & Funct3E[2];
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assign DivSignedE = ~Funct3E[0];
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intdivrestoring div(.clk, .reset, .StallM, .TrapM, .DivSignedE, .W64E, .DivE,
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intdivrestoring div(.clk, .reset, .StallM, .FlushE, .DivSignedE, .W64E, .DivE,
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.ForwardedSrcAE, .ForwardedSrcBE, .DivBusyE, .QuotM, .RemM);
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end
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@ -375,7 +375,7 @@ module wallypipelinedcore (
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.ForwardedSrcAE, .ForwardedSrcBE,
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.Funct3E, .Funct3M, .MDUE, .W64E,
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.MDUResultW, .DivBusyE,
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.StallM, .StallW, .FlushM, .FlushW, .TrapM
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.StallM, .StallW, .FlushE, .FlushM, .FlushW
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);
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end else begin // no M instructions supported
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assign MDUResultW = 0;
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