Renamed muldiv to mdu

pipelined/src/fpu/fdivsqrt/fdivsqrtpreproc.sv

@@ -70,6 +70,7 @@ module fdivsqrtpreproc (
   // cout the number of leading zeros
 
   // *** W64 muxes conditional on RV64
+  // *** why !FUnct3E
   assign AsE = ~Funct3E[0] & (W64E ? ForwardedSrcAE[31] : ForwardedSrcAE[`XLEN-1]);
   assign BsE = ~Funct3E[0] & (W64E ? ForwardedSrcBE[31] : ForwardedSrcBE[`XLEN-1]);
   assign A64 = W64E ? {{(`XLEN-32){AsE}}, ForwardedSrcAE[31:0]} : ForwardedSrcAE;

pipelined/src/mdu/mdu.sv

@@ -1,5 +1,5 @@
 ///////////////////////////////////////////
-// muldiv.sv
+// mdu.sv
 //
 // Written: David_Harris@hmc.edu 9 January 2021
 // Modified: 
@@ -30,7 +30,7 @@
 
 `include "wally-config.vh"
 
-module muldiv (
+module mdu (
 	       input logic 		clk, reset,
 	       // Execute Stage interface
 	       //    input logic [`XLEN-1:0] 	SrcAE, SrcBE,
@@ -94,6 +94,6 @@ module muldiv (
 
 	// Writeback stage pipeline register
 	flopenrc #(`XLEN) MDUResultWReg(clk, reset, FlushW, ~StallW, MDUResultM, MDUResultW);	 
-endmodule // muldiv
+endmodule // mdu
 
 

pipelined/src/wally/wallypipelinedcore.sv

@@ -370,7 +370,7 @@ module wallypipelinedcore (
       assign BigEndianM = 0;
    end
    if (`M_SUPPORTED) begin:mdu
-      muldiv mdu(
+      mdu mdu(
          .clk, .reset,
          .ForwardedSrcAE, .ForwardedSrcBE, 
          .Funct3E, .Funct3M, .MDUE, .W64E,