forked from Github_Repos/cvw
Partitioned fma into separate files
This commit is contained in:
David Harris
parent
d2de84a456
commit
e3b970d3ff
@ -1 +1 @@
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vsim -c -do "do wally-pipelined-batch.do rv32gc wally32periph"
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vsim -c -do "do wally-pipelined-batch.do rv64gc arch64d"
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@ -1,7 +1,7 @@
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///////////////////////////////////////////
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//
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// Written: me@KatherineParry.com, David Harris
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// Modified: 6/23/2021
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// Written: 6/23/2021 me@KatherineParry.com, David_Harris@hmc.edu
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// Modified:
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//
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// Purpose: Floating point multiply-accumulate of configurable size
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//
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@ -63,18 +63,18 @@ module fma(
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// calculate the product's exponent
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expadd expadd(.Fmt, .Xe, .Ye, .XZero, .YZero, .Pe);
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fmaexpadd expadd(.Fmt, .Xe, .Ye, .XZero, .YZero, .Pe);
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// multiplication of the mantissa's
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mult mult(.Xm, .Ym, .Pm);
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fmamult mult(.Xm, .Ym, .Pm);
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///////////////////////////////////////////////////////////////////////////////
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// Alignment shifter
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///////////////////////////////////////////////////////////////////////////////
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// calculate the signs and take the opperation into account
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sign sign(.OpCtrl, .Xs, .Ys, .Zs, .Ps, .As);
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fmasign sign(.OpCtrl, .Xs, .Ys, .Zs, .Ps, .As);
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align align(.Ze, .Zm, .XZero, .YZero, .ZZero, .Xe, .Ye,
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fmaalign align(.Ze, .Zm, .XZero, .YZero, .ZZero, .Xe, .Ye,
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.Am, .ZmSticky, .KillProd);
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@ -83,223 +83,8 @@ module fma(
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// // Addition/LZA
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// ///////////////////////////////////////////////////////////////////////////////
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add add(.Am, .Pm, .Ze, .Pe, .Ps, .As, .KillProd, .ZmSticky, .AmInv, .PmKilled, .NegSum, .InvA, .Sm, .Se, .Ss);
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fmaadd add(.Am, .Pm, .Ze, .Pe, .Ps, .As, .KillProd, .ZmSticky, .AmInv, .PmKilled, .NegSum, .InvA, .Sm, .Se, .Ss);
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loa loa(.A(AmInv+{(3*`NF+6)'(0),InvA&~((ZmSticky&~KillProd))}), .P({PmKilled, 1'b0, InvA&Ps&ZmSticky&KillProd}), .SCnt);
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fmalza lza(.A(AmInv+{(3*`NF+6)'(0),InvA&~((ZmSticky&~KillProd))}), .P({PmKilled, 1'b0, InvA&Ps&ZmSticky&KillProd}), .SCnt);
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endmodule
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module expadd(
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input logic [`FMTBITS-1:0] Fmt, // format of the output: single double half quad
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input logic [`NE-1:0] Xe, Ye, // input's exponents
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input logic XZero, YZero, // are the inputs zero
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output logic [`NE+1:0] Pe // product's exponent B^(1023)NE+2
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);
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// kill the exponent if the product is zero - either X or Y is 0
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assign Pe = ({2'b0, Xe} + {2'b0, Ye} - {2'b0, (`NE)'(`BIAS)})&{`NE+2{~(XZero|YZero)}};
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endmodule
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module mult(
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input logic [`NF:0] Xm, Ym,
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output logic [2*`NF+1:0] Pm
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);
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assign Pm = Xm * Ym;
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endmodule
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module sign(
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input logic [2:0] OpCtrl, // opperation contol
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input logic Xs, Ys, Zs, // sign of the inputs
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output logic Ps, // the product's sign - takes opperation into account
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output logic As // aligned addend sign used in fma - takes opperation into account
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);
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// Calculate the product's sign
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// Negate product's sign if FNMADD or FNMSUB
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// flip is negation opperation
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assign Ps = Xs ^ Ys ^ (OpCtrl[1]&~OpCtrl[2]);
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// flip if subtraction
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assign As = Zs^OpCtrl[0];
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endmodule
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module align(
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input logic [`NE-1:0] Xe, Ye, Ze, // biased exponents in B(NE.0) format
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input logic [`NF:0] Zm, // significand in U(0.NF) format]
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input logic XZero, YZero, ZZero, // is the input zero
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output logic [3*`NF+5:0] Am, // addend aligned for addition in U(NF+5.2NF+1)
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output logic ZmSticky, // Sticky bit calculated from the aliged addend
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output logic KillProd // should the product be set to zero
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);
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logic [`NE+1:0] ACnt; // how far to shift the addend to align with the product in Q(NE+2.0) format
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logic [4*`NF+5:0] ZmShifted; // output of the alignment shifter including sticky bits U(NF+5.3NF+1)
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logic [4*`NF+5:0] ZmPreshifted; // input to the alignment shifter U(NF+5.3NF+1)
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logic KillZ;
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///////////////////////////////////////////////////////////////////////////////
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// Alignment shifter
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///////////////////////////////////////////////////////////////////////////////
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// determine the shift count for alignment
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// - negitive means Z is larger, so shift Z left
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// - positive means the product is larger, so shift Z right
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// This could have been done using Pe, but ACnt is on the critical path so we replicate logic for speed
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assign ACnt = {2'b0, Xe} + {2'b0, Ye} - {2'b0, (`NE)'(`BIAS)} + (`NE+2)'(`NF+3) - {2'b0, Ze};
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// Defualt Addition without shifting
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// | 54'b0 | 106'b(product) | 2'b0 |
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// | addnend |
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// the 1'b0 before the added is because the product's mantissa has two bits before the binary point (xx.xxxxxxxxxx...)
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assign ZmPreshifted = {Zm,(3*`NF+5)'(0)};
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assign KillProd = (ACnt[`NE+1]&~ZZero)|XZero|YZero;
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assign KillZ = $signed(ACnt)>$signed((`NE+2)'(3)*(`NE+2)'(`NF)+(`NE+2)'(5));
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always_comb
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begin
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// If the product is too small to effect the sum, kill the product
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// | 54'b0 | 106'b(product) | 2'b0 |
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// | addnend |
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if (KillProd) begin
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ZmShifted = {(`NF+3)'(0), Zm, (2*`NF+2)'(0)};
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ZmSticky = ~(XZero|YZero);
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// If the addend is too small to effect the addition
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// - The addend has to shift two past the end of the addend to be considered too small
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// - The 2 extra bits are needed for rounding
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// | 54'b0 | 106'b(product) | 2'b0 |
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// | addnend |
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end else if (KillZ) begin
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ZmShifted = 0;
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ZmSticky = ~ZZero;
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// If the Addend is shifted right
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// | 54'b0 | 106'b(product) | 2'b0 |
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// | addnend |
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end else begin
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ZmShifted = ZmPreshifted >> ACnt;
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ZmSticky = |(ZmShifted[`NF-1:0]);
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end
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end
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assign Am = ZmShifted[4*`NF+5:`NF];
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endmodule
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module add(
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input logic [3*`NF+5:0] Am, // aligned addend's mantissa for addition in U(NF+5.2NF+1)
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input logic [2*`NF+1:0] Pm, // the product's mantissa
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input logic Ps, As,// the product sign and the alligend addeded's sign (Modified Z sign for other opperations)
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input logic KillProd, // should the product be set to 0
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input logic ZmSticky,
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input logic [`NE-1:0] Ze,
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input logic [`NE+1:0] Pe,
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output logic [3*`NF+6:0] AmInv, // aligned addend possibly inverted
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output logic [2*`NF+1:0] PmKilled, // the product's mantissa possibly killed
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output logic NegSum, // was the sum negitive
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output logic InvA, // do you invert the aligned addend
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output logic Ss,
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output logic [`NE+1:0] Se,
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output logic [3*`NF+5:0] Sm // the positive sum
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);
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logic [3*`NF+6:0] PreSum, NegPreSum; // possibly negitive sum
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///////////////////////////////////////////////////////////////////////////////
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// Addition
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///////////////////////////////////////////////////////////////////////////////
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// Negate Z when doing one of the following opperations:
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// -prod + Z
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// prod - Z
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assign InvA = As ^ Ps;
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// Choose an inverted or non-inverted addend - the one has to be added now for the LZA
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assign AmInv = InvA ? {1'b1, ~Am} : {1'b0, Am};
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// Kill the product if the product is too small to effect the addition (determined in fma1.sv)
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assign PmKilled = Pm&{2*`NF+2{~KillProd}};
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// Do the addition
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// - calculate a positive and negitive sum in parallel
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// Zsticky Psticky
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// PreSum -1 = don't add 1 +1 = add 2
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// NegPreSum +1 = add 2 -1 = don't add 1
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// for NegPreSum the product is set to -1 whenever the product is killed, therefore add 1, 2 or 0
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assign PreSum = {{`NF+3{1'b0}}, PmKilled, 1'b0, InvA&ZmSticky&KillProd} + AmInv + {{3*`NF+6{1'b0}}, InvA&~((ZmSticky&~KillProd))};
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assign NegPreSum = {1'b0, Am} + {{`NF+3{1'b1}}, ~PmKilled, 2'b11} + {(3*`NF+5)'(0), ZmSticky&~KillProd, ~(ZmSticky)};
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// Is the sum negitive
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assign NegSum = PreSum[3*`NF+6];
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// Choose the positive sum and accompanying LZA result.
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assign Sm = NegSum ? NegPreSum[3*`NF+5:0] : PreSum[3*`NF+5:0];
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// is the result negitive
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// if p - z is the Sum negitive
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// if -p + z is the Sum positive
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// if -p - z then the Sum is negitive
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assign Ss = NegSum^Ps; //*** move to execute stage
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assign Se = KillProd ? {2'b0, Ze} : Pe;
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endmodule
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module loa( // [Schmookler & Nowka, Leading zero anticipation and detection, IEEE Sym. Computer Arithmetic, 2001]
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input logic [3*`NF+6:0] A, // addend
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input logic [2*`NF+3:0] P, // product
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output logic [$clog2(3*`NF+7)-1:0] SCnt // normalization shift count for the positive result
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);
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logic [3*`NF+6:0] T;
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logic [3*`NF+6:0] G;
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logic [3*`NF+6:0] Z;
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logic [3*`NF+6:0] f;
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assign T[3*`NF+6:2*`NF+4] = A[3*`NF+6:2*`NF+4];
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assign G[3*`NF+6:2*`NF+4] = 0;
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assign Z[3*`NF+6:2*`NF+4] = ~A[3*`NF+6:2*`NF+4];
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assign T[2*`NF+3:0] = A[2*`NF+3:0]^P;
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assign G[2*`NF+3:0] = A[2*`NF+3:0]&P;
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assign Z[2*`NF+3:0] = ~A[2*`NF+3:0]&~P;
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// Apply function to determine Leading pattern
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// - note: the paper linked above uses the numbering system where 0 is the most significant bit
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//f[n] = ~T[n]&T[n-1] note: n is the MSB
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//f[i] = (T[i+1]&(G[i]&~Z[i-1] | Z[i]&~G[i-1])) | (~T[i+1]&(Z[i]&~Z[i-1] | G[i]&~G[i-1]))
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assign f[3*`NF+6] = ~T[3*`NF+6]&T[3*`NF+5];
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assign f[3*`NF+5:0] = (T[3*`NF+6:1]&(G[3*`NF+5:0]&{~Z[3*`NF+4:0], 1'b0} | Z[3*`NF+5:0]&{~G[3*`NF+4:0], 1'b1})) | (~T[3*`NF+6:1]&(Z[3*`NF+5:0]&{~Z[3*`NF+4:0], 1'b0} | G[3*`NF+5:0]&{~G[3*`NF+4:0], 1'b1}));
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lzc #(3*`NF+7) lzc (.num(f), .ZeroCnt(SCnt));
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endmodule
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83
pipelined/src/fpu/fmaadd.sv
Normal file
83
pipelined/src/fpu/fmaadd.sv
Normal file
@ -0,0 +1,83 @@
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///////////////////////////////////////////
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//
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// Written: 6/23/2021 me@KatherineParry.com, David_Harris@hmc.edu
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// Modified:
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//
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// Purpose: FMA significand adder
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// MIT LICENSE
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this
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// software and associated documentation files (the "Software"), to deal in the Software
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// without restriction, including without limitation the rights to use, copy, modify, merge,
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// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons
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// to whom the Software is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or
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// substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
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// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
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// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE
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// OR OTHER DEALINGS IN THE SOFTWARE.
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////////////////////////////////////////////////////////////////////////////////////////////////
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`include "wally-config.vh"
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module fmaadd(
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input logic [3*`NF+5:0] Am, // aligned addend's mantissa for addition in U(NF+5.2NF+1)
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input logic [2*`NF+1:0] Pm, // the product's mantissa
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input logic Ps, As,// the product sign and the alligend addeded's sign (Modified Z sign for other opperations)
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input logic KillProd, // should the product be set to 0
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input logic ZmSticky,
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input logic [`NE-1:0] Ze,
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input logic [`NE+1:0] Pe,
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output logic [3*`NF+6:0] AmInv, // aligned addend possibly inverted
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output logic [2*`NF+1:0] PmKilled, // the product's mantissa possibly killed
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output logic NegSum, // was the sum negitive
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output logic InvA, // do you invert the aligned addend
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output logic Ss,
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output logic [`NE+1:0] Se,
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output logic [3*`NF+5:0] Sm // the positive sum
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);
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logic [3*`NF+6:0] PreSum, NegPreSum; // possibly negitive sum
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///////////////////////////////////////////////////////////////////////////////
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// Addition
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///////////////////////////////////////////////////////////////////////////////
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// Negate Z when doing one of the following opperations:
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// -prod + Z
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// prod - Z
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assign InvA = As ^ Ps;
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// Choose an inverted or non-inverted addend - the one has to be added now for the LZA
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assign AmInv = InvA ? {1'b1, ~Am} : {1'b0, Am};
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// Kill the product if the product is too small to effect the addition (determined in fma1.sv)
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assign PmKilled = Pm&{2*`NF+2{~KillProd}};
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// Do the addition
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// - calculate a positive and negitive sum in parallel
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// Zsticky Psticky
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// PreSum -1 = don't add 1 +1 = add 2
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// NegPreSum +1 = add 2 -1 = don't add 1
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// for NegPreSum the product is set to -1 whenever the product is killed, therefore add 1, 2 or 0
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assign PreSum = {{`NF+3{1'b0}}, PmKilled, 1'b0, InvA&ZmSticky&KillProd} + AmInv + {{3*`NF+6{1'b0}}, InvA&~((ZmSticky&~KillProd))};
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assign NegPreSum = {1'b0, Am} + {{`NF+3{1'b1}}, ~PmKilled, 2'b11} + {(3*`NF+5)'(0), ZmSticky&~KillProd, ~(ZmSticky)};
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// Is the sum negitive
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assign NegSum = PreSum[3*`NF+6];
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// Choose the positive sum and accompanying LZA result.
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assign Sm = NegSum ? NegPreSum[3*`NF+5:0] : PreSum[3*`NF+5:0];
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// is the result negitive
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// if p - z is the Sum negitive
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// if -p + z is the Sum positive
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// if -p - z then the Sum is negitive
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assign Ss = NegSum^Ps; //*** move to execute stage
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assign Se = KillProd ? {2'b0, Ze} : Pe;
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endmodule
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101
pipelined/src/fpu/fmaalign.sv
Normal file
101
pipelined/src/fpu/fmaalign.sv
Normal file
@ -0,0 +1,101 @@
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///////////////////////////////////////////
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//
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// Written: 6/23/2021 me@KatherineParry.com, David_Harris@hmc.edu
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// Modified:
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//
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// Purpose: FMA alginment shift
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// MIT LICENSE
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this
|
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// software and associated documentation files (the "Software"), to deal in the Software
|
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// without restriction, including without limitation the rights to use, copy, modify, merge,
|
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// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons
|
||||
// to whom the Software is furnished to do so, subject to the following conditions:
|
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//
|
||||
// The above copyright notice and this permission notice shall be included in all copies or
|
||||
// substantial portions of the Software.
|
||||
//
|
||||
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
|
||||
// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
|
||||
// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
|
||||
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
|
||||
// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE
|
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// OR OTHER DEALINGS IN THE SOFTWARE.
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////////////////////////////////////////////////////////////////////////////////////////////////
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`include "wally-config.vh"
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module fmaalign(
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input logic [`NE-1:0] Xe, Ye, Ze, // biased exponents in B(NE.0) format
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input logic [`NF:0] Zm, // significand in U(0.NF) format]
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input logic XZero, YZero, ZZero, // is the input zero
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output logic [3*`NF+5:0] Am, // addend aligned for addition in U(NF+5.2NF+1)
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output logic ZmSticky, // Sticky bit calculated from the aliged addend
|
||||
output logic KillProd // should the product be set to zero
|
||||
);
|
||||
|
||||
logic [`NE+1:0] ACnt; // how far to shift the addend to align with the product in Q(NE+2.0) format
|
||||
logic [4*`NF+5:0] ZmShifted; // output of the alignment shifter including sticky bits U(NF+5.3NF+1)
|
||||
logic [4*`NF+5:0] ZmPreshifted; // input to the alignment shifter U(NF+5.3NF+1)
|
||||
logic KillZ;
|
||||
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
// Alignment shifter
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// determine the shift count for alignment
|
||||
// - negitive means Z is larger, so shift Z left
|
||||
// - positive means the product is larger, so shift Z right
|
||||
// This could have been done using Pe, but ACnt is on the critical path so we replicate logic for speed
|
||||
assign ACnt = {2'b0, Xe} + {2'b0, Ye} - {2'b0, (`NE)'(`BIAS)} + (`NE+2)'(`NF+3) - {2'b0, Ze};
|
||||
|
||||
// Defualt Addition without shifting
|
||||
// | 54'b0 | 106'b(product) | 2'b0 |
|
||||
// | addnend |
|
||||
|
||||
// the 1'b0 before the added is because the product's mantissa has two bits before the binary point (xx.xxxxxxxxxx...)
|
||||
assign ZmPreshifted = {Zm,(3*`NF+5)'(0)};
|
||||
|
||||
assign KillProd = (ACnt[`NE+1]&~ZZero)|XZero|YZero;
|
||||
assign KillZ = $signed(ACnt)>$signed((`NE+2)'(3)*(`NE+2)'(`NF)+(`NE+2)'(5));
|
||||
|
||||
always_comb
|
||||
begin
|
||||
|
||||
// If the product is too small to effect the sum, kill the product
|
||||
|
||||
// | 54'b0 | 106'b(product) | 2'b0 |
|
||||
// | addnend |
|
||||
if (KillProd) begin
|
||||
ZmShifted = {(`NF+3)'(0), Zm, (2*`NF+2)'(0)};
|
||||
ZmSticky = ~(XZero|YZero);
|
||||
|
||||
// If the addend is too small to effect the addition
|
||||
// - The addend has to shift two past the end of the addend to be considered too small
|
||||
// - The 2 extra bits are needed for rounding
|
||||
|
||||
// | 54'b0 | 106'b(product) | 2'b0 |
|
||||
// | addnend |
|
||||
end else if (KillZ) begin
|
||||
ZmShifted = 0;
|
||||
ZmSticky = ~ZZero;
|
||||
|
||||
// If the Addend is shifted right
|
||||
// | 54'b0 | 106'b(product) | 2'b0 |
|
||||
// | addnend |
|
||||
end else begin
|
||||
ZmShifted = ZmPreshifted >> ACnt;
|
||||
ZmSticky = |(ZmShifted[`NF-1:0]);
|
||||
|
||||
end
|
||||
end
|
||||
|
||||
assign Am = ZmShifted[4*`NF+5:`NF];
|
||||
|
||||
endmodule
|
||||
|
||||
42
pipelined/src/fpu/fmaexpadd.sv
Normal file
42
pipelined/src/fpu/fmaexpadd.sv
Normal file
@ -0,0 +1,42 @@
|
||||
///////////////////////////////////////////
|
||||
//
|
||||
// Written: 6/23/2021 me@KatherineParry.com, David_Harris@hmc.edu
|
||||
// Modified:
|
||||
//
|
||||
// Purpose: FMA exponent addition
|
||||
//
|
||||
// A component of the Wally configurable RISC-V project.
|
||||
//
|
||||
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
|
||||
//
|
||||
// MIT LICENSE
|
||||
// Permission is hereby granted, free of charge, to any person obtaining a copy of this
|
||||
// software and associated documentation files (the "Software"), to deal in the Software
|
||||
// without restriction, including without limitation the rights to use, copy, modify, merge,
|
||||
// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons
|
||||
// to whom the Software is furnished to do so, subject to the following conditions:
|
||||
//
|
||||
// The above copyright notice and this permission notice shall be included in all copies or
|
||||
// substantial portions of the Software.
|
||||
//
|
||||
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
|
||||
// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
|
||||
// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
|
||||
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
|
||||
// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE
|
||||
// OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
`include "wally-config.vh"
|
||||
|
||||
module fmaexpadd(
|
||||
input logic [`FMTBITS-1:0] Fmt, // format of the output: single double half quad
|
||||
input logic [`NE-1:0] Xe, Ye, // input's exponents
|
||||
input logic XZero, YZero, // are the inputs zero
|
||||
output logic [`NE+1:0] Pe // product's exponent B^(1023)NE+2
|
||||
);
|
||||
|
||||
// kill the exponent if the product is zero - either X or Y is 0
|
||||
assign Pe = ({2'b0, Xe} + {2'b0, Ye} - {2'b0, (`NE)'(`BIAS)})&{`NE+2{~(XZero|YZero)}};
|
||||
|
||||
endmodule
|
||||
62
pipelined/src/fpu/fmalza.sv
Normal file
62
pipelined/src/fpu/fmalza.sv
Normal file
@ -0,0 +1,62 @@
|
||||
///////////////////////////////////////////
|
||||
//
|
||||
// Written: 6/23/2021 me@KatherineParry.com, David_Harris@hmc.edu
|
||||
// Modified:
|
||||
//
|
||||
// Purpose: Leading Zero Anticipator
|
||||
//
|
||||
// A component of the Wally configurable RISC-V project.
|
||||
//
|
||||
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
|
||||
//
|
||||
// MIT LICENSE
|
||||
// Permission is hereby granted, free of charge, to any person obtaining a copy of this
|
||||
// software and associated documentation files (the "Software"), to deal in the Software
|
||||
// without restriction, including without limitation the rights to use, copy, modify, merge,
|
||||
// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons
|
||||
// to whom the Software is furnished to do so, subject to the following conditions:
|
||||
//
|
||||
// The above copyright notice and this permission notice shall be included in all copies or
|
||||
// substantial portions of the Software.
|
||||
//
|
||||
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
|
||||
// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
|
||||
// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
|
||||
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
|
||||
// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE
|
||||
// OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
`include "wally-config.vh"
|
||||
|
||||
module fmalza( // [Schmookler & Nowka, Leading zero anticipation and detection, IEEE Sym. Computer Arithmetic, 2001]
|
||||
input logic [3*`NF+6:0] A, // addend
|
||||
input logic [2*`NF+3:0] P, // product
|
||||
output logic [$clog2(3*`NF+7)-1:0] SCnt // normalization shift count for the positive result
|
||||
);
|
||||
|
||||
logic [3*`NF+6:0] T;
|
||||
logic [3*`NF+6:0] G;
|
||||
logic [3*`NF+6:0] Z;
|
||||
logic [3*`NF+6:0] f;
|
||||
|
||||
assign T[3*`NF+6:2*`NF+4] = A[3*`NF+6:2*`NF+4];
|
||||
assign G[3*`NF+6:2*`NF+4] = 0;
|
||||
assign Z[3*`NF+6:2*`NF+4] = ~A[3*`NF+6:2*`NF+4];
|
||||
assign T[2*`NF+3:0] = A[2*`NF+3:0]^P;
|
||||
assign G[2*`NF+3:0] = A[2*`NF+3:0]&P;
|
||||
assign Z[2*`NF+3:0] = ~A[2*`NF+3:0]&~P;
|
||||
|
||||
|
||||
// Apply function to determine Leading pattern
|
||||
// - note: the paper linked above uses the numbering system where 0 is the most significant bit
|
||||
//f[n] = ~T[n]&T[n-1] note: n is the MSB
|
||||
//f[i] = (T[i+1]&(G[i]&~Z[i-1] | Z[i]&~G[i-1])) | (~T[i+1]&(Z[i]&~Z[i-1] | G[i]&~G[i-1]))
|
||||
assign f[3*`NF+6] = ~T[3*`NF+6]&T[3*`NF+5];
|
||||
assign f[3*`NF+5:0] = (T[3*`NF+6:1]&(G[3*`NF+5:0]&{~Z[3*`NF+4:0], 1'b0} | Z[3*`NF+5:0]&{~G[3*`NF+4:0], 1'b1})) | (~T[3*`NF+6:1]&(Z[3*`NF+5:0]&{~Z[3*`NF+4:0], 1'b0} | G[3*`NF+5:0]&{~G[3*`NF+4:0], 1'b1}));
|
||||
|
||||
|
||||
|
||||
lzc #(3*`NF+7) lzc (.num(f), .ZeroCnt(SCnt));
|
||||
|
||||
endmodule
|
||||
38
pipelined/src/fpu/fmamult.sv
Normal file
38
pipelined/src/fpu/fmamult.sv
Normal file
@ -0,0 +1,38 @@
|
||||
///////////////////////////////////////////
|
||||
//
|
||||
// Written: 6/23/2021 me@KatherineParry.com, David_Harris@hmc.edu
|
||||
// Modified:
|
||||
//
|
||||
// Purpose: FMA Significand Multiplier
|
||||
//
|
||||
// A component of the Wally configurable RISC-V project.
|
||||
//
|
||||
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
|
||||
//
|
||||
// MIT LICENSE
|
||||
// Permission is hereby granted, free of charge, to any person obtaining a copy of this
|
||||
// software and associated documentation files (the "Software"), to deal in the Software
|
||||
// without restriction, including without limitation the rights to use, copy, modify, merge,
|
||||
// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons
|
||||
// to whom the Software is furnished to do so, subject to the following conditions:
|
||||
//
|
||||
// The above copyright notice and this permission notice shall be included in all copies or
|
||||
// substantial portions of the Software.
|
||||
//
|
||||
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
|
||||
// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
|
||||
// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
|
||||
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
|
||||
// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE
|
||||
// OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
`include "wally-config.vh"
|
||||
|
||||
module fmamult(
|
||||
input logic [`NF:0] Xm, Ym,
|
||||
output logic [2*`NF+1:0] Pm
|
||||
);
|
||||
assign Pm = Xm * Ym;
|
||||
endmodule
|
||||
|
||||
47
pipelined/src/fpu/fmasign.sv
Normal file
47
pipelined/src/fpu/fmasign.sv
Normal file
@ -0,0 +1,47 @@
|
||||
///////////////////////////////////////////
|
||||
//
|
||||
// Written: 6/23/2021 me@KatherineParry.com, David_Harris@hmc.edu
|
||||
// Modified:
|
||||
//
|
||||
// Purpose: FMA Sign Logic
|
||||
//
|
||||
// A component of the Wally configurable RISC-V project.
|
||||
//
|
||||
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
|
||||
//
|
||||
// MIT LICENSE
|
||||
// Permission is hereby granted, free of charge, to any person obtaining a copy of this
|
||||
// software and associated documentation files (the "Software"), to deal in the Software
|
||||
// without restriction, including without limitation the rights to use, copy, modify, merge,
|
||||
// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons
|
||||
// to whom the Software is furnished to do so, subject to the following conditions:
|
||||
//
|
||||
// The above copyright notice and this permission notice shall be included in all copies or
|
||||
// substantial portions of the Software.
|
||||
//
|
||||
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
|
||||
// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
|
||||
// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
|
||||
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
|
||||
// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE
|
||||
// OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
`include "wally-config.vh"
|
||||
|
||||
module fmasign(
|
||||
input logic [2:0] OpCtrl, // opperation contol
|
||||
input logic Xs, Ys, Zs, // sign of the inputs
|
||||
output logic Ps, // the product's sign - takes opperation into account
|
||||
output logic As // aligned addend sign used in fma - takes opperation into account
|
||||
);
|
||||
|
||||
// Calculate the product's sign
|
||||
// Negate product's sign if FNMADD or FNMSUB
|
||||
|
||||
// flip is negation opperation
|
||||
assign Ps = Xs ^ Ys ^ (OpCtrl[1]&~OpCtrl[2]);
|
||||
// flip if subtraction
|
||||
assign As = Zs^OpCtrl[0];
|
||||
|
||||
endmodule
|
||||
@ -1902,7 +1902,8 @@ string imperas32f[] = '{
|
||||
"rv32i_m/privilege/src/WALLY-gpio-01.S",
|
||||
"rv32i_m/privilege/src/WALLY-clint-01.S",
|
||||
"rv32i_m/privilege/src/WALLY-uart-01.S",
|
||||
"rv32i_m/privilege/src/WALLY-plic-01.S"
|
||||
"rv32i_m/privilege/src/WALLY-plic-01.S",
|
||||
"rv32i_m/privilege/src/WALLY-plic-s-01.S"
|
||||
};
|
||||
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user