Added bootmem source ccode

This commit is contained in:
David Harris 2022-04-05 23:22:53 +00:00
parent 171b943254
commit 23da303ad3
5 changed files with 22 additions and 6 deletions

1
.gitignore vendored
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@ -70,3 +70,4 @@ synthDC/*.svf
synthDC/runs/
synthDC/hdl
/pipelined/regression/power.saif
tests/fp/vectors/*.tv

@ -1 +1 @@
Subproject commit be67c99bd461742aa1c100bcc0732657faae2230
Subproject commit effd553a6a91ed9b0ba251796a8a44505a45174f

12
linux/bootmem.txt Normal file
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@ -0,0 +1,12 @@
00001000: 00000297 auipc t0, 0 # t0 = 0x00001000
00001004: 02828613 addi a2, t0,0x28 # a2 = 0x00001028
00001008: f1402573 csrr a0, mhartid # a0 = mhartid
0000100c: 0202b583 ld a1, 32(t0) # a1 = 87000000 - device tree address
00001010: 0182b283 ld t0, 24(t0) # t0 = 80000000 - start of firmware
00001014: 00028067 jr t0 # jump to firmware
00001018: 0000000080000000 # firmware start address
00001020: 0000000087000000 # flattened device tree load address
00001028: 000000004942534f # a2 points to this 8 dword data structure
00001030: 0000000000000002
00001038: 0000000080200000
00001040: 0000000000000001

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@ -41,7 +41,6 @@ if {$2 eq "buildroot" || $2 eq "buildroot-checkpoint"} {
run -all
run -all
exec ./slack-notifier/slack-notifier.py
quit
} else {
vlog -lint -work wkdir/work_${1}_${2} +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583 -suppress 7063
# start and run simulation
@ -52,11 +51,15 @@ if {$2 eq "buildroot" || $2 eq "buildroot-checkpoint"} {
#vopt work_$2.testbench -work work_$2 -o workopt_$2 +cover=sbectf
#vsim -coverage -lib work_$2 workopt_$2
# power add generates the logging necessary for saif generation.
power add -r /dut/core/*
run -all
quit
power off -r /dut/core/*
}
#coverage report -file wally-pipelined-coverage.txt
# These aren't doing anything helpful
#coverage report -memory
#profile report -calltree -file wally-pipelined-calltree.rpt -cutoff 2
power report -all -bsaif power.saif
quit

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@ -57,12 +57,12 @@ if {$2 eq "buildroot" || $2 eq "buildroot-checkpoint"} {
do wave.do
# power add generates the logging necessary for saif generation.
#power add -r /dut/core/*
power add -r /dut/core/*
#-- Run the Simulation
run -all
#power off -r /dut/core/*
#power report -all -bsaif power.saif
power off -r /dut/core/*
power report -all -bsaif power.saif
noview ../testbench/testbench.sv
view wave
}