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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main

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This commit is contained in:
Ross Thompson 2022-12-05 17:20:12 -06:00
commit 85366a287b
1 changed files with 2 additions and 2 deletions
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fpga/constraints/debug2.xdc
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@ -316,12 +316,12 @@ connect_debug_port u_ila_0/probe60 [get_nets [list wallypipelinedsoc/core/hzu/IF
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe61]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe61]
connect_debug_port u_ila_0/probe61 [get_nets [list wallypipelinedsoc/core/hzu/FPUStallD ]]
connect_debug_port u_ila_0/probe61 [get_nets [list wallypipelinedsoc/core/hzu/FStallD ]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe62]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe62]
connect_debug_port u_ila_0/probe62 [get_nets [list wallypipelinedsoc/core/hzu/FStallD ]]
connect_debug_port u_ila_0/probe62 [get_nets [list wallypipelinedsoc/core/hzu/FCvtIntStallD ]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe63]