forked from Github_Repos/cvw
Properly decode fcvtint to prevent unnecessary stalls
This commit is contained in:
David Harris
parent
5a82898649
commit
3172dfd6a9
@ -58,7 +58,7 @@ module fctrl (
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output logic [4:0] Adr1E, Adr2E, Adr3E // adresses of each input
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);
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`define FCTRLW 11
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`define FCTRLW 12
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logic [`FCTRLW-1:0] ControlsD;
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logic IllegalFPUInstrD, IllegalFPUInstrE;
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logic FRegWriteD; // FP register write enable
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@ -72,6 +72,7 @@ module fctrl (
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logic [`FMTBITS-1:0] FmtD; // FP format
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logic [1:0] Fmt;
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logic SupportedFmt;
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logic FCvtIntD, FCvtIntM;
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// FPU Instruction Decoder
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assign Fmt = Funct7D[1:0];
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@ -80,97 +81,97 @@ module fctrl (
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(Fmt == 2'b10 & `ZFH_SUPPORTED) | (Fmt == 2'b11 & `Q_SUPPORTED));
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always_comb
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if (STATUS_FS == 2'b00) // FPU instructions are illegal when FPU is disabled
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ControlsD = `FCTRLW'b0_0_00_xx_0xx_0_1;
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ControlsD = `FCTRLW'b0_0_00_xx_0xx_0_1_0;
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else if (OpD != 7'b0000111 & OpD != 7'b0100111 & ~SupportedFmt)
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ControlsD = `FCTRLW'b0_0_00_xx_0xx_0_1; // for anything other than loads and stores, check for supported format
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ControlsD = `FCTRLW'b0_0_00_xx_0xx_0_1_0; // for anything other than loads and stores, check for supported format
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else case(OpD)
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// FRegWrite_FWriteInt_FResSel_PostProcSel_FOpCtrl_FDivStart_IllegalFPUInstr
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// FRegWrite_FWriteInt_FResSel_PostProcSel_FOpCtrl_FDivStart_IllegalFPUInstr_FCvtInt
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7'b0000111: case(Funct3D)
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3'b010: ControlsD = `FCTRLW'b1_0_10_xx_0xx_0_0; // flw
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3'b011: if (`D_SUPPORTED) ControlsD = `FCTRLW'b1_0_10_xx_0xx_0_0; // fld
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else ControlsD = `FCTRLW'b0_0_00_xx_0xx_0_1; // fld not supported
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3'b100: if (`Q_SUPPORTED) ControlsD = `FCTRLW'b1_0_10_xx_0xx_0_0; // flq
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else ControlsD = `FCTRLW'b0_0_00_xx_0xx_0_1; // flq not supported
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3'b001: if (`ZFH_SUPPORTED) ControlsD = `FCTRLW'b1_0_10_xx_0xx_0_0; // flh
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else ControlsD = `FCTRLW'b0_0_00_xx_0xx_0_1; // flh not supported
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default: ControlsD = `FCTRLW'b0_0_00_xx_0xx_0_1; // non-implemented instruction
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3'b010: ControlsD = `FCTRLW'b1_0_10_xx_0xx_0_0_0; // flw
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3'b011: if (`D_SUPPORTED) ControlsD = `FCTRLW'b1_0_10_xx_0xx_0_0_0; // fld
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else ControlsD = `FCTRLW'b0_0_00_xx_0xx_0_1_0; // fld not supported
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3'b100: if (`Q_SUPPORTED) ControlsD = `FCTRLW'b1_0_10_xx_0xx_0_0_0; // flq
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else ControlsD = `FCTRLW'b0_0_00_xx_0xx_0_1_0; // flq not supported
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3'b001: if (`ZFH_SUPPORTED) ControlsD = `FCTRLW'b1_0_10_xx_0xx_0_0_0; // flh
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else ControlsD = `FCTRLW'b0_0_00_xx_0xx_0_1_0; // flh not supported
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default: ControlsD = `FCTRLW'b0_0_00_xx_0xx_0_1_0; // non-implemented instruction
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endcase
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7'b0100111: case(Funct3D)
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3'b010: ControlsD = `FCTRLW'b0_0_10_xx_0xx_0_0; // fsw
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3'b011: if (`D_SUPPORTED) ControlsD = `FCTRLW'b0_0_10_xx_0xx_0_0; // fsd
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else ControlsD = `FCTRLW'b0_0_00_xx_0xx_0_1; // fsd not supported
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3'b100: if (`Q_SUPPORTED) ControlsD = `FCTRLW'b0_0_10_xx_0xx_0_0; // fsq
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else ControlsD = `FCTRLW'b0_0_00_xx_0xx_0_1; // fsq not supported
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3'b001: if (`ZFH_SUPPORTED) ControlsD = `FCTRLW'b0_0_10_xx_0xx_0_0; // fsh
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else ControlsD = `FCTRLW'b0_0_00_xx_0xx_0_1; // fsh not supported
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default: ControlsD = `FCTRLW'b0_0_00_xx_0xx_0_1; // non-implemented instruction
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3'b010: ControlsD = `FCTRLW'b0_0_10_xx_0xx_0_0_0; // fsw
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3'b011: if (`D_SUPPORTED) ControlsD = `FCTRLW'b0_0_10_xx_0xx_0_0_0; // fsd
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else ControlsD = `FCTRLW'b0_0_00_xx_0xx_0_1_0; // fsd not supported
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3'b100: if (`Q_SUPPORTED) ControlsD = `FCTRLW'b0_0_10_xx_0xx_0_0_0; // fsq
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else ControlsD = `FCTRLW'b0_0_00_xx_0xx_0_1_0; // fsq not supported
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3'b001: if (`ZFH_SUPPORTED) ControlsD = `FCTRLW'b0_0_10_xx_0xx_0_0_0; // fsh
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else ControlsD = `FCTRLW'b0_0_00_xx_0xx_0_1_0; // fsh not supported
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default: ControlsD = `FCTRLW'b0_0_00_xx_0xx_0_1_0; // non-implemented instruction
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endcase
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7'b1000011: ControlsD = `FCTRLW'b1_0_01_10_000_0_0; // fmadd
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7'b1000111: ControlsD = `FCTRLW'b1_0_01_10_001_0_0; // fmsub
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7'b1001011: ControlsD = `FCTRLW'b1_0_01_10_010_0_0; // fnmsub
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7'b1001111: ControlsD = `FCTRLW'b1_0_01_10_011_0_0; // fnmadd
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7'b1000011: ControlsD = `FCTRLW'b1_0_01_10_000_0_0_0; // fmadd
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7'b1000111: ControlsD = `FCTRLW'b1_0_01_10_001_0_0_0; // fmsub
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7'b1001011: ControlsD = `FCTRLW'b1_0_01_10_010_0_0_0; // fnmsub
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7'b1001111: ControlsD = `FCTRLW'b1_0_01_10_011_0_0_0; // fnmadd
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7'b1010011: casez(Funct7D)
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7'b00000??: ControlsD = `FCTRLW'b1_0_01_10_110_0_0; // fadd
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7'b00001??: ControlsD = `FCTRLW'b1_0_01_10_111_0_0; // fsub
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7'b00010??: ControlsD = `FCTRLW'b1_0_01_10_100_0_0; // fmul
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7'b00011??: ControlsD = `FCTRLW'b1_0_01_01_xx0_1_0; // fdiv
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7'b01011??: ControlsD = `FCTRLW'b1_0_01_01_xx1_1_0; // fsqrt
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7'b00000??: ControlsD = `FCTRLW'b1_0_01_10_110_0_0_0; // fadd
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7'b00001??: ControlsD = `FCTRLW'b1_0_01_10_111_0_0_0; // fsub
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7'b00010??: ControlsD = `FCTRLW'b1_0_01_10_100_0_0_0; // fmul
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7'b00011??: ControlsD = `FCTRLW'b1_0_01_01_xx0_1_0_0; // fdiv
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7'b01011??: ControlsD = `FCTRLW'b1_0_01_01_xx1_1_0_0; // fsqrt
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7'b00100??: case(Funct3D)
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3'b000: ControlsD = `FCTRLW'b1_0_00_xx_000_0_0; // fsgnj
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3'b001: ControlsD = `FCTRLW'b1_0_00_xx_001_0_0; // fsgnjn
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3'b010: ControlsD = `FCTRLW'b1_0_00_xx_010_0_0; // fsgnjx
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default: ControlsD = `FCTRLW'b0_0_00_xx_0xx_0_1; // non-implemented instruction
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3'b000: ControlsD = `FCTRLW'b1_0_00_xx_000_0_0_0; // fsgnj
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3'b001: ControlsD = `FCTRLW'b1_0_00_xx_001_0_0_0; // fsgnjn
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3'b010: ControlsD = `FCTRLW'b1_0_00_xx_010_0_0_0; // fsgnjx
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default: ControlsD = `FCTRLW'b0_0_00_xx_0xx_0_1_0; // non-implemented instruction
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endcase
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7'b00101??: case(Funct3D)
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3'b000: ControlsD = `FCTRLW'b1_0_00_xx_110_0_0; // fmin
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3'b001: ControlsD = `FCTRLW'b1_0_00_xx_101_0_0; // fmax
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default: ControlsD = `FCTRLW'b0_0_00_xx_0xx_0_1; // non-implemented instruction
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3'b000: ControlsD = `FCTRLW'b1_0_00_xx_110_0_0_0; // fmin
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3'b001: ControlsD = `FCTRLW'b1_0_00_xx_101_0_0_0; // fmax
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default: ControlsD = `FCTRLW'b0_0_00_xx_0xx_0_1_0; // non-implemented instruction
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endcase
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7'b10100??: case(Funct3D)
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3'b010: ControlsD = `FCTRLW'b0_1_00_xx_010_0_0; // feq
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3'b001: ControlsD = `FCTRLW'b0_1_00_xx_001_0_0; // flt
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3'b000: ControlsD = `FCTRLW'b0_1_00_xx_011_0_0; // fle
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default: ControlsD = `FCTRLW'b0_0_00_xx_0xx__0_1; // non-implemented instruction
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3'b010: ControlsD = `FCTRLW'b0_1_00_xx_010_0_0_0; // feq
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3'b001: ControlsD = `FCTRLW'b0_1_00_xx_001_0_0_0; // flt
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3'b000: ControlsD = `FCTRLW'b0_1_00_xx_011_0_0_0; // fle
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default: ControlsD = `FCTRLW'b0_0_00_xx_0xx__0_1_0; // non-implemented instruction
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endcase
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7'b11100??: if (Funct3D == 3'b001) ControlsD = `FCTRLW'b0_1_10_xx_000_0_0; // fclass
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else if (Funct3D[1:0] == 2'b00) ControlsD = `FCTRLW'b0_1_11_xx_000_0_0; // fmv.x.w to int reg
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else if (Funct3D[1:0] == 2'b01) ControlsD = `FCTRLW'b0_1_11_xx_000_0_0; // fmv.x.d to int reg
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else ControlsD = `FCTRLW'b0_0_00_xx_0xx_0_1; // non-implemented instruction
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7'b11100??: if (Funct3D == 3'b001) ControlsD = `FCTRLW'b0_1_10_xx_000_0_0_0; // fclass
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else if (Funct3D[1:0] == 2'b00) ControlsD = `FCTRLW'b0_1_11_xx_000_0_0_0; // fmv.x.w to int reg
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else if (Funct3D[1:0] == 2'b01) ControlsD = `FCTRLW'b0_1_11_xx_000_0_0_0; // fmv.x.d to int reg
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else ControlsD = `FCTRLW'b0_0_00_xx_0xx_0_1_0; // non-implemented instruction
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7'b1101000: case(Rs2D[1:0])
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2'b00: ControlsD = `FCTRLW'b1_0_01_00_101_0_0; // fcvt.s.w w->s
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2'b01: ControlsD = `FCTRLW'b1_0_01_00_100_0_0; // fcvt.s.wu wu->s
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2'b10: ControlsD = `FCTRLW'b1_0_01_00_111_0_0; // fcvt.s.l l->s
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2'b11: ControlsD = `FCTRLW'b1_0_01_00_110_0_0; // fcvt.s.lu lu->s
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2'b00: ControlsD = `FCTRLW'b1_0_01_00_101_0_0_0; // fcvt.s.w w->s
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2'b01: ControlsD = `FCTRLW'b1_0_01_00_100_0_0_0; // fcvt.s.wu wu->s
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2'b10: ControlsD = `FCTRLW'b1_0_01_00_111_0_0_0; // fcvt.s.l l->s
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2'b11: ControlsD = `FCTRLW'b1_0_01_00_110_0_0_0; // fcvt.s.lu lu->s
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endcase
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7'b1100000: case(Rs2D[1:0])
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2'b00: ControlsD = `FCTRLW'b0_1_01_00_001_0_0; // fcvt.w.s s->w
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2'b01: ControlsD = `FCTRLW'b0_1_01_00_000_0_0; // fcvt.wu.s s->wu
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2'b10: ControlsD = `FCTRLW'b0_1_01_00_011_0_0; // fcvt.l.s s->l
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2'b11: ControlsD = `FCTRLW'b0_1_01_00_010_0_0; // fcvt.lu.s s->lu
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2'b00: ControlsD = `FCTRLW'b0_1_01_00_001_0_0_1; // fcvt.w.s s->w
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2'b01: ControlsD = `FCTRLW'b0_1_01_00_000_0_0_1; // fcvt.wu.s s->wu
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2'b10: ControlsD = `FCTRLW'b0_1_01_00_011_0_0_1; // fcvt.l.s s->l
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2'b11: ControlsD = `FCTRLW'b0_1_01_00_010_0_0_1; // fcvt.lu.s s->lu
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endcase
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7'b1111000: ControlsD = `FCTRLW'b1_0_00_xx_011_0_0; // fmv.w.x to fp reg
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7'b0100000: ControlsD = `FCTRLW'b1_0_01_00_000_0_0; // fcvt.s.d
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7'b1111000: ControlsD = `FCTRLW'b1_0_00_xx_011_0_0_0; // fmv.w.x to fp reg
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7'b0100000: ControlsD = `FCTRLW'b1_0_01_00_000_0_0_0; // fcvt.s.d
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7'b1101001: case(Rs2D[1:0])
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2'b00: ControlsD = `FCTRLW'b1_0_01_00_101_0_0; // fcvt.d.w w->d
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2'b01: ControlsD = `FCTRLW'b1_0_01_00_100_0_0; // fcvt.d.wu wu->d
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2'b10: ControlsD = `FCTRLW'b1_0_01_00_111_0_0; // fcvt.d.l l->d
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2'b11: ControlsD = `FCTRLW'b1_0_01_00_110_0_0; // fcvt.d.lu lu->d
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2'b00: ControlsD = `FCTRLW'b1_0_01_00_101_0_0_0; // fcvt.d.w w->d
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2'b01: ControlsD = `FCTRLW'b1_0_01_00_100_0_0_0; // fcvt.d.wu wu->d
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2'b10: ControlsD = `FCTRLW'b1_0_01_00_111_0_0_0; // fcvt.d.l l->d
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2'b11: ControlsD = `FCTRLW'b1_0_01_00_110_0_0_0; // fcvt.d.lu lu->d
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endcase
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7'b1100001: case(Rs2D[1:0])
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2'b00: ControlsD = `FCTRLW'b0_1_01_00_001_0_0; // fcvt.w.d d->w
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2'b01: ControlsD = `FCTRLW'b0_1_01_00_000_0_0; // fcvt.wu.d d->wu
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2'b10: ControlsD = `FCTRLW'b0_1_01_00_011_0_0; // fcvt.l.d d->l
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2'b11: ControlsD = `FCTRLW'b0_1_01_00_010_0_0; // fcvt.lu.d d->lu
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2'b00: ControlsD = `FCTRLW'b0_1_01_00_001_0_0_1; // fcvt.w.d d->w
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2'b01: ControlsD = `FCTRLW'b0_1_01_00_000_0_0_1; // fcvt.wu.d d->wu
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2'b10: ControlsD = `FCTRLW'b0_1_01_00_011_0_0_1; // fcvt.l.d d->l
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2'b11: ControlsD = `FCTRLW'b0_1_01_00_010_0_0_1; // fcvt.lu.d d->lu
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endcase
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7'b1111001: ControlsD = `FCTRLW'b1_0_00_xx_011_0_0; // fmv.d.x to fp reg
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7'b0100001: ControlsD = `FCTRLW'b1_0_01_00_001_0_0; // fcvt.d.s
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default: ControlsD = `FCTRLW'b0_0_00_xx_0xx_0_1; // non-implemented instruction
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7'b1111001: ControlsD = `FCTRLW'b1_0_00_xx_011_0_0_0; // fmv.d.x to fp reg
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7'b0100001: ControlsD = `FCTRLW'b1_0_01_00_001_0_0_0; // fcvt.d.s
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default: ControlsD = `FCTRLW'b0_0_00_xx_0xx_0_1_0; // non-implemented instruction
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endcase
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default: ControlsD = `FCTRLW'b0_0_00_xx_0xx_0_1; // non-implemented instruction
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default: ControlsD = `FCTRLW'b0_0_00_xx_0xx_0_1_0; // non-implemented instruction
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endcase
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// unswizzle control bits
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assign {FRegWriteD, FWriteIntD, FResSelD, PostProcSelD, OpCtrlD, FDivStartD, IllegalFPUInstrD} = ControlsD;
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assign #1 {FRegWriteD, FWriteIntD, FResSelD, PostProcSelD, OpCtrlD, FDivStartD, IllegalFPUInstrD, FCvtIntD} = ControlsD;
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// rounding modes:
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// 000 - round to nearest, ties to even
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@ -260,26 +261,26 @@ module fctrl (
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// 10 - xor sign
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// D/E pipleine register
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flopenrc #(13+`FMTBITS) DECtrlReg3(clk, reset, FlushE, ~StallE,
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{FRegWriteD, PostProcSelD, FResSelD, FrmD, FmtD, OpCtrlD, FWriteIntD, IllegalFPUInstrD},
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{FRegWriteE, PostProcSelE, FResSelE, FrmE, FmtE, OpCtrlE, FWriteIntE, IllegalFPUInstrE});
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flopenrc #(14+`FMTBITS) DECtrlReg3(clk, reset, FlushE, ~StallE,
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{FRegWriteD, PostProcSelD, FResSelD, FrmD, FmtD, OpCtrlD, FWriteIntD, IllegalFPUInstrD, FCvtIntD},
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{FRegWriteE, PostProcSelE, FResSelE, FrmE, FmtE, OpCtrlE, FWriteIntE, IllegalFPUInstrE, FCvtIntE});
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flopenrc #(15) DEAdrReg(clk, reset, FlushE, ~StallE, {InstrD[19:15], InstrD[24:20], InstrD[31:27]},
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{Adr1E, Adr2E, Adr3E});
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flopenrc #(1) DEFDivStartReg(clk, reset, FlushE, ~StallE|FDivBusyE, FDivStartD, FDivStartE);
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if (`M_SUPPORTED) assign IDivStartE = MDUE & Funct3E[2];
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else assign IDivStartE = 0;
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assign FCvtIntE = (FResSelE == 2'b01);
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//assign FCvtIntE = (FResSelE == 2'b01);
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// E/M pipleine register
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flopenrc #(13+int'(`FMTBITS)) EMCtrlReg (clk, reset, FlushM, ~StallM,
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{FRegWriteE, FResSelE, PostProcSelE, FrmE, FmtE, OpCtrlE, FWriteIntE, IllegalFPUInstrE},
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{FRegWriteM, FResSelM, PostProcSelM, FrmM, FmtM, OpCtrlM, FWriteIntM, IllegalFPUInstrM});
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flopenrc #(14+int'(`FMTBITS)) EMCtrlReg (clk, reset, FlushM, ~StallM,
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{FRegWriteE, FResSelE, PostProcSelE, FrmE, FmtE, OpCtrlE, FWriteIntE, IllegalFPUInstrE, FCvtIntE},
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{FRegWriteM, FResSelM, PostProcSelM, FrmM, FmtM, OpCtrlM, FWriteIntM, IllegalFPUInstrM, FCvtIntM});
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// M/W pipleine register
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flopenrc #(3) MWCtrlReg(clk, reset, FlushW, ~StallW,
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{FRegWriteM, FResSelM},
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{FRegWriteW, FResSelW});
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flopenrc #(4) MWCtrlReg(clk, reset, FlushW, ~StallW,
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{FRegWriteM, FResSelM, FCvtIntM},
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{FRegWriteW, FResSelW, FCvtIntW});
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assign FCvtIntW = (FResSelW == 2'b01);
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//assign FCvtIntW = (FResSelW == 2'b01);
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endmodule
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