forked from Github_Repos/cvw
Forced to go back to hard coded preload.
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@ -58,10 +58,59 @@ module bram2p1r1w
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logic [DATA_WIDTH-1:0] RAM [(2**ADDR_WIDTH)-1:0];
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integer i;
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/* -----\/----- EXCLUDED -----\/-----
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initial begin
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if(PRELOAD_ENABLED)
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$readmemh(PRELOAD_FILE, RAM);
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end
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-----/\----- EXCLUDED -----/\----- */
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initial begin
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if(PRELOAD_ENABLED) begin
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RAM[0] = 64'h94e1819300002197;
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RAM[1] = 64'h4281420141014081;
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RAM[2] = 64'h4481440143814301;
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RAM[3] = 64'h4681460145814501;
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RAM[4] = 64'h4881480147814701;
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RAM[5] = 64'h4a814a0149814901;
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RAM[6] = 64'h4c814c014b814b01;
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RAM[7] = 64'h4e814e014d814d01;
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RAM[8] = 64'h0110011b4f814f01;
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RAM[9] = 64'h059b45011161016e;
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RAM[10] = 64'h0004063705fe0010;
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RAM[11] = 64'h05a000ef8006061b;
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RAM[12] = 64'h0ff003930000100f;
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RAM[13] = 64'h4e952e3110060e37;
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RAM[14] = 64'hc602829b0053f2b7;
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RAM[15] = 64'h2023fe02dfe312fd;
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RAM[16] = 64'h829b0053f2b7007e;
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RAM[17] = 64'hfe02dfe312fdc602;
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RAM[18] = 64'h4de31efd000e2023;
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RAM[19] = 64'h059bf1402573fdd0;
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RAM[20] = 64'h0000061705e20870;
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RAM[21] = 64'h0010029b01260613;
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RAM[22] = 64'h11010002806702fe;
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RAM[23] = 64'h84b2842ae426e822;
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RAM[24] = 64'h892ee04aec064505;
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RAM[25] = 64'h06e000ef07e000ef;
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RAM[26] = 64'h979334fd02905563;
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RAM[27] = 64'h07930177d4930204;
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RAM[28] = 64'h4089093394be2004;
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RAM[29] = 64'h04138522008905b3;
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RAM[30] = 64'h19e3014000ef2004;
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RAM[31] = 64'h64a2644260e2fe94;
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RAM[32] = 64'h6749808261056902;
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RAM[33] = 64'hdfed8b8510472783;
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RAM[34] = 64'h2423479110a73823;
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RAM[35] = 64'h10472783674910f7;
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RAM[36] = 64'h20058693ffed8b89;
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RAM[37] = 64'h05a1118737836749;
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RAM[38] = 64'hfed59be3fef5bc23;
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RAM[39] = 64'h1047278367498082;
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RAM[40] = 64'h67c98082dfed8b85;
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RAM[41] = 64'h0000808210a7a023;
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end
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end
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// Port-A Operation
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always @ (posedge clk) begin
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