forked from Github_Repos/cvw
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
This commit is contained in:
Ross Thompson
commit
8af055c78e
21
linux/buildroot-scripts/Makefile
Normal file
21
linux/buildroot-scripts/Makefile
Normal file
@ -0,0 +1,21 @@
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all:
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make disassemble
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make generate
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generate:
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# generating device tree binary
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dtc -I dts -O dtb ../devicetree/wally-virt.dts > ${RISCV}/buildroot/output/images/wally-virt.dtb
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disassemble:
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mkdir ${RISCV}/buildroot/output/images/disassembly
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# fw_jump
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riscv64-unknown-elf-objdump -D ${RISCV}/buildroot/output/images/fw_jump.elf >> ${RISCV}/buildroot/output/images/disassembly/fw_jump.objdump
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# vmlinux
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riscv64-unknown-elf-objdump -D ${RISCV}/buildroot/output/images/vmlinux >> ${RISCV}/buildroot/output/images/disassembly/vmlinux.objdump
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# filesystem
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mkdir ${RISCV}/buildroot/output/images/disassembly/rootfs
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-cd ${RISCV}/buildroot/output/images/disassembly/rootfs; cpio -idv < ../../rootfs.cpio
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clean:
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rm ${RISCV}/buildroot/output/images/wally-virt.dtb
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rm -rf ${RISCV}/buildroot/output/images/disassembly
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@ -262,10 +262,6 @@ module hptw
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UPDATE_PTE: if(`HPTW_WRITES_SUPPORTED & DCacheStallM) NextWalkerState = UPDATE_PTE;
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else NextWalkerState = LEAF;
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default: begin
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// synthesis translate_off
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if (WalkerState !== 'x)
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$error("Default state in HPTW should be unreachable; was %d", WalkerState);
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// synthesis translate_on
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NextWalkerState = IDLE; // should never be reached
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end
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endcase
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@ -1489,7 +1489,10 @@ string imperas32f[] = '{
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"rv64i_m/privilege/WALLY-PMA", "40A0",
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"rv64i_m/privilege/WALLY-minfo-01", "40A0",
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"rv64i_m/privilege/WALLY-CSR-permission-s-01", "50A0",
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"rv64i_m/privilege/WALLY-CSR-permission-u-01", "50A0"
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"rv64i_m/privilege/WALLY-CSR-permission-u-01", "50A0",
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"rv64i_m/privilege/WALLY-misa-01", "40A0",
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"rv64i_m/privilege/WALLY-scratch-01", "40A0",
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"rv64i_m/privilege/WALLY-sscratch-s-01", "40A0"
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};
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string wally64periph[] = '{
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@ -1550,9 +1553,13 @@ string wally32i[] = '{
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`WALLYTEST,
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"rv32i_m/privilege/WALLY-MMU-SV32", "4080",
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"rv32i_m/privilege/WALLY-PMP", "4080",
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"rv32i_m/privilege/WALLY-PMA", "4080",
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"rv32i_m/privilege/WALLY-CSR-permission-s-01", "5080",
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"rv32i_m/privilege/WALLY-CSR-permission-u-01", "5080",
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"rv32i_m/privilege/WALLY-minfo-01", "4080"
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"rv32i_m/privilege/WALLY-minfo-01", "4080",
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"rv32i_m/privilege/WALLY-misa-01", "4080",
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"rv32i_m/privilege/WALLY-scratch-01", "4080",
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"rv32i_m/privilege/WALLY-sscratch-s-01", "4080"
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};
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string wally32periph[] = '{
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@ -32,7 +32,10 @@ rv32i_sc_tests = \
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WALLY-PMP \
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WALLY-CSR-permission-s-01 \
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WALLY-CSR-permission-u-01 \
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WALLY-minfo-01
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WALLY-minfo-01 \
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WALLY-misa-01 \
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WALLY-scratch-01 \
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WALLY-sscratch-s-01
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target_tests_nosim = WALLY-PMA \
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File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@ -34,161 +34,161 @@ s_file_begin:
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||||
GOTO_S_MODE 0x0, 0x0
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# Attempt to write 0xbad to each of these CSRs and read the value back
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# Attempt to write 0x111 to each of these CSRs and read the value back
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||||
# should result in an illegal instruction for the write and read, respectively
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||||
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||||
# High-bit versions storing the upper 32 bits of some CSRs for RV32
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||||
# WRITE_READ_CSR mstatush 0xbad # *** these appear not to be implemented in GCC
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||||
# WRITE_READ_CSR menvcfgh 0xbad
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# WRITE_READ_CSR mseccfgh 0xbad
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WRITE_READ_CSR pmpcfg1 0xbad
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WRITE_READ_CSR pmpcfg3 0xbad
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WRITE_READ_CSR mcycleh 0xbad
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WRITE_READ_CSR minstreth 0xbad
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WRITE_READ_CSR mhpmcounter3h 0xbad
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WRITE_READ_CSR mhpmcounter4h 0xbad
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||||
WRITE_READ_CSR mhpmcounter5h 0xbad
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||||
WRITE_READ_CSR mhpmcounter6h 0xbad
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WRITE_READ_CSR mhpmcounter7h 0xbad
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WRITE_READ_CSR mhpmcounter8h 0xbad
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||||
WRITE_READ_CSR mhpmcounter9h 0xbad
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||||
WRITE_READ_CSR mhpmcounter10h 0xbad
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||||
WRITE_READ_CSR mhpmcounter11h 0xbad
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||||
WRITE_READ_CSR mhpmcounter12h 0xbad
|
||||
WRITE_READ_CSR mhpmcounter13h 0xbad
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||||
WRITE_READ_CSR mhpmcounter14h 0xbad
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||||
WRITE_READ_CSR mhpmcounter15h 0xbad
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||||
WRITE_READ_CSR mhpmcounter16h 0xbad
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||||
WRITE_READ_CSR mhpmcounter17h 0xbad
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||||
WRITE_READ_CSR mhpmcounter18h 0xbad
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||||
WRITE_READ_CSR mhpmcounter19h 0xbad
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||||
WRITE_READ_CSR mhpmcounter20h 0xbad
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WRITE_READ_CSR mhpmcounter21h 0xbad
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||||
WRITE_READ_CSR mhpmcounter22h 0xbad
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||||
WRITE_READ_CSR mhpmcounter23h 0xbad
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||||
WRITE_READ_CSR mhpmcounter24h 0xbad
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||||
WRITE_READ_CSR mhpmcounter25h 0xbad
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||||
WRITE_READ_CSR mhpmcounter26h 0xbad
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||||
WRITE_READ_CSR mhpmcounter27h 0xbad
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||||
WRITE_READ_CSR mhpmcounter28h 0xbad
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||||
WRITE_READ_CSR mhpmcounter29h 0xbad
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||||
WRITE_READ_CSR mhpmcounter30h 0xbad
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WRITE_READ_CSR mhpmcounter31h 0xbad
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# WRITE_READ_CSR mstatush 0x111 # *** these appear not to be implemented in GCC
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# WRITE_READ_CSR menvcfgh 0x111
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# WRITE_READ_CSR mseccfgh 0x111
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WRITE_READ_CSR pmpcfg1 0x111
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WRITE_READ_CSR pmpcfg3 0x111
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WRITE_READ_CSR mcycleh 0x111
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WRITE_READ_CSR minstreth 0x111
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WRITE_READ_CSR mhpmcounter3h 0x111
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||||
WRITE_READ_CSR mhpmcounter4h 0x111
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||||
WRITE_READ_CSR mhpmcounter5h 0x111
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WRITE_READ_CSR mhpmcounter6h 0x111
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WRITE_READ_CSR mhpmcounter7h 0x111
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||||
WRITE_READ_CSR mhpmcounter8h 0x111
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||||
WRITE_READ_CSR mhpmcounter9h 0x111
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||||
WRITE_READ_CSR mhpmcounter10h 0x111
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WRITE_READ_CSR mhpmcounter11h 0x111
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WRITE_READ_CSR mhpmcounter12h 0x111
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||||
WRITE_READ_CSR mhpmcounter13h 0x111
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||||
WRITE_READ_CSR mhpmcounter14h 0x111
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||||
WRITE_READ_CSR mhpmcounter15h 0x111
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||||
WRITE_READ_CSR mhpmcounter16h 0x111
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WRITE_READ_CSR mhpmcounter17h 0x111
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WRITE_READ_CSR mhpmcounter18h 0x111
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WRITE_READ_CSR mhpmcounter19h 0x111
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||||
WRITE_READ_CSR mhpmcounter20h 0x111
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WRITE_READ_CSR mhpmcounter21h 0x111
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WRITE_READ_CSR mhpmcounter22h 0x111
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||||
WRITE_READ_CSR mhpmcounter23h 0x111
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||||
WRITE_READ_CSR mhpmcounter24h 0x111
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WRITE_READ_CSR mhpmcounter25h 0x111
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||||
WRITE_READ_CSR mhpmcounter26h 0x111
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WRITE_READ_CSR mhpmcounter27h 0x111
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WRITE_READ_CSR mhpmcounter28h 0x111
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WRITE_READ_CSR mhpmcounter29h 0x111
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WRITE_READ_CSR mhpmcounter30h 0x111
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WRITE_READ_CSR mhpmcounter31h 0x111
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# Machine information Registers
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WRITE_READ_CSR mvendorid, 0xbad
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WRITE_READ_CSR marchid, 0xbad
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WRITE_READ_CSR mimpid, 0xbad
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WRITE_READ_CSR mhartid, 0xbad
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# WRITE_READ_CSR mconfigptr, 0xbad # mconfigptr unimplemented in spike as of 31 Jan 22
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WRITE_READ_CSR mvendorid, 0x111
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WRITE_READ_CSR marchid, 0x111
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WRITE_READ_CSR mimpid, 0x111
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WRITE_READ_CSR mhartid, 0x111
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# WRITE_READ_CSR mconfigptr, 0x111 # mconfigptr unimplemented in spike as of 31 Jan 22
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# Machine Trap Setup
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WRITE_READ_CSR mstatus, 0xbad
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WRITE_READ_CSR misa, 0xbad
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WRITE_READ_CSR medeleg, 0xbad
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WRITE_READ_CSR mideleg, 0xbad
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WRITE_READ_CSR mie, 0xbad
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WRITE_READ_CSR mtvec, 0xbad
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WRITE_READ_CSR mcounteren, 0xbad
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WRITE_READ_CSR mstatus, 0x111
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WRITE_READ_CSR misa, 0x111
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WRITE_READ_CSR medeleg, 0x111
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WRITE_READ_CSR mideleg, 0x111
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WRITE_READ_CSR mie, 0x111
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WRITE_READ_CSR mtvec, 0x111
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WRITE_READ_CSR mcounteren, 0x111
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# Machine Trap Handling
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WRITE_READ_CSR mscratch, 0xbad
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WRITE_READ_CSR mepc, 0xbad
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WRITE_READ_CSR mcause, 0xbad
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WRITE_READ_CSR mtval, 0xbad
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WRITE_READ_CSR mip, 0xbad
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# WRITE_READ_CSR mtinst, 0xbad # *** these appear not to be implemented in GCC
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# WRITE_READ_CSR mtval2, 0xbad
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WRITE_READ_CSR mscratch, 0x111
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WRITE_READ_CSR mepc, 0x111
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WRITE_READ_CSR mcause, 0x111
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WRITE_READ_CSR mtval, 0x111
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WRITE_READ_CSR mip, 0x111
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# WRITE_READ_CSR mtinst, 0x111 # *** these appear not to be implemented in GCC
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# WRITE_READ_CSR mtval2, 0x111
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# Machine Configuration
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# WRITE_READ_CSR menvcfg, 0xbad # *** these appear not to be implemented in GCC
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# WRITE_READ_CSR mseccgf, 0xbad
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# WRITE_READ_CSR menvcfg, 0x111 # *** these appear not to be implemented in GCC
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# WRITE_READ_CSR mseccgf, 0x111
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# Machine Memory Protection
|
||||
WRITE_READ_CSR pmpcfg0, 0xbad
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WRITE_READ_CSR pmpcfg2, 0xbad # there's 1 pmpcfg reg per 8 pmpaddr regs
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WRITE_READ_CSR pmpcfg0, 0x111
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WRITE_READ_CSR pmpcfg2, 0x111 # there's 1 pmpcfg reg per 8 pmpaddr regs
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|
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WRITE_READ_CSR pmpaddr0, 0xbad
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WRITE_READ_CSR pmpaddr1, 0xbad
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||||
WRITE_READ_CSR pmpaddr2, 0xbad
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WRITE_READ_CSR pmpaddr3, 0xbad
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||||
WRITE_READ_CSR pmpaddr4, 0xbad
|
||||
WRITE_READ_CSR pmpaddr5, 0xbad
|
||||
WRITE_READ_CSR pmpaddr6, 0xbad
|
||||
WRITE_READ_CSR pmpaddr7, 0xbad
|
||||
WRITE_READ_CSR pmpaddr8, 0xbad
|
||||
WRITE_READ_CSR pmpaddr9, 0xbad
|
||||
WRITE_READ_CSR pmpaddr10, 0xbad
|
||||
WRITE_READ_CSR pmpaddr11, 0xbad
|
||||
WRITE_READ_CSR pmpaddr12, 0xbad
|
||||
WRITE_READ_CSR pmpaddr13, 0xbad
|
||||
WRITE_READ_CSR pmpaddr14, 0xbad
|
||||
WRITE_READ_CSR pmpaddr15, 0xbad # only pmpcfg0...15 are enabled in our config
|
||||
WRITE_READ_CSR pmpaddr0, 0x111
|
||||
WRITE_READ_CSR pmpaddr1, 0x111
|
||||
WRITE_READ_CSR pmpaddr2, 0x111
|
||||
WRITE_READ_CSR pmpaddr3, 0x111
|
||||
WRITE_READ_CSR pmpaddr4, 0x111
|
||||
WRITE_READ_CSR pmpaddr5, 0x111
|
||||
WRITE_READ_CSR pmpaddr6, 0x111
|
||||
WRITE_READ_CSR pmpaddr7, 0x111
|
||||
WRITE_READ_CSR pmpaddr8, 0x111
|
||||
WRITE_READ_CSR pmpaddr9, 0x111
|
||||
WRITE_READ_CSR pmpaddr10, 0x111
|
||||
WRITE_READ_CSR pmpaddr11, 0x111
|
||||
WRITE_READ_CSR pmpaddr12, 0x111
|
||||
WRITE_READ_CSR pmpaddr13, 0x111
|
||||
WRITE_READ_CSR pmpaddr14, 0x111
|
||||
WRITE_READ_CSR pmpaddr15, 0x111 # only pmpcfg0...15 are enabled in our config
|
||||
|
||||
# Machine Counter/Timers
|
||||
WRITE_READ_CSR mcycle, 0xbad
|
||||
WRITE_READ_CSR minstret, 0xbad
|
||||
WRITE_READ_CSR mhpmcounter3, 0xbad
|
||||
WRITE_READ_CSR mhpmcounter4, 0xbad
|
||||
WRITE_READ_CSR mhpmcounter5, 0xbad
|
||||
WRITE_READ_CSR mhpmcounter6, 0xbad
|
||||
WRITE_READ_CSR mhpmcounter7, 0xbad
|
||||
WRITE_READ_CSR mhpmcounter8, 0xbad
|
||||
WRITE_READ_CSR mhpmcounter9, 0xbad
|
||||
WRITE_READ_CSR mhpmcounter10, 0xbad
|
||||
WRITE_READ_CSR mhpmcounter11, 0xbad
|
||||
WRITE_READ_CSR mhpmcounter12, 0xbad
|
||||
WRITE_READ_CSR mhpmcounter13, 0xbad
|
||||
WRITE_READ_CSR mhpmcounter14, 0xbad
|
||||
WRITE_READ_CSR mhpmcounter15, 0xbad
|
||||
WRITE_READ_CSR mhpmcounter16, 0xbad
|
||||
WRITE_READ_CSR mhpmcounter17, 0xbad
|
||||
WRITE_READ_CSR mhpmcounter18, 0xbad
|
||||
WRITE_READ_CSR mhpmcounter19, 0xbad
|
||||
WRITE_READ_CSR mhpmcounter20, 0xbad
|
||||
WRITE_READ_CSR mhpmcounter21, 0xbad
|
||||
WRITE_READ_CSR mhpmcounter22, 0xbad
|
||||
WRITE_READ_CSR mhpmcounter23, 0xbad
|
||||
WRITE_READ_CSR mhpmcounter24, 0xbad
|
||||
WRITE_READ_CSR mhpmcounter25, 0xbad
|
||||
WRITE_READ_CSR mhpmcounter26, 0xbad
|
||||
WRITE_READ_CSR mhpmcounter27, 0xbad
|
||||
WRITE_READ_CSR mhpmcounter28, 0xbad
|
||||
WRITE_READ_CSR mhpmcounter29, 0xbad
|
||||
WRITE_READ_CSR mhpmcounter30, 0xbad
|
||||
WRITE_READ_CSR mhpmcounter31, 0xbad
|
||||
WRITE_READ_CSR mcycle, 0x111
|
||||
WRITE_READ_CSR minstret, 0x111
|
||||
WRITE_READ_CSR mhpmcounter3, 0x111
|
||||
WRITE_READ_CSR mhpmcounter4, 0x111
|
||||
WRITE_READ_CSR mhpmcounter5, 0x111
|
||||
WRITE_READ_CSR mhpmcounter6, 0x111
|
||||
WRITE_READ_CSR mhpmcounter7, 0x111
|
||||
WRITE_READ_CSR mhpmcounter8, 0x111
|
||||
WRITE_READ_CSR mhpmcounter9, 0x111
|
||||
WRITE_READ_CSR mhpmcounter10, 0x111
|
||||
WRITE_READ_CSR mhpmcounter11, 0x111
|
||||
WRITE_READ_CSR mhpmcounter12, 0x111
|
||||
WRITE_READ_CSR mhpmcounter13, 0x111
|
||||
WRITE_READ_CSR mhpmcounter14, 0x111
|
||||
WRITE_READ_CSR mhpmcounter15, 0x111
|
||||
WRITE_READ_CSR mhpmcounter16, 0x111
|
||||
WRITE_READ_CSR mhpmcounter17, 0x111
|
||||
WRITE_READ_CSR mhpmcounter18, 0x111
|
||||
WRITE_READ_CSR mhpmcounter19, 0x111
|
||||
WRITE_READ_CSR mhpmcounter20, 0x111
|
||||
WRITE_READ_CSR mhpmcounter21, 0x111
|
||||
WRITE_READ_CSR mhpmcounter22, 0x111
|
||||
WRITE_READ_CSR mhpmcounter23, 0x111
|
||||
WRITE_READ_CSR mhpmcounter24, 0x111
|
||||
WRITE_READ_CSR mhpmcounter25, 0x111
|
||||
WRITE_READ_CSR mhpmcounter26, 0x111
|
||||
WRITE_READ_CSR mhpmcounter27, 0x111
|
||||
WRITE_READ_CSR mhpmcounter28, 0x111
|
||||
WRITE_READ_CSR mhpmcounter29, 0x111
|
||||
WRITE_READ_CSR mhpmcounter30, 0x111
|
||||
WRITE_READ_CSR mhpmcounter31, 0x111
|
||||
|
||||
# Machine Counter Setup
|
||||
WRITE_READ_CSR mcountinhibit, 0xbad
|
||||
WRITE_READ_CSR mhpmevent3, 0xbad
|
||||
WRITE_READ_CSR mhpmevent4, 0xbad
|
||||
WRITE_READ_CSR mhpmevent5, 0xbad
|
||||
WRITE_READ_CSR mhpmevent6, 0xbad
|
||||
WRITE_READ_CSR mhpmevent7, 0xbad
|
||||
WRITE_READ_CSR mhpmevent8, 0xbad
|
||||
WRITE_READ_CSR mhpmevent9, 0xbad
|
||||
WRITE_READ_CSR mhpmevent10, 0xbad
|
||||
WRITE_READ_CSR mhpmevent11, 0xbad
|
||||
WRITE_READ_CSR mhpmevent12, 0xbad
|
||||
WRITE_READ_CSR mhpmevent13, 0xbad
|
||||
WRITE_READ_CSR mhpmevent14, 0xbad
|
||||
WRITE_READ_CSR mhpmevent15, 0xbad
|
||||
WRITE_READ_CSR mhpmevent16, 0xbad
|
||||
WRITE_READ_CSR mhpmevent17, 0xbad
|
||||
WRITE_READ_CSR mhpmevent18, 0xbad
|
||||
WRITE_READ_CSR mhpmevent19, 0xbad
|
||||
WRITE_READ_CSR mhpmevent20, 0xbad
|
||||
WRITE_READ_CSR mhpmevent21, 0xbad
|
||||
WRITE_READ_CSR mhpmevent22, 0xbad
|
||||
WRITE_READ_CSR mhpmevent23, 0xbad
|
||||
WRITE_READ_CSR mhpmevent24, 0xbad
|
||||
WRITE_READ_CSR mhpmevent25, 0xbad
|
||||
WRITE_READ_CSR mhpmevent26, 0xbad
|
||||
WRITE_READ_CSR mhpmevent27, 0xbad
|
||||
WRITE_READ_CSR mhpmevent28, 0xbad
|
||||
WRITE_READ_CSR mhpmevent29, 0xbad
|
||||
WRITE_READ_CSR mhpmevent30, 0xbad
|
||||
WRITE_READ_CSR mhpmevent31, 0xbad
|
||||
WRITE_READ_CSR mcountinhibit, 0x111
|
||||
WRITE_READ_CSR mhpmevent3, 0x111
|
||||
WRITE_READ_CSR mhpmevent4, 0x111
|
||||
WRITE_READ_CSR mhpmevent5, 0x111
|
||||
WRITE_READ_CSR mhpmevent6, 0x111
|
||||
WRITE_READ_CSR mhpmevent7, 0x111
|
||||
WRITE_READ_CSR mhpmevent8, 0x111
|
||||
WRITE_READ_CSR mhpmevent9, 0x111
|
||||
WRITE_READ_CSR mhpmevent10, 0x111
|
||||
WRITE_READ_CSR mhpmevent11, 0x111
|
||||
WRITE_READ_CSR mhpmevent12, 0x111
|
||||
WRITE_READ_CSR mhpmevent13, 0x111
|
||||
WRITE_READ_CSR mhpmevent14, 0x111
|
||||
WRITE_READ_CSR mhpmevent15, 0x111
|
||||
WRITE_READ_CSR mhpmevent16, 0x111
|
||||
WRITE_READ_CSR mhpmevent17, 0x111
|
||||
WRITE_READ_CSR mhpmevent18, 0x111
|
||||
WRITE_READ_CSR mhpmevent19, 0x111
|
||||
WRITE_READ_CSR mhpmevent20, 0x111
|
||||
WRITE_READ_CSR mhpmevent21, 0x111
|
||||
WRITE_READ_CSR mhpmevent22, 0x111
|
||||
WRITE_READ_CSR mhpmevent23, 0x111
|
||||
WRITE_READ_CSR mhpmevent24, 0x111
|
||||
WRITE_READ_CSR mhpmevent25, 0x111
|
||||
WRITE_READ_CSR mhpmevent26, 0x111
|
||||
WRITE_READ_CSR mhpmevent27, 0x111
|
||||
WRITE_READ_CSR mhpmevent28, 0x111
|
||||
WRITE_READ_CSR mhpmevent29, 0x111
|
||||
WRITE_READ_CSR mhpmevent30, 0x111
|
||||
WRITE_READ_CSR mhpmevent31, 0x111
|
||||
|
||||
END_TESTS
|
||||
|
||||
|
||||
@ -31,142 +31,142 @@ s_file_begin:
|
||||
|
||||
GOTO_U_MODE 0x0, 0x0
|
||||
|
||||
# Attempt to write 0xbad to each of these CSRs and read the value back
|
||||
# Attempt to write 0xAAA to each of these CSRs and read the value back
|
||||
# should result in an illegal instruction for the write and read, respectively
|
||||
|
||||
# Supervisor Trap Setup
|
||||
WRITE_READ_CSR sstatus, 0xbad
|
||||
WRITE_READ_CSR sie, 0xbad
|
||||
WRITE_READ_CSR stvec, 0xbad
|
||||
WRITE_READ_CSR scounteren, 0xbad
|
||||
WRITE_READ_CSR sstatus, 0xAAA
|
||||
WRITE_READ_CSR sie, 0xAAA
|
||||
WRITE_READ_CSR stvec, 0xAAA
|
||||
WRITE_READ_CSR scounteren, 0xAAA
|
||||
|
||||
# Supervisor Configuration
|
||||
# WRITE_READ_CSR senvcfg, 0xbad # *** these appear not to be implemented in the compile step of make???
|
||||
# WRITE_READ_CSR senvcfg, 0xAAA # *** these appear not to be implemented in the compile step of make???
|
||||
|
||||
# Supervisor Trap Handling
|
||||
WRITE_READ_CSR sscratch, 0xbad
|
||||
WRITE_READ_CSR sepc, 0xbad
|
||||
WRITE_READ_CSR scause, 0xbad
|
||||
WRITE_READ_CSR stval, 0xbad
|
||||
WRITE_READ_CSR sip, 0xbad
|
||||
WRITE_READ_CSR sscratch, 0xAAA
|
||||
WRITE_READ_CSR sepc, 0xAAA
|
||||
WRITE_READ_CSR scause, 0xAAA
|
||||
WRITE_READ_CSR stval, 0xAAA
|
||||
WRITE_READ_CSR sip, 0xAAA
|
||||
|
||||
# Supervisor Protection and Translation
|
||||
WRITE_READ_CSR satp, 0xbad
|
||||
WRITE_READ_CSR satp, 0xAAA
|
||||
|
||||
# Machine information Registers
|
||||
WRITE_READ_CSR mvendorid, 0xbad
|
||||
WRITE_READ_CSR marchid, 0xbad
|
||||
WRITE_READ_CSR mimpid, 0xbad
|
||||
WRITE_READ_CSR mhartid, 0xbad
|
||||
# WRITE_READ_CSR mconfigptr, 0xbad # mconfigptr unimplemented in spike as of 31 Jan 22
|
||||
WRITE_READ_CSR mvendorid, 0xAAA
|
||||
WRITE_READ_CSR marchid, 0xAAA
|
||||
WRITE_READ_CSR mimpid, 0xAAA
|
||||
WRITE_READ_CSR mhartid, 0xAAA
|
||||
# WRITE_READ_CSR mconfigptr, 0xAAA # mconfigptr unimplemented in spike as of 31 Jan 22
|
||||
|
||||
# Machine Trap Setup
|
||||
WRITE_READ_CSR mstatus, 0xbad
|
||||
WRITE_READ_CSR misa, 0xbad
|
||||
WRITE_READ_CSR medeleg, 0xbad
|
||||
WRITE_READ_CSR mideleg, 0xbad
|
||||
WRITE_READ_CSR mie, 0xbad
|
||||
WRITE_READ_CSR mtvec, 0xbad
|
||||
WRITE_READ_CSR mcounteren, 0xbad
|
||||
WRITE_READ_CSR mstatus, 0xAAA
|
||||
WRITE_READ_CSR misa, 0xAAA
|
||||
WRITE_READ_CSR medeleg, 0xAAA
|
||||
WRITE_READ_CSR mideleg, 0xAAA
|
||||
WRITE_READ_CSR mie, 0xAAA
|
||||
WRITE_READ_CSR mtvec, 0xAAA
|
||||
WRITE_READ_CSR mcounteren, 0xAAA
|
||||
|
||||
# Machine Trap Handling
|
||||
WRITE_READ_CSR mscratch, 0xbad
|
||||
WRITE_READ_CSR mepc, 0xbad
|
||||
WRITE_READ_CSR mcause, 0xbad
|
||||
WRITE_READ_CSR mtval, 0xbad
|
||||
WRITE_READ_CSR mip, 0xbad
|
||||
# WRITE_READ_CSR mtinst, 0xbad # *** these appear not to be implemented in GCC
|
||||
# WRITE_READ_CSR mtval2, 0xbad
|
||||
WRITE_READ_CSR mscratch, 0xAAA
|
||||
WRITE_READ_CSR mepc, 0xAAA
|
||||
WRITE_READ_CSR mcause, 0xAAA
|
||||
WRITE_READ_CSR mtval, 0xAAA
|
||||
WRITE_READ_CSR mip, 0xAAA
|
||||
# WRITE_READ_CSR mtinst, 0xAAA # *** these appear not to be implemented in GCC
|
||||
# WRITE_READ_CSR mtval2, 0xAAA
|
||||
|
||||
# Machine Configuration
|
||||
# WRITE_READ_CSR menvcfg, 0xbad # *** these appear not to be implemented in GCC
|
||||
# WRITE_READ_CSR mseccgf, 0xbad
|
||||
# WRITE_READ_CSR menvcfg, 0xAAA # *** these appear not to be implemented in GCC
|
||||
# WRITE_READ_CSR mseccgf, 0xAAA
|
||||
|
||||
# Machine Memory Protection
|
||||
WRITE_READ_CSR pmpcfg0, 0xbad
|
||||
WRITE_READ_CSR pmpcfg2, 0xbad # pmpcfg 1 and 3 dont exist in rv64. there's 1 pmpcfg reg per 8 pmpaddr regs
|
||||
WRITE_READ_CSR pmpcfg0, 0xAAA
|
||||
WRITE_READ_CSR pmpcfg2, 0xAAA # pmpcfg 1 and 3 dont exist in rv64. there's 1 pmpcfg reg per 8 pmpaddr regs
|
||||
|
||||
WRITE_READ_CSR pmpaddr0, 0xbad
|
||||
WRITE_READ_CSR pmpaddr1, 0xbad
|
||||
WRITE_READ_CSR pmpaddr2, 0xbad
|
||||
WRITE_READ_CSR pmpaddr3, 0xbad
|
||||
WRITE_READ_CSR pmpaddr4, 0xbad
|
||||
WRITE_READ_CSR pmpaddr5, 0xbad
|
||||
WRITE_READ_CSR pmpaddr6, 0xbad
|
||||
WRITE_READ_CSR pmpaddr7, 0xbad
|
||||
WRITE_READ_CSR pmpaddr8, 0xbad
|
||||
WRITE_READ_CSR pmpaddr9, 0xbad
|
||||
WRITE_READ_CSR pmpaddr10, 0xbad
|
||||
WRITE_READ_CSR pmpaddr11, 0xbad
|
||||
WRITE_READ_CSR pmpaddr12, 0xbad
|
||||
WRITE_READ_CSR pmpaddr13, 0xbad
|
||||
WRITE_READ_CSR pmpaddr14, 0xbad
|
||||
WRITE_READ_CSR pmpaddr15, 0xbad # only pmpcfg0...15 are enabled in our config
|
||||
WRITE_READ_CSR pmpaddr0, 0xAAA
|
||||
WRITE_READ_CSR pmpaddr1, 0xAAA
|
||||
WRITE_READ_CSR pmpaddr2, 0xAAA
|
||||
WRITE_READ_CSR pmpaddr3, 0xAAA
|
||||
WRITE_READ_CSR pmpaddr4, 0xAAA
|
||||
WRITE_READ_CSR pmpaddr5, 0xAAA
|
||||
WRITE_READ_CSR pmpaddr6, 0xAAA
|
||||
WRITE_READ_CSR pmpaddr7, 0xAAA
|
||||
WRITE_READ_CSR pmpaddr8, 0xAAA
|
||||
WRITE_READ_CSR pmpaddr9, 0xAAA
|
||||
WRITE_READ_CSR pmpaddr10, 0xAAA
|
||||
WRITE_READ_CSR pmpaddr11, 0xAAA
|
||||
WRITE_READ_CSR pmpaddr12, 0xAAA
|
||||
WRITE_READ_CSR pmpaddr13, 0xAAA
|
||||
WRITE_READ_CSR pmpaddr14, 0xAAA
|
||||
WRITE_READ_CSR pmpaddr15, 0xAAA # only pmpcfg0...15 are enabled in our config
|
||||
|
||||
# Machine Counter/Timers
|
||||
WRITE_READ_CSR mcycle, 0xbad
|
||||
WRITE_READ_CSR minstret, 0xbad
|
||||
WRITE_READ_CSR mhpmcounter3, 0xbad
|
||||
WRITE_READ_CSR mhpmcounter4, 0xbad
|
||||
WRITE_READ_CSR mhpmcounter5, 0xbad
|
||||
WRITE_READ_CSR mhpmcounter6, 0xbad
|
||||
WRITE_READ_CSR mhpmcounter7, 0xbad
|
||||
WRITE_READ_CSR mhpmcounter8, 0xbad
|
||||
WRITE_READ_CSR mhpmcounter9, 0xbad
|
||||
WRITE_READ_CSR mhpmcounter10, 0xbad
|
||||
WRITE_READ_CSR mhpmcounter11, 0xbad
|
||||
WRITE_READ_CSR mhpmcounter12, 0xbad
|
||||
WRITE_READ_CSR mhpmcounter13, 0xbad
|
||||
WRITE_READ_CSR mhpmcounter14, 0xbad
|
||||
WRITE_READ_CSR mhpmcounter15, 0xbad
|
||||
WRITE_READ_CSR mhpmcounter16, 0xbad
|
||||
WRITE_READ_CSR mhpmcounter17, 0xbad
|
||||
WRITE_READ_CSR mhpmcounter18, 0xbad
|
||||
WRITE_READ_CSR mhpmcounter19, 0xbad
|
||||
WRITE_READ_CSR mhpmcounter20, 0xbad
|
||||
WRITE_READ_CSR mhpmcounter21, 0xbad
|
||||
WRITE_READ_CSR mhpmcounter22, 0xbad
|
||||
WRITE_READ_CSR mhpmcounter23, 0xbad
|
||||
WRITE_READ_CSR mhpmcounter24, 0xbad
|
||||
WRITE_READ_CSR mhpmcounter25, 0xbad
|
||||
WRITE_READ_CSR mhpmcounter26, 0xbad
|
||||
WRITE_READ_CSR mhpmcounter27, 0xbad
|
||||
WRITE_READ_CSR mhpmcounter28, 0xbad
|
||||
WRITE_READ_CSR mhpmcounter29, 0xbad
|
||||
WRITE_READ_CSR mhpmcounter30, 0xbad
|
||||
WRITE_READ_CSR mhpmcounter31, 0xbad
|
||||
WRITE_READ_CSR mcycle, 0xAAA
|
||||
WRITE_READ_CSR minstret, 0xAAA
|
||||
WRITE_READ_CSR mhpmcounter3, 0xAAA
|
||||
WRITE_READ_CSR mhpmcounter4, 0xAAA
|
||||
WRITE_READ_CSR mhpmcounter5, 0xAAA
|
||||
WRITE_READ_CSR mhpmcounter6, 0xAAA
|
||||
WRITE_READ_CSR mhpmcounter7, 0xAAA
|
||||
WRITE_READ_CSR mhpmcounter8, 0xAAA
|
||||
WRITE_READ_CSR mhpmcounter9, 0xAAA
|
||||
WRITE_READ_CSR mhpmcounter10, 0xAAA
|
||||
WRITE_READ_CSR mhpmcounter11, 0xAAA
|
||||
WRITE_READ_CSR mhpmcounter12, 0xAAA
|
||||
WRITE_READ_CSR mhpmcounter13, 0xAAA
|
||||
WRITE_READ_CSR mhpmcounter14, 0xAAA
|
||||
WRITE_READ_CSR mhpmcounter15, 0xAAA
|
||||
WRITE_READ_CSR mhpmcounter16, 0xAAA
|
||||
WRITE_READ_CSR mhpmcounter17, 0xAAA
|
||||
WRITE_READ_CSR mhpmcounter18, 0xAAA
|
||||
WRITE_READ_CSR mhpmcounter19, 0xAAA
|
||||
WRITE_READ_CSR mhpmcounter20, 0xAAA
|
||||
WRITE_READ_CSR mhpmcounter21, 0xAAA
|
||||
WRITE_READ_CSR mhpmcounter22, 0xAAA
|
||||
WRITE_READ_CSR mhpmcounter23, 0xAAA
|
||||
WRITE_READ_CSR mhpmcounter24, 0xAAA
|
||||
WRITE_READ_CSR mhpmcounter25, 0xAAA
|
||||
WRITE_READ_CSR mhpmcounter26, 0xAAA
|
||||
WRITE_READ_CSR mhpmcounter27, 0xAAA
|
||||
WRITE_READ_CSR mhpmcounter28, 0xAAA
|
||||
WRITE_READ_CSR mhpmcounter29, 0xAAA
|
||||
WRITE_READ_CSR mhpmcounter30, 0xAAA
|
||||
WRITE_READ_CSR mhpmcounter31, 0xAAA
|
||||
|
||||
# Machine Counter Setup
|
||||
WRITE_READ_CSR mcountinhibit, 0xbad
|
||||
WRITE_READ_CSR mhpmevent3, 0xbad
|
||||
WRITE_READ_CSR mhpmevent4, 0xbad
|
||||
WRITE_READ_CSR mhpmevent5, 0xbad
|
||||
WRITE_READ_CSR mhpmevent6, 0xbad
|
||||
WRITE_READ_CSR mhpmevent7, 0xbad
|
||||
WRITE_READ_CSR mhpmevent8, 0xbad
|
||||
WRITE_READ_CSR mhpmevent9, 0xbad
|
||||
WRITE_READ_CSR mhpmevent10, 0xbad
|
||||
WRITE_READ_CSR mhpmevent11, 0xbad
|
||||
WRITE_READ_CSR mhpmevent12, 0xbad
|
||||
WRITE_READ_CSR mhpmevent13, 0xbad
|
||||
WRITE_READ_CSR mhpmevent14, 0xbad
|
||||
WRITE_READ_CSR mhpmevent15, 0xbad
|
||||
WRITE_READ_CSR mhpmevent16, 0xbad
|
||||
WRITE_READ_CSR mhpmevent17, 0xbad
|
||||
WRITE_READ_CSR mhpmevent18, 0xbad
|
||||
WRITE_READ_CSR mhpmevent19, 0xbad
|
||||
WRITE_READ_CSR mhpmevent20, 0xbad
|
||||
WRITE_READ_CSR mhpmevent21, 0xbad
|
||||
WRITE_READ_CSR mhpmevent22, 0xbad
|
||||
WRITE_READ_CSR mhpmevent23, 0xbad
|
||||
WRITE_READ_CSR mhpmevent24, 0xbad
|
||||
WRITE_READ_CSR mhpmevent25, 0xbad
|
||||
WRITE_READ_CSR mhpmevent26, 0xbad
|
||||
WRITE_READ_CSR mhpmevent27, 0xbad
|
||||
WRITE_READ_CSR mhpmevent28, 0xbad
|
||||
WRITE_READ_CSR mhpmevent29, 0xbad
|
||||
WRITE_READ_CSR mhpmevent30, 0xbad
|
||||
WRITE_READ_CSR mhpmevent31, 0xbad
|
||||
WRITE_READ_CSR mcountinhibit, 0xAAA
|
||||
WRITE_READ_CSR mhpmevent3, 0xAAA
|
||||
WRITE_READ_CSR mhpmevent4, 0xAAA
|
||||
WRITE_READ_CSR mhpmevent5, 0xAAA
|
||||
WRITE_READ_CSR mhpmevent6, 0xAAA
|
||||
WRITE_READ_CSR mhpmevent7, 0xAAA
|
||||
WRITE_READ_CSR mhpmevent8, 0xAAA
|
||||
WRITE_READ_CSR mhpmevent9, 0xAAA
|
||||
WRITE_READ_CSR mhpmevent10, 0xAAA
|
||||
WRITE_READ_CSR mhpmevent11, 0xAAA
|
||||
WRITE_READ_CSR mhpmevent12, 0xAAA
|
||||
WRITE_READ_CSR mhpmevent13, 0xAAA
|
||||
WRITE_READ_CSR mhpmevent14, 0xAAA
|
||||
WRITE_READ_CSR mhpmevent15, 0xAAA
|
||||
WRITE_READ_CSR mhpmevent16, 0xAAA
|
||||
WRITE_READ_CSR mhpmevent17, 0xAAA
|
||||
WRITE_READ_CSR mhpmevent18, 0xAAA
|
||||
WRITE_READ_CSR mhpmevent19, 0xAAA
|
||||
WRITE_READ_CSR mhpmevent20, 0xAAA
|
||||
WRITE_READ_CSR mhpmevent21, 0xAAA
|
||||
WRITE_READ_CSR mhpmevent22, 0xAAA
|
||||
WRITE_READ_CSR mhpmevent23, 0xAAA
|
||||
WRITE_READ_CSR mhpmevent24, 0xAAA
|
||||
WRITE_READ_CSR mhpmevent25, 0xAAA
|
||||
WRITE_READ_CSR mhpmevent26, 0xAAA
|
||||
WRITE_READ_CSR mhpmevent27, 0xAAA
|
||||
WRITE_READ_CSR mhpmevent28, 0xAAA
|
||||
WRITE_READ_CSR mhpmevent29, 0xAAA
|
||||
WRITE_READ_CSR mhpmevent30, 0xAAA
|
||||
WRITE_READ_CSR mhpmevent31, 0xAAA
|
||||
|
||||
END_TESTS
|
||||
|
||||
|
||||
@ -0,0 +1,44 @@
|
||||
///////////////////////////////////////////
|
||||
//
|
||||
// WALLY-MMU
|
||||
//
|
||||
// Author: Kip Macsai-Goren <kmacsaigoren@g.hmc.edu>
|
||||
//
|
||||
// Created 2022-02-18
|
||||
//
|
||||
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
|
||||
//
|
||||
// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
|
||||
// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
|
||||
// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
|
||||
// is furnished to do so, subject to the following conditions:
|
||||
//
|
||||
// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
|
||||
//
|
||||
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
|
||||
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
|
||||
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
///////////////////////////////////////////
|
||||
|
||||
#include "WALLY-TEST-LIB-32.h"
|
||||
|
||||
INIT_TESTS
|
||||
|
||||
s_file_begin:
|
||||
// Test 5.3.2.2: Machine ISA register test
|
||||
|
||||
// Misa is a specific case *** so I don't want to add a whole test case for reading nonzero but unkown value CSRs.
|
||||
csrr x30, misa // should not cause a fault in machine mode. *** not writing to output because MISA is different for different configs.
|
||||
li x7, 0x111 // success value for read of nonzero misa
|
||||
bnez x30, misa_nonzero
|
||||
li x7, 0xbad // misa was zero, store bad value
|
||||
|
||||
misa_nonzero:
|
||||
sw x7, 0(x6)
|
||||
addi x6, x6, 4
|
||||
addi x16, x16, 4
|
||||
|
||||
END_TESTS
|
||||
|
||||
TEST_STACK_AND_DATA
|
||||
@ -0,0 +1,35 @@
|
||||
///////////////////////////////////////////
|
||||
//
|
||||
// WALLY-scratch
|
||||
//
|
||||
// Author: Kip Macsai-Goren <kmacsaigoren@g.hmc.edu>
|
||||
//
|
||||
// Created 2022-02-20
|
||||
//
|
||||
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
|
||||
//
|
||||
// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
|
||||
// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
|
||||
// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
|
||||
// is furnished to do so, subject to the following conditions:
|
||||
//
|
||||
// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
|
||||
//
|
||||
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
|
||||
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
|
||||
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
///////////////////////////////////////////
|
||||
|
||||
#include "WALLY-TEST-LIB-32.h"
|
||||
|
||||
INIT_TESTS
|
||||
|
||||
s_file_begin:
|
||||
// Test 5.3.2.3: Scratch registers test
|
||||
|
||||
WRITE_READ_CSR mscratch, 0x111 // check that mscratch is readable and writeable in machine mode
|
||||
|
||||
END_TESTS
|
||||
|
||||
TEST_STACK_AND_DATA
|
||||
@ -0,0 +1,39 @@
|
||||
///////////////////////////////////////////
|
||||
//
|
||||
// WALLY-sscratch
|
||||
//
|
||||
// Author: Kip Macsai-Goren <kmacsaigoren@g.hmc.edu>
|
||||
//
|
||||
// Created 2022-02-20
|
||||
//
|
||||
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
|
||||
//
|
||||
// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
|
||||
// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
|
||||
// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
|
||||
// is furnished to do so, subject to the following conditions:
|
||||
//
|
||||
// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
|
||||
//
|
||||
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
|
||||
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
|
||||
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
///////////////////////////////////////////
|
||||
|
||||
#include "WALLY-TEST-LIB-32.h"
|
||||
|
||||
INIT_TESTS
|
||||
|
||||
s_file_begin:
|
||||
|
||||
// Test 5.3.2.3: Scratch registers test
|
||||
WRITE_READ_CSR sscratch, 0x111 // check that sscratch is readable and writeable in machine mode
|
||||
|
||||
GOTO_S_MODE 0x0, 0x0
|
||||
|
||||
WRITE_READ_CSR sscratch, 0xAAA // check that sscratch is readable and writeable in supervisor mode
|
||||
|
||||
END_TESTS
|
||||
|
||||
TEST_STACK_AND_DATA
|
||||
@ -33,7 +33,10 @@ rv64i_sc_tests = \
|
||||
WALLY-PMP \
|
||||
WALLY-minfo-01 \
|
||||
WALLY-CSR-permission-s-01 \
|
||||
WALLY-CSR-permission-u-01
|
||||
WALLY-CSR-permission-u-01 \
|
||||
WALLY-misa-01 \
|
||||
WALLY-scratch-01 \
|
||||
WALLY-sscratch-s-01
|
||||
|
||||
target_tests_nosim = WALLY-PMA \
|
||||
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@ -34,123 +34,123 @@ s_file_begin:
|
||||
|
||||
GOTO_S_MODE 0x0, 0x0
|
||||
|
||||
# Attempt to write 0xbad to each of these CSRs and read the value back
|
||||
# Attempt to write 0x111 to each of these CSRs and read the value back
|
||||
# should result in an illegal instruction for the write and read, respectively
|
||||
|
||||
# Machine information Registers
|
||||
WRITE_READ_CSR mvendorid, 0xbad
|
||||
WRITE_READ_CSR marchid, 0xbad
|
||||
WRITE_READ_CSR mimpid, 0xbad
|
||||
WRITE_READ_CSR mhartid, 0xbad
|
||||
# WRITE_READ_CSR mconfigptr, 0xbad # mconfigptr unimplemented in spike as of 31 Jan 22
|
||||
WRITE_READ_CSR mvendorid, 0x111
|
||||
WRITE_READ_CSR marchid, 0x111
|
||||
WRITE_READ_CSR mimpid, 0x111
|
||||
WRITE_READ_CSR mhartid, 0x111
|
||||
# WRITE_READ_CSR mconfigptr, 0x111 # mconfigptr unimplemented in spike as of 31 Jan 22
|
||||
|
||||
# Machine Trap Setup
|
||||
WRITE_READ_CSR mstatus, 0xbad
|
||||
WRITE_READ_CSR misa, 0xbad
|
||||
WRITE_READ_CSR medeleg, 0xbad
|
||||
WRITE_READ_CSR mideleg, 0xbad
|
||||
WRITE_READ_CSR mie, 0xbad
|
||||
WRITE_READ_CSR mtvec, 0xbad
|
||||
WRITE_READ_CSR mcounteren, 0xbad
|
||||
WRITE_READ_CSR mstatus, 0x111
|
||||
WRITE_READ_CSR misa, 0x111
|
||||
WRITE_READ_CSR medeleg, 0x111
|
||||
WRITE_READ_CSR mideleg, 0x111
|
||||
WRITE_READ_CSR mie, 0x111
|
||||
WRITE_READ_CSR mtvec, 0x111
|
||||
WRITE_READ_CSR mcounteren, 0x111
|
||||
|
||||
# Machine Trap Handling
|
||||
WRITE_READ_CSR mscratch, 0xbad
|
||||
WRITE_READ_CSR mepc, 0xbad
|
||||
WRITE_READ_CSR mcause, 0xbad
|
||||
WRITE_READ_CSR mtval, 0xbad
|
||||
WRITE_READ_CSR mip, 0xbad
|
||||
# WRITE_READ_CSR mtinst, 0xbad # *** these appear not to be implemented in GCC
|
||||
# WRITE_READ_CSR mtval2, 0xbad
|
||||
WRITE_READ_CSR mscratch, 0x111
|
||||
WRITE_READ_CSR mepc, 0x111
|
||||
WRITE_READ_CSR mcause, 0x111
|
||||
WRITE_READ_CSR mtval, 0x111
|
||||
WRITE_READ_CSR mip, 0x111
|
||||
# WRITE_READ_CSR mtinst, 0x111 # *** these appear not to be implemented in GCC
|
||||
# WRITE_READ_CSR mtval2, 0x111
|
||||
|
||||
# Machine Configuration
|
||||
# WRITE_READ_CSR menvcfg, 0xbad # *** these appear not to be implemented in GCC
|
||||
# WRITE_READ_CSR mseccgf, 0xbad
|
||||
# WRITE_READ_CSR menvcfg, 0x111 # *** these appear not to be implemented in GCC
|
||||
# WRITE_READ_CSR mseccgf, 0x111
|
||||
|
||||
# Machine Memory Protection
|
||||
WRITE_READ_CSR pmpcfg0, 0xbad
|
||||
WRITE_READ_CSR pmpcfg2, 0xbad # pmpcfg 1 and 3 dont exist in rv64. there's 1 pmpcfg reg per 8 pmpaddr regs
|
||||
WRITE_READ_CSR pmpcfg0, 0x111
|
||||
WRITE_READ_CSR pmpcfg2, 0x111 # pmpcfg 1 and 3 dont exist in rv64. there's 1 pmpcfg reg per 8 pmpaddr regs
|
||||
|
||||
WRITE_READ_CSR pmpaddr0, 0xbad
|
||||
WRITE_READ_CSR pmpaddr1, 0xbad
|
||||
WRITE_READ_CSR pmpaddr2, 0xbad
|
||||
WRITE_READ_CSR pmpaddr3, 0xbad
|
||||
WRITE_READ_CSR pmpaddr4, 0xbad
|
||||
WRITE_READ_CSR pmpaddr5, 0xbad
|
||||
WRITE_READ_CSR pmpaddr6, 0xbad
|
||||
WRITE_READ_CSR pmpaddr7, 0xbad
|
||||
WRITE_READ_CSR pmpaddr8, 0xbad
|
||||
WRITE_READ_CSR pmpaddr9, 0xbad
|
||||
WRITE_READ_CSR pmpaddr10, 0xbad
|
||||
WRITE_READ_CSR pmpaddr11, 0xbad
|
||||
WRITE_READ_CSR pmpaddr12, 0xbad
|
||||
WRITE_READ_CSR pmpaddr13, 0xbad
|
||||
WRITE_READ_CSR pmpaddr14, 0xbad
|
||||
WRITE_READ_CSR pmpaddr15, 0xbad # only pmpcfg0...15 are enabled in our config
|
||||
WRITE_READ_CSR pmpaddr0, 0x111
|
||||
WRITE_READ_CSR pmpaddr1, 0x111
|
||||
WRITE_READ_CSR pmpaddr2, 0x111
|
||||
WRITE_READ_CSR pmpaddr3, 0x111
|
||||
WRITE_READ_CSR pmpaddr4, 0x111
|
||||
WRITE_READ_CSR pmpaddr5, 0x111
|
||||
WRITE_READ_CSR pmpaddr6, 0x111
|
||||
WRITE_READ_CSR pmpaddr7, 0x111
|
||||
WRITE_READ_CSR pmpaddr8, 0x111
|
||||
WRITE_READ_CSR pmpaddr9, 0x111
|
||||
WRITE_READ_CSR pmpaddr10, 0x111
|
||||
WRITE_READ_CSR pmpaddr11, 0x111
|
||||
WRITE_READ_CSR pmpaddr12, 0x111
|
||||
WRITE_READ_CSR pmpaddr13, 0x111
|
||||
WRITE_READ_CSR pmpaddr14, 0x111
|
||||
WRITE_READ_CSR pmpaddr15, 0x111 # only pmpcfg0...15 are enabled in our config
|
||||
|
||||
# Machine Counter/Timers
|
||||
WRITE_READ_CSR mcycle, 0xbad
|
||||
WRITE_READ_CSR minstret, 0xbad
|
||||
WRITE_READ_CSR mhpmcounter3, 0xbad
|
||||
WRITE_READ_CSR mhpmcounter4, 0xbad
|
||||
WRITE_READ_CSR mhpmcounter5, 0xbad
|
||||
WRITE_READ_CSR mhpmcounter6, 0xbad
|
||||
WRITE_READ_CSR mhpmcounter7, 0xbad
|
||||
WRITE_READ_CSR mhpmcounter8, 0xbad
|
||||
WRITE_READ_CSR mhpmcounter9, 0xbad
|
||||
WRITE_READ_CSR mhpmcounter10, 0xbad
|
||||
WRITE_READ_CSR mhpmcounter11, 0xbad
|
||||
WRITE_READ_CSR mhpmcounter12, 0xbad
|
||||
WRITE_READ_CSR mhpmcounter13, 0xbad
|
||||
WRITE_READ_CSR mhpmcounter14, 0xbad
|
||||
WRITE_READ_CSR mhpmcounter15, 0xbad
|
||||
WRITE_READ_CSR mhpmcounter16, 0xbad
|
||||
WRITE_READ_CSR mhpmcounter17, 0xbad
|
||||
WRITE_READ_CSR mhpmcounter18, 0xbad
|
||||
WRITE_READ_CSR mhpmcounter19, 0xbad
|
||||
WRITE_READ_CSR mhpmcounter20, 0xbad
|
||||
WRITE_READ_CSR mhpmcounter21, 0xbad
|
||||
WRITE_READ_CSR mhpmcounter22, 0xbad
|
||||
WRITE_READ_CSR mhpmcounter23, 0xbad
|
||||
WRITE_READ_CSR mhpmcounter24, 0xbad
|
||||
WRITE_READ_CSR mhpmcounter25, 0xbad
|
||||
WRITE_READ_CSR mhpmcounter26, 0xbad
|
||||
WRITE_READ_CSR mhpmcounter27, 0xbad
|
||||
WRITE_READ_CSR mhpmcounter28, 0xbad
|
||||
WRITE_READ_CSR mhpmcounter29, 0xbad
|
||||
WRITE_READ_CSR mhpmcounter30, 0xbad
|
||||
WRITE_READ_CSR mhpmcounter31, 0xbad
|
||||
WRITE_READ_CSR mcycle, 0x111
|
||||
WRITE_READ_CSR minstret, 0x111
|
||||
WRITE_READ_CSR mhpmcounter3, 0x111
|
||||
WRITE_READ_CSR mhpmcounter4, 0x111
|
||||
WRITE_READ_CSR mhpmcounter5, 0x111
|
||||
WRITE_READ_CSR mhpmcounter6, 0x111
|
||||
WRITE_READ_CSR mhpmcounter7, 0x111
|
||||
WRITE_READ_CSR mhpmcounter8, 0x111
|
||||
WRITE_READ_CSR mhpmcounter9, 0x111
|
||||
WRITE_READ_CSR mhpmcounter10, 0x111
|
||||
WRITE_READ_CSR mhpmcounter11, 0x111
|
||||
WRITE_READ_CSR mhpmcounter12, 0x111
|
||||
WRITE_READ_CSR mhpmcounter13, 0x111
|
||||
WRITE_READ_CSR mhpmcounter14, 0x111
|
||||
WRITE_READ_CSR mhpmcounter15, 0x111
|
||||
WRITE_READ_CSR mhpmcounter16, 0x111
|
||||
WRITE_READ_CSR mhpmcounter17, 0x111
|
||||
WRITE_READ_CSR mhpmcounter18, 0x111
|
||||
WRITE_READ_CSR mhpmcounter19, 0x111
|
||||
WRITE_READ_CSR mhpmcounter20, 0x111
|
||||
WRITE_READ_CSR mhpmcounter21, 0x111
|
||||
WRITE_READ_CSR mhpmcounter22, 0x111
|
||||
WRITE_READ_CSR mhpmcounter23, 0x111
|
||||
WRITE_READ_CSR mhpmcounter24, 0x111
|
||||
WRITE_READ_CSR mhpmcounter25, 0x111
|
||||
WRITE_READ_CSR mhpmcounter26, 0x111
|
||||
WRITE_READ_CSR mhpmcounter27, 0x111
|
||||
WRITE_READ_CSR mhpmcounter28, 0x111
|
||||
WRITE_READ_CSR mhpmcounter29, 0x111
|
||||
WRITE_READ_CSR mhpmcounter30, 0x111
|
||||
WRITE_READ_CSR mhpmcounter31, 0x111
|
||||
|
||||
# Machine Counter Setup
|
||||
WRITE_READ_CSR mcountinhibit, 0xbad
|
||||
WRITE_READ_CSR mhpmevent3, 0xbad
|
||||
WRITE_READ_CSR mhpmevent4, 0xbad
|
||||
WRITE_READ_CSR mhpmevent5, 0xbad
|
||||
WRITE_READ_CSR mhpmevent6, 0xbad
|
||||
WRITE_READ_CSR mhpmevent7, 0xbad
|
||||
WRITE_READ_CSR mhpmevent8, 0xbad
|
||||
WRITE_READ_CSR mhpmevent9, 0xbad
|
||||
WRITE_READ_CSR mhpmevent10, 0xbad
|
||||
WRITE_READ_CSR mhpmevent11, 0xbad
|
||||
WRITE_READ_CSR mhpmevent12, 0xbad
|
||||
WRITE_READ_CSR mhpmevent13, 0xbad
|
||||
WRITE_READ_CSR mhpmevent14, 0xbad
|
||||
WRITE_READ_CSR mhpmevent15, 0xbad
|
||||
WRITE_READ_CSR mhpmevent16, 0xbad
|
||||
WRITE_READ_CSR mhpmevent17, 0xbad
|
||||
WRITE_READ_CSR mhpmevent18, 0xbad
|
||||
WRITE_READ_CSR mhpmevent19, 0xbad
|
||||
WRITE_READ_CSR mhpmevent20, 0xbad
|
||||
WRITE_READ_CSR mhpmevent21, 0xbad
|
||||
WRITE_READ_CSR mhpmevent22, 0xbad
|
||||
WRITE_READ_CSR mhpmevent23, 0xbad
|
||||
WRITE_READ_CSR mhpmevent24, 0xbad
|
||||
WRITE_READ_CSR mhpmevent25, 0xbad
|
||||
WRITE_READ_CSR mhpmevent26, 0xbad
|
||||
WRITE_READ_CSR mhpmevent27, 0xbad
|
||||
WRITE_READ_CSR mhpmevent28, 0xbad
|
||||
WRITE_READ_CSR mhpmevent29, 0xbad
|
||||
WRITE_READ_CSR mhpmevent30, 0xbad
|
||||
WRITE_READ_CSR mhpmevent31, 0xbad
|
||||
WRITE_READ_CSR mcountinhibit, 0x111
|
||||
WRITE_READ_CSR mhpmevent3, 0x111
|
||||
WRITE_READ_CSR mhpmevent4, 0x111
|
||||
WRITE_READ_CSR mhpmevent5, 0x111
|
||||
WRITE_READ_CSR mhpmevent6, 0x111
|
||||
WRITE_READ_CSR mhpmevent7, 0x111
|
||||
WRITE_READ_CSR mhpmevent8, 0x111
|
||||
WRITE_READ_CSR mhpmevent9, 0x111
|
||||
WRITE_READ_CSR mhpmevent10, 0x111
|
||||
WRITE_READ_CSR mhpmevent11, 0x111
|
||||
WRITE_READ_CSR mhpmevent12, 0x111
|
||||
WRITE_READ_CSR mhpmevent13, 0x111
|
||||
WRITE_READ_CSR mhpmevent14, 0x111
|
||||
WRITE_READ_CSR mhpmevent15, 0x111
|
||||
WRITE_READ_CSR mhpmevent16, 0x111
|
||||
WRITE_READ_CSR mhpmevent17, 0x111
|
||||
WRITE_READ_CSR mhpmevent18, 0x111
|
||||
WRITE_READ_CSR mhpmevent19, 0x111
|
||||
WRITE_READ_CSR mhpmevent20, 0x111
|
||||
WRITE_READ_CSR mhpmevent21, 0x111
|
||||
WRITE_READ_CSR mhpmevent22, 0x111
|
||||
WRITE_READ_CSR mhpmevent23, 0x111
|
||||
WRITE_READ_CSR mhpmevent24, 0x111
|
||||
WRITE_READ_CSR mhpmevent25, 0x111
|
||||
WRITE_READ_CSR mhpmevent26, 0x111
|
||||
WRITE_READ_CSR mhpmevent27, 0x111
|
||||
WRITE_READ_CSR mhpmevent28, 0x111
|
||||
WRITE_READ_CSR mhpmevent29, 0x111
|
||||
WRITE_READ_CSR mhpmevent30, 0x111
|
||||
WRITE_READ_CSR mhpmevent31, 0x111
|
||||
|
||||
END_TESTS
|
||||
|
||||
|
||||
@ -31,142 +31,142 @@ s_file_begin:
|
||||
|
||||
GOTO_U_MODE 0x0, 0x0
|
||||
|
||||
# Attempt to write 0xbad to each of these CSRs and read the value back
|
||||
# Attempt to write 0x111 to each of these CSRs and read the value back
|
||||
# should result in an illegal instruction for the write and read, respectively
|
||||
|
||||
# Supervisor Trap Setup
|
||||
WRITE_READ_CSR sstatus, 0xbad
|
||||
WRITE_READ_CSR sie, 0xbad
|
||||
WRITE_READ_CSR stvec, 0xbad
|
||||
WRITE_READ_CSR scounteren, 0xbad
|
||||
WRITE_READ_CSR sstatus, 0x111
|
||||
WRITE_READ_CSR sie, 0x111
|
||||
WRITE_READ_CSR stvec, 0x111
|
||||
WRITE_READ_CSR scounteren, 0x111
|
||||
|
||||
# Supervisor Configuration
|
||||
# WRITE_READ_CSR senvcfg, 0xbad # *** these appear not to be implemented in GCC
|
||||
# WRITE_READ_CSR senvcfg, 0x111 # *** these appear not to be implemented in GCC
|
||||
|
||||
# Supervisor Trap Handling
|
||||
WRITE_READ_CSR sscratch, 0xbad
|
||||
WRITE_READ_CSR sepc, 0xbad
|
||||
WRITE_READ_CSR scause, 0xbad
|
||||
WRITE_READ_CSR stval, 0xbad
|
||||
WRITE_READ_CSR sip, 0xbad
|
||||
WRITE_READ_CSR sscratch, 0x111
|
||||
WRITE_READ_CSR sepc, 0x111
|
||||
WRITE_READ_CSR scause, 0x111
|
||||
WRITE_READ_CSR stval, 0x111
|
||||
WRITE_READ_CSR sip, 0x111
|
||||
|
||||
# Supervisor Protection and Translation
|
||||
WRITE_READ_CSR satp, 0xbad
|
||||
WRITE_READ_CSR satp, 0x111
|
||||
|
||||
# Machine information Registers
|
||||
WRITE_READ_CSR mvendorid, 0xbad
|
||||
WRITE_READ_CSR marchid, 0xbad
|
||||
WRITE_READ_CSR mimpid, 0xbad
|
||||
WRITE_READ_CSR mhartid, 0xbad
|
||||
# WRITE_READ_CSR mconfigptr, 0xbad # mconfigptr unimplemented in spike as of 31 Jan 22
|
||||
WRITE_READ_CSR mvendorid, 0x111
|
||||
WRITE_READ_CSR marchid, 0x111
|
||||
WRITE_READ_CSR mimpid, 0x111
|
||||
WRITE_READ_CSR mhartid, 0x111
|
||||
# WRITE_READ_CSR mconfigptr, 0x111 # mconfigptr unimplemented in spike as of 31 Jan 22
|
||||
|
||||
# Machine Trap Setup
|
||||
WRITE_READ_CSR mstatus, 0xbad
|
||||
WRITE_READ_CSR misa, 0xbad
|
||||
WRITE_READ_CSR medeleg, 0xbad
|
||||
WRITE_READ_CSR mideleg, 0xbad
|
||||
WRITE_READ_CSR mie, 0xbad
|
||||
WRITE_READ_CSR mtvec, 0xbad
|
||||
WRITE_READ_CSR mcounteren, 0xbad
|
||||
WRITE_READ_CSR mstatus, 0x111
|
||||
WRITE_READ_CSR misa, 0x111
|
||||
WRITE_READ_CSR medeleg, 0x111
|
||||
WRITE_READ_CSR mideleg, 0x111
|
||||
WRITE_READ_CSR mie, 0x111
|
||||
WRITE_READ_CSR mtvec, 0x111
|
||||
WRITE_READ_CSR mcounteren, 0x111
|
||||
|
||||
# Machine Trap Handling
|
||||
WRITE_READ_CSR mscratch, 0xbad
|
||||
WRITE_READ_CSR mepc, 0xbad
|
||||
WRITE_READ_CSR mcause, 0xbad
|
||||
WRITE_READ_CSR mtval, 0xbad
|
||||
WRITE_READ_CSR mip, 0xbad
|
||||
# WRITE_READ_CSR mtinst, 0xbad # *** these appear not to be implemented in GCC
|
||||
# WRITE_READ_CSR mtval2, 0xbad
|
||||
WRITE_READ_CSR mscratch, 0x111
|
||||
WRITE_READ_CSR mepc, 0x111
|
||||
WRITE_READ_CSR mcause, 0x111
|
||||
WRITE_READ_CSR mtval, 0x111
|
||||
WRITE_READ_CSR mip, 0x111
|
||||
# WRITE_READ_CSR mtinst, 0x111 # *** these appear not to be implemented in GCC
|
||||
# WRITE_READ_CSR mtval2, 0x111
|
||||
|
||||
# Machine Configuration
|
||||
# WRITE_READ_CSR menvcfg, 0xbad # *** these appear not to be implemented in GCC
|
||||
# WRITE_READ_CSR mseccgf, 0xbad
|
||||
# WRITE_READ_CSR menvcfg, 0x111 # *** these appear not to be implemented in GCC
|
||||
# WRITE_READ_CSR mseccgf, 0x111
|
||||
|
||||
# Machine Memory Protection
|
||||
WRITE_READ_CSR pmpcfg0, 0xbad
|
||||
WRITE_READ_CSR pmpcfg2, 0xbad # pmpcfg 1 and 3 dont exist in rv64. there's 1 pmpcfg reg per 8 pmpaddr regs
|
||||
WRITE_READ_CSR pmpcfg0, 0x111
|
||||
WRITE_READ_CSR pmpcfg2, 0x111 # pmpcfg 1 and 3 dont exist in rv64. there's 1 pmpcfg reg per 8 pmpaddr regs
|
||||
|
||||
WRITE_READ_CSR pmpaddr0, 0xbad
|
||||
WRITE_READ_CSR pmpaddr1, 0xbad
|
||||
WRITE_READ_CSR pmpaddr2, 0xbad
|
||||
WRITE_READ_CSR pmpaddr3, 0xbad
|
||||
WRITE_READ_CSR pmpaddr4, 0xbad
|
||||
WRITE_READ_CSR pmpaddr5, 0xbad
|
||||
WRITE_READ_CSR pmpaddr6, 0xbad
|
||||
WRITE_READ_CSR pmpaddr7, 0xbad
|
||||
WRITE_READ_CSR pmpaddr8, 0xbad
|
||||
WRITE_READ_CSR pmpaddr9, 0xbad
|
||||
WRITE_READ_CSR pmpaddr10, 0xbad
|
||||
WRITE_READ_CSR pmpaddr11, 0xbad
|
||||
WRITE_READ_CSR pmpaddr12, 0xbad
|
||||
WRITE_READ_CSR pmpaddr13, 0xbad
|
||||
WRITE_READ_CSR pmpaddr14, 0xbad
|
||||
WRITE_READ_CSR pmpaddr15, 0xbad # only pmpcfg0...15 are enabled in our config
|
||||
WRITE_READ_CSR pmpaddr0, 0x111
|
||||
WRITE_READ_CSR pmpaddr1, 0x111
|
||||
WRITE_READ_CSR pmpaddr2, 0x111
|
||||
WRITE_READ_CSR pmpaddr3, 0x111
|
||||
WRITE_READ_CSR pmpaddr4, 0x111
|
||||
WRITE_READ_CSR pmpaddr5, 0x111
|
||||
WRITE_READ_CSR pmpaddr6, 0x111
|
||||
WRITE_READ_CSR pmpaddr7, 0x111
|
||||
WRITE_READ_CSR pmpaddr8, 0x111
|
||||
WRITE_READ_CSR pmpaddr9, 0x111
|
||||
WRITE_READ_CSR pmpaddr10, 0x111
|
||||
WRITE_READ_CSR pmpaddr11, 0x111
|
||||
WRITE_READ_CSR pmpaddr12, 0x111
|
||||
WRITE_READ_CSR pmpaddr13, 0x111
|
||||
WRITE_READ_CSR pmpaddr14, 0x111
|
||||
WRITE_READ_CSR pmpaddr15, 0x111 # only pmpcfg0...15 are enabled in our config
|
||||
|
||||
# Machine Counter/Timers
|
||||
WRITE_READ_CSR mcycle, 0xbad
|
||||
WRITE_READ_CSR minstret, 0xbad
|
||||
WRITE_READ_CSR mhpmcounter3, 0xbad
|
||||
WRITE_READ_CSR mhpmcounter4, 0xbad
|
||||
WRITE_READ_CSR mhpmcounter5, 0xbad
|
||||
WRITE_READ_CSR mhpmcounter6, 0xbad
|
||||
WRITE_READ_CSR mhpmcounter7, 0xbad
|
||||
WRITE_READ_CSR mhpmcounter8, 0xbad
|
||||
WRITE_READ_CSR mhpmcounter9, 0xbad
|
||||
WRITE_READ_CSR mhpmcounter10, 0xbad
|
||||
WRITE_READ_CSR mhpmcounter11, 0xbad
|
||||
WRITE_READ_CSR mhpmcounter12, 0xbad
|
||||
WRITE_READ_CSR mhpmcounter13, 0xbad
|
||||
WRITE_READ_CSR mhpmcounter14, 0xbad
|
||||
WRITE_READ_CSR mhpmcounter15, 0xbad
|
||||
WRITE_READ_CSR mhpmcounter16, 0xbad
|
||||
WRITE_READ_CSR mhpmcounter17, 0xbad
|
||||
WRITE_READ_CSR mhpmcounter18, 0xbad
|
||||
WRITE_READ_CSR mhpmcounter19, 0xbad
|
||||
WRITE_READ_CSR mhpmcounter20, 0xbad
|
||||
WRITE_READ_CSR mhpmcounter21, 0xbad
|
||||
WRITE_READ_CSR mhpmcounter22, 0xbad
|
||||
WRITE_READ_CSR mhpmcounter23, 0xbad
|
||||
WRITE_READ_CSR mhpmcounter24, 0xbad
|
||||
WRITE_READ_CSR mhpmcounter25, 0xbad
|
||||
WRITE_READ_CSR mhpmcounter26, 0xbad
|
||||
WRITE_READ_CSR mhpmcounter27, 0xbad
|
||||
WRITE_READ_CSR mhpmcounter28, 0xbad
|
||||
WRITE_READ_CSR mhpmcounter29, 0xbad
|
||||
WRITE_READ_CSR mhpmcounter30, 0xbad
|
||||
WRITE_READ_CSR mhpmcounter31, 0xbad
|
||||
WRITE_READ_CSR mcycle, 0x111
|
||||
WRITE_READ_CSR minstret, 0x111
|
||||
WRITE_READ_CSR mhpmcounter3, 0x111
|
||||
WRITE_READ_CSR mhpmcounter4, 0x111
|
||||
WRITE_READ_CSR mhpmcounter5, 0x111
|
||||
WRITE_READ_CSR mhpmcounter6, 0x111
|
||||
WRITE_READ_CSR mhpmcounter7, 0x111
|
||||
WRITE_READ_CSR mhpmcounter8, 0x111
|
||||
WRITE_READ_CSR mhpmcounter9, 0x111
|
||||
WRITE_READ_CSR mhpmcounter10, 0x111
|
||||
WRITE_READ_CSR mhpmcounter11, 0x111
|
||||
WRITE_READ_CSR mhpmcounter12, 0x111
|
||||
WRITE_READ_CSR mhpmcounter13, 0x111
|
||||
WRITE_READ_CSR mhpmcounter14, 0x111
|
||||
WRITE_READ_CSR mhpmcounter15, 0x111
|
||||
WRITE_READ_CSR mhpmcounter16, 0x111
|
||||
WRITE_READ_CSR mhpmcounter17, 0x111
|
||||
WRITE_READ_CSR mhpmcounter18, 0x111
|
||||
WRITE_READ_CSR mhpmcounter19, 0x111
|
||||
WRITE_READ_CSR mhpmcounter20, 0x111
|
||||
WRITE_READ_CSR mhpmcounter21, 0x111
|
||||
WRITE_READ_CSR mhpmcounter22, 0x111
|
||||
WRITE_READ_CSR mhpmcounter23, 0x111
|
||||
WRITE_READ_CSR mhpmcounter24, 0x111
|
||||
WRITE_READ_CSR mhpmcounter25, 0x111
|
||||
WRITE_READ_CSR mhpmcounter26, 0x111
|
||||
WRITE_READ_CSR mhpmcounter27, 0x111
|
||||
WRITE_READ_CSR mhpmcounter28, 0x111
|
||||
WRITE_READ_CSR mhpmcounter29, 0x111
|
||||
WRITE_READ_CSR mhpmcounter30, 0x111
|
||||
WRITE_READ_CSR mhpmcounter31, 0x111
|
||||
|
||||
# Machine Counter Setup
|
||||
WRITE_READ_CSR mcountinhibit, 0xbad
|
||||
WRITE_READ_CSR mhpmevent3, 0xbad
|
||||
WRITE_READ_CSR mhpmevent4, 0xbad
|
||||
WRITE_READ_CSR mhpmevent5, 0xbad
|
||||
WRITE_READ_CSR mhpmevent6, 0xbad
|
||||
WRITE_READ_CSR mhpmevent7, 0xbad
|
||||
WRITE_READ_CSR mhpmevent8, 0xbad
|
||||
WRITE_READ_CSR mhpmevent9, 0xbad
|
||||
WRITE_READ_CSR mhpmevent10, 0xbad
|
||||
WRITE_READ_CSR mhpmevent11, 0xbad
|
||||
WRITE_READ_CSR mhpmevent12, 0xbad
|
||||
WRITE_READ_CSR mhpmevent13, 0xbad
|
||||
WRITE_READ_CSR mhpmevent14, 0xbad
|
||||
WRITE_READ_CSR mhpmevent15, 0xbad
|
||||
WRITE_READ_CSR mhpmevent16, 0xbad
|
||||
WRITE_READ_CSR mhpmevent17, 0xbad
|
||||
WRITE_READ_CSR mhpmevent18, 0xbad
|
||||
WRITE_READ_CSR mhpmevent19, 0xbad
|
||||
WRITE_READ_CSR mhpmevent20, 0xbad
|
||||
WRITE_READ_CSR mhpmevent21, 0xbad
|
||||
WRITE_READ_CSR mhpmevent22, 0xbad
|
||||
WRITE_READ_CSR mhpmevent23, 0xbad
|
||||
WRITE_READ_CSR mhpmevent24, 0xbad
|
||||
WRITE_READ_CSR mhpmevent25, 0xbad
|
||||
WRITE_READ_CSR mhpmevent26, 0xbad
|
||||
WRITE_READ_CSR mhpmevent27, 0xbad
|
||||
WRITE_READ_CSR mhpmevent28, 0xbad
|
||||
WRITE_READ_CSR mhpmevent29, 0xbad
|
||||
WRITE_READ_CSR mhpmevent30, 0xbad
|
||||
WRITE_READ_CSR mhpmevent31, 0xbad
|
||||
WRITE_READ_CSR mcountinhibit, 0x111
|
||||
WRITE_READ_CSR mhpmevent3, 0x111
|
||||
WRITE_READ_CSR mhpmevent4, 0x111
|
||||
WRITE_READ_CSR mhpmevent5, 0x111
|
||||
WRITE_READ_CSR mhpmevent6, 0x111
|
||||
WRITE_READ_CSR mhpmevent7, 0x111
|
||||
WRITE_READ_CSR mhpmevent8, 0x111
|
||||
WRITE_READ_CSR mhpmevent9, 0x111
|
||||
WRITE_READ_CSR mhpmevent10, 0x111
|
||||
WRITE_READ_CSR mhpmevent11, 0x111
|
||||
WRITE_READ_CSR mhpmevent12, 0x111
|
||||
WRITE_READ_CSR mhpmevent13, 0x111
|
||||
WRITE_READ_CSR mhpmevent14, 0x111
|
||||
WRITE_READ_CSR mhpmevent15, 0x111
|
||||
WRITE_READ_CSR mhpmevent16, 0x111
|
||||
WRITE_READ_CSR mhpmevent17, 0x111
|
||||
WRITE_READ_CSR mhpmevent18, 0x111
|
||||
WRITE_READ_CSR mhpmevent19, 0x111
|
||||
WRITE_READ_CSR mhpmevent20, 0x111
|
||||
WRITE_READ_CSR mhpmevent21, 0x111
|
||||
WRITE_READ_CSR mhpmevent22, 0x111
|
||||
WRITE_READ_CSR mhpmevent23, 0x111
|
||||
WRITE_READ_CSR mhpmevent24, 0x111
|
||||
WRITE_READ_CSR mhpmevent25, 0x111
|
||||
WRITE_READ_CSR mhpmevent26, 0x111
|
||||
WRITE_READ_CSR mhpmevent27, 0x111
|
||||
WRITE_READ_CSR mhpmevent28, 0x111
|
||||
WRITE_READ_CSR mhpmevent29, 0x111
|
||||
WRITE_READ_CSR mhpmevent30, 0x111
|
||||
WRITE_READ_CSR mhpmevent31, 0x111
|
||||
|
||||
END_TESTS
|
||||
|
||||
|
||||
@ -1,560 +0,0 @@
|
||||
///////////////////////////////////////////
|
||||
//
|
||||
// WALLY-TEST-LIB-64.h
|
||||
//
|
||||
// Author: Kip Macsai-Goren <kmacsaigoren@g.hmc.edu>
|
||||
//
|
||||
// Created 2022-01-30
|
||||
//
|
||||
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
|
||||
//
|
||||
// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
|
||||
// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
|
||||
// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
|
||||
// is furnished to do so, subject to the following conditions:
|
||||
//
|
||||
// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
|
||||
//
|
||||
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
|
||||
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
|
||||
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
///////////////////////////////////////////
|
||||
|
||||
|
||||
.macro INIT_TESTS
|
||||
|
||||
#include "model_test.h"
|
||||
#include "arch_test.h"
|
||||
RVTEST_ISA("RV64I")
|
||||
|
||||
.section .text.init
|
||||
.globl rvtest_entry_point
|
||||
rvtest_entry_point:
|
||||
RVMODEL_BOOT
|
||||
RVTEST_CODE_BEGIN
|
||||
|
||||
|
||||
// ---------------------------------------------------------------------------------------------
|
||||
// Initialization Overview:
|
||||
//
|
||||
// Initialize x6 as a virtual pointer to the test results
|
||||
// Initialize x16 as a physical pointer to the test results
|
||||
// Set up stack pointer (sp = x2)
|
||||
// Set up the exception Handler, keeping the original handler in x4.
|
||||
//
|
||||
// ---------------------------------------------------------------------------------------------
|
||||
|
||||
// address for test results
|
||||
la x6, test_1_res
|
||||
la x16, test_1_res // x16 reserved for the physical address equivalent of x6 to be used in trap handlers
|
||||
// any time either is used, both must be updated.
|
||||
|
||||
// address for stack
|
||||
la sp, top_of_stack
|
||||
|
||||
// trap handler setup
|
||||
la x1, machine_trap_handler
|
||||
csrrw x4, mtvec, x1 // x4 reserved for "default" trap handler address that needs to be restored before halting this test.
|
||||
li a0, 0
|
||||
li a1, 0
|
||||
li a2, 0 // reset trap handler inputs to zero
|
||||
|
||||
// go to first test!
|
||||
j begin_test
|
||||
|
||||
|
||||
// ---------------------------------------------------------------------------------------------
|
||||
// General traps Handler
|
||||
//
|
||||
// Handles traps by branching to different behaviors based on mcause.
|
||||
//
|
||||
// Note that allowing the exception handler to change mode for a program is a huge security
|
||||
// hole, but this is an expedient way of writing tests that need different modes
|
||||
//
|
||||
// input parameters:
|
||||
//
|
||||
// a0 (x10):
|
||||
// 0: halt program with no failures
|
||||
// 1: halt program with failure in x11 = a1
|
||||
// 2: go to machine mode
|
||||
// 3: go to supervisor mode
|
||||
// 4: go to user mode
|
||||
// others: do nothing
|
||||
//
|
||||
// a1 (x11):
|
||||
// VPN for return address after changing privilege mode.
|
||||
// This should be the base VPN with no offset.
|
||||
// 0x0 : defaults to next instruction on the same page the trap was called on.
|
||||
//
|
||||
// a2 (x12):
|
||||
// Pagetype of the current address VPN before changing privilge mode
|
||||
// Used so that we can know how many bits of the adress are the offset.
|
||||
// Ignored if a1 == 0x0
|
||||
// 0: Kilopage
|
||||
// 1: Megapage
|
||||
// 2: Gigapage
|
||||
// 3: Terapage
|
||||
//
|
||||
// --------------------------------------------------------------------------------------------
|
||||
|
||||
|
||||
machine_trap_handler:
|
||||
// The processor is always in machine mode when a trap takes us here
|
||||
// save registers on stack before using
|
||||
sd x1, -8(sp)
|
||||
sd x5, -16(sp)
|
||||
|
||||
// Record trap
|
||||
csrr x1, mcause // record the mcause
|
||||
sd x1, 0(x16)
|
||||
addi x6, x6, 8
|
||||
addi x16, x16, 8 // update pointers for logging results
|
||||
|
||||
// Respond to trap based on cause
|
||||
// All interrupts should return after being logged
|
||||
li x5, 0x8000000000000000 // if msb is set, it is an interrupt
|
||||
and x5, x5, x1
|
||||
bnez x5, trapreturn // return from interrupt
|
||||
// Other trap handling is specified in the vector Table
|
||||
slli x1, x1, 3 // multiply cause by 8 to get offset in vector Table
|
||||
la x5, trap_handler_vector_table
|
||||
add x5, x5, x1 // compute address of vector in Table
|
||||
ld x5, 0(x5) // fectch address of handler from vector Table
|
||||
jr x5 // and jump to the handler
|
||||
|
||||
segfault:
|
||||
ld x5, -16(sp) // restore registers from stack before faulting
|
||||
ld x1, -8(sp)
|
||||
j terminate_test // halt program.
|
||||
|
||||
trapreturn:
|
||||
// look at the instruction to figure out whether to add 2 or 4 bytes to PC, or go to address specified in a1
|
||||
csrr x1, mepc // get the mepc
|
||||
addi x1, x1, 4 // *** should be 2 for compressed instructions, see note.
|
||||
|
||||
|
||||
// ****** KMG: the following is no longer as easy to determine. mepc gets the virtual address of the trapped instruction,
|
||||
// ******** but in the handler, we work in M mode with physical addresses
|
||||
// This means the address in mepc is suddenly pointing somewhere else.
|
||||
// to get this to work, We could either retranslate the vaddr back into a paddr (probably on the scale of difficult to intractible)
|
||||
// or we could come up with some other ingenious way to stay in M mode and see if the instruction was compressed.
|
||||
|
||||
// lw x5, 0(x1) // read the faulting instruction
|
||||
// li x1, 3 // check bottom 2 bits of instruction to see if compressed
|
||||
// and x5, x5, x1 // mask the other bits
|
||||
// beq x5, x1, trapreturn_uncompressed // if 11, the instruction is return_uncompressed
|
||||
|
||||
// trapreturn_compressed:
|
||||
// csrr x1, mepc // get the mepc again
|
||||
// addi x1, x1, 2 // add 2 to find the next instruction
|
||||
// j trapreturn_specified // and return
|
||||
|
||||
// trapreturn_uncompressed:
|
||||
// csrr x1, mepc // get the mepc again
|
||||
// addi x1, x1, 4 // add 4 to find the next instruction
|
||||
|
||||
trapreturn_specified:
|
||||
// reset the necessary pointers and registers (x1, x5, x6, and the return address going to mepc)
|
||||
// so that when we return to a new virtual address, they're all in the right spot as well.
|
||||
|
||||
beqz a1, trapreturn_finished // either update values, of go to default return address.
|
||||
|
||||
la x5, trap_return_pagetype_table
|
||||
slli a2, a2, 3
|
||||
add x5, x5, a2
|
||||
ld a2, 0(x5) // a2 = number of offset bits in current page type
|
||||
|
||||
li x5, 1
|
||||
sll x5, x5, a2
|
||||
addi x5, x5, -1 // x5 = mask bits for offset into current pagetype
|
||||
|
||||
// reset the top of the stack, x1
|
||||
ld x7, -8(sp)
|
||||
and x7, x5, x7 // x7 = offset for x1
|
||||
add x7, x7, a1 // x7 = new address for x1
|
||||
sd x7, -8(sp)
|
||||
|
||||
// reset the second spot in the stack, x5
|
||||
ld x7, -16(sp)
|
||||
and x7, x5, x7 // x7 = offset for x5
|
||||
add x7, x7, a1 // x7 = new address for x5
|
||||
sd x7, -16(sp)
|
||||
|
||||
// reset x6, the pointer for the virtual address of the output of the tests
|
||||
and x7, x5, x6 // x7 = offset for x6
|
||||
add x6, x7, a1 // x6 = new address for the result pointer
|
||||
|
||||
// set return address, stored temporarily in x1, to the next instruction, but in the new virtual page.
|
||||
and x1, x5, x1 // x1 = offset for the return address
|
||||
add x1, x1, a1 // x1 = new return address.
|
||||
|
||||
li a1, 0
|
||||
li a2, 0 // reset trapreturn inputs to the trap handler
|
||||
|
||||
trapreturn_finished:
|
||||
csrw mepc, x1 // update the mepc with address of next instruction
|
||||
ld x5, -16(sp) // restore registers from stack before returning
|
||||
ld x1, -8(sp)
|
||||
mret // return from trap
|
||||
|
||||
ecallhandler:
|
||||
// Check input parameter a0. encoding above.
|
||||
// *** ASSUMES: that this trap is being handled in machine mode. in other words, that nothing odd has been written to the medeleg or mideleg csrs.
|
||||
li x5, 2 // case 2: change to machine mode
|
||||
beq a0, x5, ecallhandler_changetomachinemode
|
||||
li x5, 3 // case 3: change to supervisor mode
|
||||
beq a0, x5, ecallhandler_changetosupervisormode
|
||||
li x5, 4 // case 4: change to user mode
|
||||
beq a0, x5, ecallhandler_changetousermode
|
||||
// unsupported ecalls should segfault
|
||||
j segfault
|
||||
|
||||
ecallhandler_changetomachinemode:
|
||||
// Force mstatus.MPP (bits 12:11) to 11 to enter machine mode after mret
|
||||
li x1, 0b1100000000000
|
||||
csrs mstatus, x1
|
||||
j trapreturn
|
||||
|
||||
ecallhandler_changetosupervisormode:
|
||||
// Force mstatus.MPP (bits 12:11) to 01 to enter supervisor mode after mret
|
||||
li x1, 0b1100000000000
|
||||
csrc mstatus, x1
|
||||
li x1, 0b0100000000000
|
||||
csrs mstatus, x1
|
||||
j trapreturn
|
||||
|
||||
ecallhandler_changetousermode:
|
||||
// Force mstatus.MPP (bits 12:11) to 00 to enter user mode after mret
|
||||
li x1, 0b1100000000000
|
||||
csrc mstatus, x1
|
||||
j trapreturn
|
||||
|
||||
instrfault:
|
||||
ld x1, -8(sp) // load return address int x1 (the address AFTER the jal into faulting page)
|
||||
j trapreturn_finished // puts x1 into mepc, restores stack and returns to program (outside of faulting page)
|
||||
|
||||
illegalinstr:
|
||||
j trapreturn // return to the code after recording the mcause
|
||||
|
||||
accessfault:
|
||||
// *** What do I have to do here?
|
||||
j trapreturn
|
||||
|
||||
// Table of trap behavior
|
||||
// lists what to do on each exception (not interrupts)
|
||||
// unexpected exceptions should cause segfaults for easy detection
|
||||
// Expected exceptions should increment the EPC to the next instruction and return
|
||||
|
||||
.align 3 // aligns this data table to an 8 byte boundary
|
||||
trap_handler_vector_table:
|
||||
.8byte segfault // 0: instruction address misaligned
|
||||
.8byte instrfault // 1: instruction access fault
|
||||
.8byte illegalinstr // 2: illegal instruction
|
||||
.8byte segfault // 3: breakpoint
|
||||
.8byte segfault // 4: load address misaligned
|
||||
.8byte accessfault // 5: load access fault
|
||||
.8byte segfault // 6: store address misaligned
|
||||
.8byte accessfault // 7: store access fault
|
||||
.8byte ecallhandler // 8: ecall from U-mode
|
||||
.8byte ecallhandler // 9: ecall from S-mode
|
||||
.8byte segfault // 10: reserved
|
||||
.8byte ecallhandler // 11: ecall from M-mode
|
||||
.8byte instrfault // 12: instruction page fault
|
||||
.8byte trapreturn // 13: load page fault
|
||||
.8byte segfault // 14: reserved
|
||||
.8byte trapreturn // 15: store page fault
|
||||
|
||||
.align 3
|
||||
trap_return_pagetype_table:
|
||||
.8byte 0xC // 0: kilopage has 12 offset bits
|
||||
.8byte 0x15 // 1: megapage has 21 offset bits
|
||||
.8byte 0x1E // 2: gigapage has 30 offset bits
|
||||
.8byte 0x27 // 3: terapage has 39 offset bits
|
||||
|
||||
begin_test: // label here to jump to so we dont go through the trap handler before starting the test
|
||||
|
||||
.endm // Ends the initialization macro that set up the begginnning of the tests and the trap handler.
|
||||
|
||||
|
||||
// Test Summary table!
|
||||
|
||||
// Test Name : Description : Fault output value : Normal output values
|
||||
// ---------------------:-------------------------------------------:-------------------------------------------:------------------------------------------------------
|
||||
// write64_test : Write 64 bits to address : 0x6, 0x7, or 0xf : None
|
||||
// write32_test : Write 32 bits to address : 0x6, 0x7, or 0xf : None
|
||||
// write16_test : Write 16 bits to address : 0x6, 0x7, or 0xf : None
|
||||
// write08_test : Write 8 bits to address : 0x6, 0x7, or 0xf : None
|
||||
// read64_test : Read 64 bits from address : 0x4, 0x5, or 0xd, then 0xbad : readvalue in hex
|
||||
// read32_test : Read 32 bitsfrom address : 0x4, 0x5, or 0xd, then 0xbad : readvalue in hex
|
||||
// read16_test : Read 16 bitsfrom address : 0x4, 0x5, or 0xd, then 0xbad : readvalue in hex
|
||||
// read08_test : Read 8 bitsfrom address : 0x4, 0x5, or 0xd, then 0xbad : readvalue in hex
|
||||
// executable_test : test executable on virtual page : 0x0, 0x1, or 0xc, then 0xbad : value of x7 modified by exectuion code (usually 0x111)
|
||||
// terminate_test : terminate tests : mcause value for fault : from M 0xb, from S 0x9, from U 0x8
|
||||
// goto_baremetal : satp.MODE = bare metal : None : None
|
||||
// goto_sv39 : satp.MODE = sv39 : None : None
|
||||
// goto_sv48 : satp.MODE = sv48 : None : None
|
||||
// goto_m_mode : go to mahcine mode : mcause value for fault : from M 0xb, from S 0x9, from U 0x8
|
||||
// goto_s_mode : go to supervisor mode : mcause value for fault : from M 0xb, from S 0x9, from U 0x8
|
||||
// goto_u_mode : go to user mode : mcause value for fault : from M 0xb, from S 0x9, from U 0x8
|
||||
// write_read_csr : write to specified CSR : old CSR value, 0x2, depending on perms : value written to CSR
|
||||
// csr_r_access : test read-only permissions on CSR : 0xbad : 0x2, then 0x11
|
||||
|
||||
// *** TESTS TO ADD: execute inline, read unknown value out, read CSR unknown value, just read CSR value
|
||||
|
||||
.macro write64_test ADDR VAL
|
||||
// attempt to write VAL to ADDR
|
||||
// Success outputs:
|
||||
// None
|
||||
// Fault outputs:
|
||||
// 0x6: misaligned address
|
||||
// 0x7: access fault
|
||||
// 0xf: page fault
|
||||
li x29, \VAL
|
||||
li x30, \ADDR
|
||||
sd x29, 0(x30)
|
||||
.endm
|
||||
|
||||
.macro write32_test ADDR VAL
|
||||
// all write tests have the same description/outputs as write64
|
||||
li x29, \VAL
|
||||
li x30, \ADDR
|
||||
sw x29, 0(x30)
|
||||
.endm
|
||||
|
||||
.macro write16_test ADDR VAL
|
||||
// all write tests have the same description/outputs as write64
|
||||
li x29, \VAL
|
||||
li x30, \ADDR
|
||||
sh x29, 0(x30)
|
||||
.endm
|
||||
|
||||
.macro write08_test ADDR VAL
|
||||
// all write tests have the same description/outputs as write64
|
||||
li x29, \VAL
|
||||
li x30, \ADDR
|
||||
sb x29, 0(x30)
|
||||
.endm
|
||||
|
||||
.macro read64_test ADDR
|
||||
// Attempt read at ADDR. Write the value read out to the output *** Consider adding specific test for reading a non known value
|
||||
// Success outputs:
|
||||
// value read out from ADDR
|
||||
// Fault outputs:
|
||||
// One of the following followed by 0xBAD
|
||||
// 0x4: misaligned address
|
||||
// 0x5: access fault
|
||||
// 0xD: page fault
|
||||
li x7, 0xBAD // bad value that will be overwritten on good reads.
|
||||
li x29, \ADDR
|
||||
ld x7, 0(x29)
|
||||
sd x7, 0(x6)
|
||||
addi x6, x6, 8
|
||||
addi x16, x16, 8
|
||||
.endm
|
||||
|
||||
.macro read32_test ADDR
|
||||
// All reads have the same description/outputs as read64.
|
||||
// They will store the sign extended value of what was read out at ADDR
|
||||
li x7, 0xBAD // bad value that will be overwritten on good reads.
|
||||
li x29, \ADDR
|
||||
lw x7, 0(x29)
|
||||
sd x7, 0(x6)
|
||||
addi x6, x6, 8
|
||||
addi x16, x16, 8
|
||||
.endm
|
||||
|
||||
.macro read16_test ADDR
|
||||
// All reads have the same description/outputs as read64.
|
||||
// They will store the sign extended value of what was read out at ADDR
|
||||
li x7, 0xBAD // bad value that will be overwritten on good reads.
|
||||
li x29, \ADDR
|
||||
lh x7, 0(x29)
|
||||
sd x7, 0(x6)
|
||||
addi x6, x6, 8
|
||||
addi x16, x16, 8
|
||||
.endm
|
||||
|
||||
.macro read08_test ADDR
|
||||
// All reads have the same description/outputs as read64.
|
||||
// They will store the sign extended value of what was read out at ADDR
|
||||
li x7, 0xBAD // bad value that will be overwritten on good reads.
|
||||
li x29, \ADDR
|
||||
lb x7, 0(x29)
|
||||
sd x7, 0(x6)
|
||||
addi x6, x6, 8
|
||||
addi x16, x16, 8
|
||||
.endm
|
||||
|
||||
// These goto_x_mode tests all involve invoking the trap handler,
|
||||
// So their outputs are inevitably:
|
||||
// 0x8: test called from U mode
|
||||
// 0x9: test called from S mode
|
||||
// 0xB: test called from M mode
|
||||
// they generally do not fault or cause issues as long as these modes are enabled
|
||||
// *** add functionality to check if modes are enabled before jumping? maybe cause a fault if not?
|
||||
|
||||
.macro goto_m_mode RETURN_VPN RETURN_PAGETYPE
|
||||
li a0, 2 // determine trap handler behavior (go to supervisor mode)
|
||||
li a1, \RETURN_VPN // return VPN
|
||||
li a2, \RETURN_PAGETYPE // return page types
|
||||
ecall // writes mcause to the output.
|
||||
// now in S mode
|
||||
.endm
|
||||
|
||||
.macro goto_s_mode RETURN_VPN RETURN_PAGETYPE
|
||||
li a0, 3 // determine trap handler behavior (go to supervisor mode)
|
||||
li a1, \RETURN_VPN // return VPN
|
||||
li a2, \RETURN_PAGETYPE // return page types
|
||||
ecall // writes mcause to the output.
|
||||
// now in S mode
|
||||
.endm
|
||||
|
||||
.macro goto_u_mode RETURN_VPN RETURN_PAGETYPE
|
||||
li a0, 4 // determine trap handler behavior (go to supervisor mode)
|
||||
li a1, \RETURN_VPN // return VPN
|
||||
li a2, \RETURN_PAGETYPE // return page types
|
||||
ecall // writes mcause to the output.
|
||||
// now in S mode
|
||||
.endm
|
||||
|
||||
// These tests change virtual memory settings, turning it on/off and changing between types.
|
||||
// They don't have outputs as any error with turning on virtual memory should reveal itself in the tests *** Consider changing this policy?
|
||||
|
||||
.macro goto_baremetal
|
||||
// Turn translation off
|
||||
li x7, 0 // satp.MODE value for bare metal (0)
|
||||
slli x7, x7, 60
|
||||
li x28, 0x8000D // Base Pagetable physical page number, satp.PPN field. *** add option for different pagetable location
|
||||
add x7, x7, x28
|
||||
csrw satp, x7
|
||||
sfence.vma x0, x0 // *** flushes global pte's as well
|
||||
.endm
|
||||
|
||||
.macro goto_sv39
|
||||
// Turn on sv39 virtual memory
|
||||
li x7, 8 // satp.MODE value for Sv39 (8)
|
||||
slli x7, x7, 60
|
||||
li x28, 0x8000D // Base Pagetable physical page number, satp.PPN field. *** add option for different pagetable location
|
||||
add x7, x7, x28
|
||||
csrw satp, x7
|
||||
sfence.vma x0, x0 // *** flushes global pte's as well
|
||||
.endm
|
||||
|
||||
.macro goto_sv48
|
||||
// Turn on sv48 virtual memory
|
||||
li x7, 9 // satp.MODE value for Sv39 (8)
|
||||
slli x7, x7, 60
|
||||
li x28, 0x8000D // Base Pagetable physical page number, satp.PPN field. *** add option for different pagetable location
|
||||
add x7, x7, x28
|
||||
csrw satp, x7
|
||||
sfence.vma x0, x0 // *** flushes global pte's as well
|
||||
.endm
|
||||
|
||||
.macro write_read_csr CSR VAL
|
||||
// attempt to write CSR with VAL. Note: this also tests read access to CSR
|
||||
// Success outputs:
|
||||
// value read back out from CSR after writing
|
||||
// Fault outputs:
|
||||
// The previous CSR value before write attempt
|
||||
// *** Most likely 0x2, the mcause for illegal instruction if we don't have write or read access
|
||||
li x30, 0xbad // load bad value to be overwritten by csrr
|
||||
li x29, \VAL
|
||||
csrw \CSR\(), x29
|
||||
csrr x30, \CSR
|
||||
sd x30, 0(x6)
|
||||
addi x6, x6, 8
|
||||
addi x16, x16, 8
|
||||
.endm
|
||||
|
||||
.macro csr_r_access CSR
|
||||
// verify that a csr is accessible to read but not to write
|
||||
// Success outputs:
|
||||
// 0x2, then
|
||||
// 0x11 *** consider changing to something more meaningful
|
||||
// Fault outputs:
|
||||
// 0xBAD *** consider changing this one as well. in general, do we need the branching if it hould cause an illegal instruction fault?
|
||||
csrr x29, \CSR
|
||||
csrwi \CSR\(), 0xA // Attempt to write a 'random' value to the CSR
|
||||
csrr x30, \CSR
|
||||
bne x30, x29, 1f // 1f represents write_access
|
||||
li x30, 0x11 // Write failed, confirming read only permissions.
|
||||
j 2f // j r_access_end
|
||||
1: // w_access (write succeeded, violating read-only)
|
||||
li x30, 0xBAD
|
||||
2: // r_access end
|
||||
sd x30, 0(x6)
|
||||
addi x6, x6, 8
|
||||
addi x16, x16, 8
|
||||
.endm
|
||||
|
||||
.macro execute_at_address ADDR
|
||||
// Execute the code already written to ADDR, returning the value in x7.
|
||||
// *** Note: this test itself doesn't write the code to ADDR because it might be callled at a point where we dont have write access to ADDR
|
||||
// Assumes the code modifies x7, usually to become 0x111.
|
||||
// Sample code: 0x11100393 (li x7, 0x111), 0x00008067 (ret)
|
||||
// Success outputs:
|
||||
// modified value of x7. (0x111 if you use the sample code)
|
||||
// Fault outputs:
|
||||
// One of the following followed by 0xBAD
|
||||
// 0x0: misaligned address
|
||||
// 0x1: access fault
|
||||
// 0xC: page fault
|
||||
fence.i // forces caches and main memory to sync so execution code written to ADDR can run.
|
||||
li x7, 0xBAD
|
||||
li x28, \ADDR
|
||||
jalr x28 // jump to executable test code
|
||||
sd x7, 0(x6)
|
||||
addi x6, x6, 8
|
||||
addi x16, x16, 8
|
||||
.endm
|
||||
|
||||
.macro END_TESTS
|
||||
// invokes one final ecall to return to machine mode then terminates this program, so the output is
|
||||
// 0x8: termination called from U mode
|
||||
// 0x9: termination called from S mode
|
||||
// 0xB: termination called from M mode
|
||||
|
||||
terminate_test:
|
||||
|
||||
li a0, 2 // Trap handler behavior (go to machine mode)
|
||||
ecall // writes mcause to the output.
|
||||
csrw mtvec, x4 // restore original trap handler to halt program
|
||||
|
||||
RVTEST_CODE_END
|
||||
RVMODEL_HALT
|
||||
|
||||
RVTEST_DATA_BEGIN
|
||||
.align 4
|
||||
rvtest_data:
|
||||
.word 0xbabecafe
|
||||
RVTEST_DATA_END
|
||||
|
||||
.align 3 // align stack to 8 byte boundary
|
||||
bottom_of_stack:
|
||||
.fill 1024, 4, 0xdeadbeef
|
||||
top_of_stack:
|
||||
|
||||
|
||||
RVMODEL_DATA_BEGIN
|
||||
|
||||
test_1_res:
|
||||
.fill 1024, 4, 0xdeadbeef
|
||||
|
||||
RVMODEL_DATA_END
|
||||
|
||||
#ifdef rvtest_mtrap_routine
|
||||
|
||||
mtrap_sigptr:
|
||||
.fill 64*(XLEN/32),4,0xdeadbeef
|
||||
|
||||
#endif
|
||||
|
||||
#ifdef rvtest_gpr_save
|
||||
|
||||
gpr_save:
|
||||
.fill 32*(XLEN/32),4,0xdeadbeef
|
||||
|
||||
#endif
|
||||
|
||||
.endm // ends the macro that terminates this test program.
|
||||
@ -1,6 +1,6 @@
|
||||
///////////////////////////////////////////
|
||||
//
|
||||
// WALLY-MMU
|
||||
// WALLY-minfo
|
||||
//
|
||||
// Author: Kip Macsai-Goren <kmacsaigoren@g.hmc.edu>
|
||||
//
|
||||
|
||||
@ -0,0 +1,44 @@
|
||||
///////////////////////////////////////////
|
||||
//
|
||||
// WALLY-misa
|
||||
//
|
||||
// Author: Kip Macsai-Goren <kmacsaigoren@g.hmc.edu>
|
||||
//
|
||||
// Created 2022-02-18
|
||||
//
|
||||
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
|
||||
//
|
||||
// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
|
||||
// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
|
||||
// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
|
||||
// is furnished to do so, subject to the following conditions:
|
||||
//
|
||||
// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
|
||||
//
|
||||
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
|
||||
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
|
||||
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
///////////////////////////////////////////
|
||||
|
||||
#include "WALLY-TEST-LIB-64.h"
|
||||
|
||||
INIT_TESTS
|
||||
|
||||
s_file_begin:
|
||||
// Test 5.3.2.2: Machine ISA register test
|
||||
|
||||
// Misa is a specific case *** so I don't want to add a whole test case for reading nonzero but unkown value CSRs.
|
||||
csrr x30, misa // should not cause a fault in machine mode. *** not writing to output because MISA is different for different configs.
|
||||
li x7, 0x111 // success value for read of nonzero misa
|
||||
bnez x30, misa_nonzero
|
||||
li x7, 0xbad // misa was zero, store bad value
|
||||
|
||||
misa_nonzero:
|
||||
sd x7, 0(x6)
|
||||
addi x6, x6, 8
|
||||
addi x16, x16, 8
|
||||
|
||||
END_TESTS
|
||||
|
||||
TEST_STACK_AND_DATA
|
||||
@ -0,0 +1,35 @@
|
||||
///////////////////////////////////////////
|
||||
//
|
||||
// WALLY-scratch
|
||||
//
|
||||
// Author: Kip Macsai-Goren <kmacsaigoren@g.hmc.edu>
|
||||
//
|
||||
// Created 2022-02-20
|
||||
//
|
||||
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
|
||||
//
|
||||
// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
|
||||
// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
|
||||
// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
|
||||
// is furnished to do so, subject to the following conditions:
|
||||
//
|
||||
// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
|
||||
//
|
||||
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
|
||||
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
|
||||
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
///////////////////////////////////////////
|
||||
|
||||
#include "WALLY-TEST-LIB-64.h"
|
||||
|
||||
INIT_TESTS
|
||||
|
||||
s_file_begin:
|
||||
// Test 5.3.2.3: Scratch registers test
|
||||
|
||||
WRITE_READ_CSR mscratch, 0x111 // check that mscratch is readable and writeable in machine mode
|
||||
|
||||
END_TESTS
|
||||
|
||||
TEST_STACK_AND_DATA
|
||||
@ -0,0 +1,39 @@
|
||||
///////////////////////////////////////////
|
||||
//
|
||||
// WALLY-sscratch
|
||||
//
|
||||
// Author: Kip Macsai-Goren <kmacsaigoren@g.hmc.edu>
|
||||
//
|
||||
// Created 2022-02-20
|
||||
//
|
||||
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
|
||||
//
|
||||
// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
|
||||
// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
|
||||
// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
|
||||
// is furnished to do so, subject to the following conditions:
|
||||
//
|
||||
// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
|
||||
//
|
||||
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
|
||||
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
|
||||
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
///////////////////////////////////////////
|
||||
|
||||
#include "WALLY-TEST-LIB-64.h"
|
||||
|
||||
INIT_TESTS
|
||||
|
||||
s_file_begin:
|
||||
|
||||
// Test 5.3.2.3: Scratch registers test
|
||||
WRITE_READ_CSR sscratch, 0x111 // check that sscratch is readable and writeable in machine mode
|
||||
|
||||
GOTO_S_MODE 0x0, 0x0
|
||||
|
||||
WRITE_READ_CSR sscratch, 0xAAA // check that sscratch is readable and writeable in supervisor mode
|
||||
|
||||
END_TESTS
|
||||
|
||||
TEST_STACK_AND_DATA
|
||||
Loading…
Reference in New Issue
Block a user