forked from Github_Repos/cvw
Fixed floating Sqrt signal when floating point is disabled, causing REMU tohang during buildroot around 3.2M
This commit is contained in:
David Harris
parent
c08811357c
commit
6cf73cdaee
1
.gitignore
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.gitignore
vendored
@ -9,6 +9,7 @@ __pycache__/
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#External repos
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addins/riscv-arch-test/Makefile.include
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addins/riscv-tests/target
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addins/TestFloat-3e/build/Linux-x86_64-GCC/*
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benchmarks/embench/wally*.json
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#vsim work files to ignore
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@ -81,9 +81,9 @@ module fctrl (
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(Fmt == 2'b10 & `ZFH_SUPPORTED) | (Fmt == 2'b11 & `Q_SUPPORTED));
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always_comb
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if (STATUS_FS == 2'b00) // FPU instructions are illegal when FPU is disabled
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ControlsD = `FCTRLW'b0_0_00_xx_0xx_0_1_0;
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ControlsD = `FCTRLW'b0_0_00_xx_000_0_1_0;
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else if (OpD != 7'b0000111 & OpD != 7'b0100111 & ~SupportedFmt)
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ControlsD = `FCTRLW'b0_0_00_xx_0xx_0_1_0; // for anything other than loads and stores, check for supported format
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ControlsD = `FCTRLW'b0_0_00_xx_000_0_1_0; // for anything other than loads and stores, check for supported format
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else case(OpD)
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// FRegWrite_FWriteInt_FResSel_PostProcSel_FOpCtrl_FDivStart_IllegalFPUInstr_FCvtInt
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7'b0000111: case(Funct3D)
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@ -94,7 +94,7 @@ module fctrl (
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else ControlsD = `FCTRLW'b0_0_00_xx_0xx_0_1_0; // flq not supported
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3'b001: if (`ZFH_SUPPORTED) ControlsD = `FCTRLW'b1_0_10_xx_0xx_0_0_0; // flh
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else ControlsD = `FCTRLW'b0_0_00_xx_0xx_0_1_0; // flh not supported
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default: ControlsD = `FCTRLW'b0_0_00_xx_0xx_0_1_0; // non-implemented instruction
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default: ControlsD = `FCTRLW'b0_0_00_xx_000_0_1_0; // non-implemented instruction
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endcase
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7'b0100111: case(Funct3D)
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3'b010: ControlsD = `FCTRLW'b0_0_10_xx_0xx_0_0_0; // fsw
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@ -104,7 +104,7 @@ module fctrl (
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else ControlsD = `FCTRLW'b0_0_00_xx_0xx_0_1_0; // fsq not supported
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3'b001: if (`ZFH_SUPPORTED) ControlsD = `FCTRLW'b0_0_10_xx_0xx_0_0_0; // fsh
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else ControlsD = `FCTRLW'b0_0_00_xx_0xx_0_1_0; // fsh not supported
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default: ControlsD = `FCTRLW'b0_0_00_xx_0xx_0_1_0; // non-implemented instruction
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default: ControlsD = `FCTRLW'b0_0_00_xx_000_0_1_0; // non-implemented instruction
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endcase
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7'b1000011: ControlsD = `FCTRLW'b1_0_01_10_000_0_0_0; // fmadd
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7'b1000111: ControlsD = `FCTRLW'b1_0_01_10_001_0_0_0; // fmsub
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@ -120,23 +120,23 @@ module fctrl (
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3'b000: ControlsD = `FCTRLW'b1_0_00_xx_000_0_0_0; // fsgnj
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3'b001: ControlsD = `FCTRLW'b1_0_00_xx_001_0_0_0; // fsgnjn
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3'b010: ControlsD = `FCTRLW'b1_0_00_xx_010_0_0_0; // fsgnjx
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default: ControlsD = `FCTRLW'b0_0_00_xx_0xx_0_1_0; // non-implemented instruction
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default: ControlsD = `FCTRLW'b0_0_00_xx_000_0_1_0; // non-implemented instruction
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endcase
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7'b00101??: case(Funct3D)
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3'b000: ControlsD = `FCTRLW'b1_0_00_xx_110_0_0_0; // fmin
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3'b001: ControlsD = `FCTRLW'b1_0_00_xx_101_0_0_0; // fmax
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default: ControlsD = `FCTRLW'b0_0_00_xx_0xx_0_1_0; // non-implemented instruction
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default: ControlsD = `FCTRLW'b0_0_00_xx_000_0_1_0; // non-implemented instruction
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endcase
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7'b10100??: case(Funct3D)
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3'b010: ControlsD = `FCTRLW'b0_1_00_xx_010_0_0_0; // feq
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3'b001: ControlsD = `FCTRLW'b0_1_00_xx_001_0_0_0; // flt
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3'b000: ControlsD = `FCTRLW'b0_1_00_xx_011_0_0_0; // fle
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default: ControlsD = `FCTRLW'b0_0_00_xx_0xx__0_1_0; // non-implemented instruction
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default: ControlsD = `FCTRLW'b0_0_00_xx_000__0_1_0; // non-implemented instruction
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endcase
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7'b11100??: if (Funct3D == 3'b001) ControlsD = `FCTRLW'b0_1_10_xx_000_0_0_0; // fclass
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else if (Funct3D[1:0] == 2'b00) ControlsD = `FCTRLW'b0_1_11_xx_000_0_0_0; // fmv.x.w to int reg
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else if (Funct3D[1:0] == 2'b01) ControlsD = `FCTRLW'b0_1_11_xx_000_0_0_0; // fmv.x.d to int reg
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else ControlsD = `FCTRLW'b0_0_00_xx_0xx_0_1_0; // non-implemented instruction
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else ControlsD = `FCTRLW'b0_0_00_xx_000_0_1_0; // non-implemented instruction
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7'b1101000: case(Rs2D[1:0])
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2'b00: ControlsD = `FCTRLW'b1_0_01_00_101_0_0_0; // fcvt.s.w w->s
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2'b01: ControlsD = `FCTRLW'b1_0_01_00_100_0_0_0; // fcvt.s.wu wu->s
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@ -165,7 +165,7 @@ module fctrl (
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endcase
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7'b1111001: ControlsD = `FCTRLW'b1_0_00_xx_011_0_0_0; // fmv.d.x to fp reg
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7'b0100001: ControlsD = `FCTRLW'b1_0_01_00_001_0_0_0; // fcvt.d.s
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default: ControlsD = `FCTRLW'b0_0_00_xx_0xx_0_1_0; // non-implemented instruction
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default: ControlsD = `FCTRLW'b0_0_00_xx_000_0_1_0; // non-implemented instruction
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endcase
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default: ControlsD = `FCTRLW'b0_0_00_xx_000_0_1_0; // non-implemented instruction
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endcase
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@ -82,7 +82,7 @@ module testbenchfp;
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logic [`LOGCVTLEN-1:0] CvtShiftAmtE; // how much to shift by
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logic [`DIVb:0] Quot;
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logic CvtResDenormUfE;
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logic DivStart, FDivBusyE;
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logic DivStart, FDivBusyE, OldFDivBusyE;
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logic reset = 1'b0;
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logic [$clog2(`NF+2)-1:0] XZeroCnt, YZeroCnt;
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logic [`DURLEN-1:0] Dur;
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@ -689,12 +689,12 @@ module testbenchfp;
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.Xe(Xe), .Ye(Ye), .Ze(Ze),
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.Xm(Xm), .Ym(Ym), .Zm(Zm),
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.XZero, .YZero, .ZZero, .Ss, .Se,
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.OpCtrl(OpCtrlVal), .Fmt(ModFmt), .Sm, .InvA, .SCnt, .As, .Ps,
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.OpCtrl(OpCtrlVal), .Sm, .InvA, .SCnt, .As, .Ps,
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.ZmSticky);
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end
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postprocess postprocess(.Xs(Xs), .Ys(Ys), .PostProcSel(UnitVal[1:0]),
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.Ze(Ze), .ZDenorm(ZDenorm), .OpCtrl(OpCtrlVal), .DivQm(Quot), .DivQe(DivCalcExp),
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.ZDenorm(ZDenorm), .OpCtrl(OpCtrlVal), .DivQm(Quot), .DivQe(DivCalcExp),
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.Xm(Xm), .Ym(Ym), .Zm(Zm), .CvtCe(CvtCalcExpE), .DivS(DivSticky), .FmaSs(Ss),
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.XNaN(XNaN), .YNaN(YNaN), .ZNaN(ZNaN), .CvtResDenormUf(CvtResDenormUfE),
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.XZero(XZero), .YZero(YZero), .ZZero(ZZero), .CvtShiftAmt(CvtShiftAmtE),
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@ -719,8 +719,8 @@ module testbenchfp;
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fdivsqrt fdivsqrt(.clk, .reset, .XsE(Xs), .FmtE(ModFmt), .XmE(Xm), .YmE(Ym), .XeE(Xe), .YeE(Ye), .SqrtE(OpCtrlVal[0]), .SqrtM(OpCtrlVal[0]),
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.XInfE(XInf), .YInfE(YInf), .XZeroE(XZero), .YZeroE(YZero), .XNaNE(XNaN), .YNaNE(YNaN),
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.FDivStartE(DivStart), .IDivStartE(1'b0), .MDUE(1'b0), .W64E(1'b0),
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.StallE(1'b0), .StallM(1'b0), .DivSM(DivSticky), .FDivBusyE, .QeM(DivCalcExp),
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.QmM(Quot), .DivDone);
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.StallM(1'b0), .DivSM(DivSticky), .FDivBusyE, .QeM(DivCalcExp),
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.QmM(Quot));
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end
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assign CmpFlg[3:0] = 0;
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@ -811,6 +811,9 @@ end
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logic ResMatch, FlagMatch, CheckNow;
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always @(posedge clk)
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OldFDivBusyE = FDivBusyE;
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// check results on falling edge of clk
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always @(negedge clk) begin
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@ -883,6 +886,7 @@ always @(negedge clk) begin
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ResMatch = (Res === Ans | NaNGood | NaNGood === 1'bx);
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FlagMatch = (ResFlg === AnsFlg | AnsFlg === 5'bx);
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divsqrtop = OpCtrlVal == `SQRT_OPCTRL | OpCtrlVal == `DIV_OPCTRL;
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assign DivDone = OldFDivBusyE & ~FDivBusyE;
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//assign divsqrtop = OpCtrl[TestNum] == `SQRT_OPCTRL | OpCtrl[TestNum] == `DIV_OPCTRL;
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CheckNow = (DivDone | ~divsqrtop) & (UnitVal !== `CVTINTUNIT)&(UnitVal !== `CMPUNIT);
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