forked from Github_Repos/cvw
Update ram2 and other memories and associated wrappers
This commit is contained in:
James Stine
parent
73b29e1f71
commit
6ce80b6b8a
@ -5,7 +5,9 @@
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// Two port SRAM 1 read port and 1 write port.
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// When clk rises Addr and LineWriteData are sampled.
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// Following the clk edge read data is output from the sampled Addr.
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// Write
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// Write
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// Modified: james.stine@okstate.edu Feb 1, 2023
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// Integration of memories
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//
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// Purpose: Storage and read/write access to data cache data, tag valid, dirty, and replacement.
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//
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@ -42,31 +44,79 @@ module ram2p1r1wbe #(parameter DEPTH=128, WIDTH=256) (
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output logic [WIDTH-1:0] rd1
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);
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logic [WIDTH-1:0] mem[DEPTH-1:0];
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logic [WIDTH-1:0] mem[DEPTH-1:0];
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localparam SRAMWIDTH = 32;
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localparam SRAMNUMSETS = SRAMWIDTH/WIDTH;
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// ***************************************************************************
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// TRUE Smem macro
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// ***************************************************************************
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// ***************************************************************************
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// READ first SRAM model
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// ***************************************************************************
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integer i;
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if (`USE_SRAM == 1 && WIDTH == 68 && DEPTH == 1024) begin
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ram2p1r1wbe_1024x68 memory1(.CLKA(clk), .CLKB(clk),
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.CEBA(~ce1), .CEBB(~ce2),
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.WEBA('0), .WEBB(~we2),
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.AA(ra1), .AB(wa2),
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.DA('0),
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.DB(wd2),
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.BWEBA('0), .BWEBB('1),
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.QA(rd1),
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.QB());
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// Read
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always_ff @(posedge clk)
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if(ce1) rd1 <= #1 mem[ra1];
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// Write divided into part for bytes and part for extra msbs
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if(WIDTH >= 8)
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always @(posedge clk)
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if (ce2 & we2)
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for(i = 0; i < WIDTH/8; i++)
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if(bwe2[i]) mem[wa2][i*8 +: 8] <= #1 wd2[i*8 +: 8];
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if (WIDTH%8 != 0) // handle msbs if width not a multiple of 8
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always @(posedge clk)
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if (ce2 & we2 & bwe2[WIDTH/8])
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mem[wa2][WIDTH-1:WIDTH-WIDTH%8] <= #1 wd2[WIDTH-1:WIDTH-WIDTH%8];
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end else if (`USE_SRAM == 1 && WIDTH == 2 && DEPTH == 1024) begin
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logic [SRAMWIDTH-1:0] SRAMReadData;
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logic [SRAMWIDTH-1:0] SRAMWriteData;
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logic [SRAMWIDTH-1:0] RD1Sets[SRAMNUMSETS-1:0];
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logic [SRAMNUMSETS-1:0] SRAMBitMaskPre;
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logic [SRAMWIDTH-1:0] SRAMBitMask;
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logic [$clog2(DEPTH)-1:0] RA1Q;
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onehotdecoder #($clog2(SRAMNUMSETS)) oh1(wa2[$clog2(SRAMNUMSETS)-1:0], SRAMBitMaskPre);
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genvar index;
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for (index = 0; index < SRAMNUMSETS; index++) begin:readdatalinesetsmux
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assign RD1Sets[index] = SRAMReadData[(index*WIDTH)+WIDTH-1 : (index*WIDTH)];
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assign SRAMWriteData[index*2+1:index*2] = wd2;
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assign SRAMBitMask[index*2+1:index*2] = {2{SRAMBitMaskPre[index]}};
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end
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flopen #($clog2(DEPTH)) mem_reg1 (clk, ce1, ra1, RA1Q);
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assign rd1 = RD1Sets[RA1Q[$clog2(SRAMWIDTH)-1:0]];
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ram2p1r1wbe_64x32 memory2(.CLKA(clk), .CLKB(clk),
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.CEBA(~ce1), .CEBB(~ce2),
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.WEBA('0), .WEBB(~we2),
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.AA(ra1[$clog2(DEPTH)-1:$clog2(SRAMNUMSETS)]),
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.AB(wa2[$clog2(DEPTH)-1:$clog2(SRAMNUMSETS)]),
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.DA('0),
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.DB(SRAMWriteData),
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.BWEBA('0), .BWEBB(SRAMBitMask),
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.QA(SRAMReadData),
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.QB());
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end else begin
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// ***************************************************************************
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// READ first SRAM model
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// ***************************************************************************
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integer i;
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// Read
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always_ff @(posedge clk)
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if(ce1) rd1 <= #1 mem[ra1];
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// Write divided into part for bytes and part for extra msbs
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if(WIDTH >= 8)
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always @(posedge clk)
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if (ce2 & we2)
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for(i = 0; i < WIDTH/8; i++)
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if(bwe2[i]) mem[wa2][i*8 +: 8] <= #1 wd2[i*8 +: 8];
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if (WIDTH%8 != 0) // handle msbs if width not a multiple of 8
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always @(posedge clk)
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if (ce2 & we2 & bwe2[WIDTH/8])
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mem[wa2][WIDTH-1:WIDTH-WIDTH%8] <= #1 wd2[WIDTH-1:WIDTH-WIDTH%8];
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end
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endmodule
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@ -1,5 +1,5 @@
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///////////////////////////////////////////
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// ram2p1rwbe_1024x69.sv
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// ram2p1rwbe_1024x68.sv
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//
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// Written: james.stine@okstate.edu 28 January 2023
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// Modified:
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@ -24,7 +24,7 @@
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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module ram2p1r1wbe_1024x69(
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module ram2p1r1wbe_1024x68(
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input logic CLKA,
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input logic CLKB,
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input logic CEBA,
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@ -33,16 +33,16 @@ module ram2p1r1wbe_1024x69(
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input logic WEBB,
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input logic [9:0] AA,
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input logic [9:0] AB,
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input logic [68:0] DA,
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input logic [68:0] DB,
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input logic [68:0] BWEBA,
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input logic [68:0] BWEBB,
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output logic [68:0] QA,
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output logic [68:0] QB
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input logic [67:0] DA,
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input logic [67:0] DB,
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input logic [67:0] BWEBA,
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input logic [67:0] BWEBB,
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output logic [67:0] QA,
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output logic [67:0] QB
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);
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// replace "generic1024x69RAM" with "TSDN..1024X69.." module from your memory vendor
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generic1024x69RAM sramIP (.CLKA, .CLKB, .CEBA, .CEBB, .WEBA, .WEBB,
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generic1024x68RAM sramIP (.CLKA, .CLKB, .CEBA, .CEBB, .WEBA, .WEBB,
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.AA, .AB, .DA, .DB, .BWEBA, .BWEBB, .QA, .QB);
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endmodule
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48
pipelined/src/generic/mem/ram2p1r1wbe_64x32.sv
Executable file
48
pipelined/src/generic/mem/ram2p1r1wbe_64x32.sv
Executable file
@ -0,0 +1,48 @@
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///////////////////////////////////////////
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// ram2p1rwbe_64x32.sv
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//
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// Written: james.stine@okstate.edu 28 January 2023
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// Modified:
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//
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// Purpose: RAM wrapper for instantiating RAM IP
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//
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// A component of the CORE-V-WALLY configurable RISC-V project.
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//
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// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
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//
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// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
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//
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// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
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// except in compliance with the License, or, at your option, the Apache License version 2.0. You
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// may obtain a copy of the License at
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//
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// https://solderpad.org/licenses/SHL-2.1/
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//
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// Unless required by applicable law or agreed to in writing, any work distributed under the
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// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
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// either express or implied. See the License for the specific language governing permissions
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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module ram2p1r1wbe_64x32(
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input logic CLKA,
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input logic CLKB,
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input logic CEBA,
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input logic CEBB,
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input logic WEBA,
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input logic WEBB,
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input logic [5:0] AA,
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input logic [5:0] AB,
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input logic [31:0] DA,
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input logic [31:0] DB,
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input logic [31:0] BWEBA,
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input logic [31:0] BWEBB,
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output logic [31:0] QA,
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output logic [31:0] QB
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);
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// replace "generic64x32RAM" with "TSDN..64X32.." module from your memory vendor
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generic64x32RAM sramIP (.CLKA, .CLKB, .CEBA, .CEBB, .WEBA, .WEBB,
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.AA, .AB, .DA, .DB, .BWEBA, .BWEBB, .QA, .QB);
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endmodule
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@ -27,74 +27,73 @@
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`include "wally-config.vh"
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module rom1p1r
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#(
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//--------------------------------------------------------------------------
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parameter ADDR_WIDTH = 8,
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// Addr Width in bits : 2 **ADDR_WIDTH = RAM Depth
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parameter DATA_WIDTH = 32, // Data Width in bits
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parameter PRELOAD_ENABLED = 0
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//----------------------------------------------------------------------
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) (
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input logic clk,
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input logic ce,
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input logic [ADDR_WIDTH-1:0] addr,
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output logic [DATA_WIDTH-1:0] dout
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);
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// Core Memory
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logic [DATA_WIDTH-1:0] ROM [(2**ADDR_WIDTH)-1:0];
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module rom1p1r #(parameter ADDR_WIDTH = 8,
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parameter DATA_WIDTH = 32,
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parameter PRELOAD_ENABLED = 0)
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(input logic clk,
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input logic ce,
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input logic [ADDR_WIDTH-1:0] addr,
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output logic [DATA_WIDTH-1:0] dout
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);
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always @ (posedge clk) begin
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if(ce) dout <= ROM[addr];
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end
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// Core Memory
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logic [DATA_WIDTH-1:0] ROM [(2**ADDR_WIDTH)-1:0];
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if (`USE_SRAM == 1 && DATA_WIDTH == 64 && `XLEN == 64) begin
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rom1p1r_128x64 rom1 (.CLK(clk), .CEB(~ce), .A(addr[6:0]), .Q(dout));
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// for FPGA, initialize with zero-stage bootloader
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if(PRELOAD_ENABLED) begin
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initial begin
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ROM[0] = 64'h9581819300002197;
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ROM[1] = 64'h4281420141014081;
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ROM[2] = 64'h4481440143814301;
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ROM[3] = 64'h4681460145814501;
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ROM[4] = 64'h4881480147814701;
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ROM[5] = 64'h4a814a0149814901;
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ROM[6] = 64'h4c814c014b814b01;
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ROM[7] = 64'h4e814e014d814d01;
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ROM[8] = 64'h0110011b4f814f01;
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ROM[9] = 64'h059b45011161016e;
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ROM[10] = 64'h0004063705fe0010;
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ROM[11] = 64'h05a000ef8006061b;
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ROM[12] = 64'h0ff003930000100f;
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ROM[13] = 64'h4e952e3110060e37;
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ROM[14] = 64'hc602829b0053f2b7;
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ROM[15] = 64'h2023fe02dfe312fd;
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ROM[16] = 64'h829b0053f2b7007e;
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ROM[17] = 64'hfe02dfe312fdc602;
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ROM[18] = 64'h4de31efd000e2023;
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ROM[19] = 64'h059bf1402573fdd0;
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ROM[20] = 64'h0000061705e20870;
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ROM[21] = 64'h0010029b01260613;
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ROM[22] = 64'h11010002806702fe;
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ROM[23] = 64'h84b2842ae426e822;
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ROM[24] = 64'h892ee04aec064511;
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ROM[25] = 64'h06e000ef07e000ef;
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ROM[26] = 64'h979334fd02905563;
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ROM[27] = 64'h07930177d4930204;
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ROM[28] = 64'h4089093394be2004;
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ROM[29] = 64'h04138522008905b3;
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ROM[30] = 64'h19e3014000ef2004;
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ROM[31] = 64'h64a2644260e2fe94;
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ROM[32] = 64'h6749808261056902;
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ROM[33] = 64'hdfed8b8510472783;
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ROM[34] = 64'h2423479110a73823;
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ROM[35] = 64'h10472783674910f7;
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ROM[36] = 64'h20058693ffed8b89;
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ROM[37] = 64'h05a1118737836749;
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ROM[38] = 64'hfed59be3fef5bc23;
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ROM[39] = 64'h1047278367498082;
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ROM[40] = 64'h47858082dfed8b85;
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ROM[41] = 64'h40a7853b4015551b;
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ROM[42] = 64'h808210a7a02367c9;
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end
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end
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endmodule // bytewrite_tdp_ram_rf
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end else begin
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always @ (posedge clk) begin
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if(ce) dout <= ROM[addr];
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end
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// for FPGA, initialize with zero-stage bootloader
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if(PRELOAD_ENABLED) begin
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initial begin
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ROM[0] = 64'h9581819300002197;
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ROM[1] = 64'h4281420141014081;
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ROM[2] = 64'h4481440143814301;
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ROM[3] = 64'h4681460145814501;
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ROM[4] = 64'h4881480147814701;
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ROM[5] = 64'h4a814a0149814901;
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ROM[6] = 64'h4c814c014b814b01;
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ROM[7] = 64'h4e814e014d814d01;
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ROM[8] = 64'h0110011b4f814f01;
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ROM[9] = 64'h059b45011161016e;
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ROM[10] = 64'h0004063705fe0010;
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ROM[11] = 64'h05a000ef8006061b;
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ROM[12] = 64'h0ff003930000100f;
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ROM[13] = 64'h4e952e3110060e37;
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ROM[14] = 64'hc602829b0053f2b7;
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ROM[15] = 64'h2023fe02dfe312fd;
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ROM[16] = 64'h829b0053f2b7007e;
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ROM[17] = 64'hfe02dfe312fdc602;
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ROM[18] = 64'h4de31efd000e2023;
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ROM[19] = 64'h059bf1402573fdd0;
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ROM[20] = 64'h0000061705e20870;
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ROM[21] = 64'h0010029b01260613;
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ROM[22] = 64'h11010002806702fe;
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ROM[23] = 64'h84b2842ae426e822;
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ROM[24] = 64'h892ee04aec064511;
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ROM[25] = 64'h06e000ef07e000ef;
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ROM[26] = 64'h979334fd02905563;
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ROM[27] = 64'h07930177d4930204;
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ROM[28] = 64'h4089093394be2004;
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ROM[29] = 64'h04138522008905b3;
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ROM[30] = 64'h19e3014000ef2004;
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ROM[31] = 64'h64a2644260e2fe94;
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ROM[32] = 64'h6749808261056902;
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ROM[33] = 64'hdfed8b8510472783;
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ROM[34] = 64'h2423479110a73823;
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ROM[35] = 64'h10472783674910f7;
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ROM[36] = 64'h20058693ffed8b89;
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ROM[37] = 64'h05a1118737836749;
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ROM[38] = 64'hfed59be3fef5bc23;
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ROM[39] = 64'h1047278367498082;
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ROM[40] = 64'h47858082dfed8b85;
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ROM[41] = 64'h40a7853b4015551b;
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ROM[42] = 64'h808210a7a02367c9;
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end
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end
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end
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endmodule
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@ -4,7 +4,7 @@
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// Written: james.stine@okstate.edu 28 January 2023
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// Modified:
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//
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// Purpose: RAM wrapper for instantiating RAM IP
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// Purpose: ROM wrapper for instantiating ROM IP
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//
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// A component of the CORE-V-WALLY configurable RISC-V project.
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//
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37
pipelined/src/generic/mem/rom1p1r_128x64.sv
Executable file
37
pipelined/src/generic/mem/rom1p1r_128x64.sv
Executable file
@ -0,0 +1,37 @@
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///////////////////////////////////////////
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// rom1p1r_128x64.sv
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//
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// Written: james.stine@okstate.edu 28 January 2023
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// Modified:
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//
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// Purpose: ROM wrapper for instantiating ROM IP
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//
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// A component of the CORE-V-WALLY configurable RISC-V project.
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//
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// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
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//
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// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
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//
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// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
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// except in compliance with the License, or, at your option, the Apache License version 2.0. You
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// may obtain a copy of the License at
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//
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// https://solderpad.org/licenses/SHL-2.1/
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//
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// Unless required by applicable law or agreed to in writing, any work distributed under the
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// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
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// either express or implied. See the License for the specific language governing permissions
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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module rom1p1r_128x64(
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input logic CLK,
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input logic CEB,
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input logic [6:0] A,
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output logic [63:0] Q
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);
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// replace "generic64x128RAM" with "TS3N..64X128.." module from your memory vendor
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generic64x128ROM romIP (.CLK, .CEB, .A, .Q);
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endmodule
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