forked from Github_Repos/cvw
Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
This commit is contained in:
David Harris
commit
af8f1ab786
@ -37,14 +37,13 @@ module alu #(parameter WIDTH=32) (
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input logic [1:0] BSelect, // Binary encoding of if it's a ZBA_ZBB_ZBC_ZBS instruction
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input logic [2:0] ZBBSelect, // ZBB mux select signal
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input logic [2:0] Funct3, // For BMU decoding
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input logic CompLT, // Less-Than flag from comparator
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input logic [2:0] BALUControl, // ALU Control signals for B instructions in Execute Stage
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output logic [WIDTH-1:0] Result, // ALU result
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output logic [WIDTH-1:0] ALUResult, // ALU result
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output logic [WIDTH-1:0] Sum); // Sum of operands
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// CondInvB = ~B when subtracting, B otherwise. Shift = shift result. SLT/U = result of a slt/u instruction.
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// FullResult = ALU result before adjusting for a RV64 w-suffix instruction.
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logic [WIDTH-1:0] CondMaskInvB, Shift, FullResult, ALUResult; // Intermediate Signals
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logic [WIDTH-1:0] CondMaskInvB, Shift, FullResult, PreALUResult; // Intermediate Signals
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logic [WIDTH-1:0] CondMaskB; // Result of B mask select mux
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logic [WIDTH-1:0] CondShiftA; // Result of A shifted select mux
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logic [WIDTH-1:0] CondExtA; // Result of Zero Extend A select mux
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@ -84,16 +83,16 @@ module alu #(parameter WIDTH=32) (
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end
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// Support RV64I W-type addw/subw/addiw/shifts that discard upper 32 bits and sign-extend 32-bit result to 64 bits
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if (WIDTH == 64) assign ALUResult = W64 ? {{32{FullResult[31]}}, FullResult[31:0]} : FullResult;
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else assign ALUResult = FullResult;
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if (WIDTH == 64) assign PreALUResult = W64 ? {{32{FullResult[31]}}, FullResult[31:0]} : FullResult;
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else assign PreALUResult = FullResult;
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// Final Result B instruction select mux
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if (`ZBC_SUPPORTED | `ZBS_SUPPORTED | `ZBA_SUPPORTED | `ZBB_SUPPORTED) begin : bitmanipalu
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bitmanipalu #(WIDTH) balu(.A, .B, .W64, .BSelect, .ZBBSelect,
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.Funct3, .CompLT, .BALUControl, .ALUResult, .FullResult,
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.CondMaskB, .CondShiftA, .Result);
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.Funct3, .LT,.LTU, .BALUControl, .PreALUResult, .FullResult,
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.CondMaskB, .CondShiftA, .ALUResult);
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end else begin
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assign Result = ALUResult;
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assign ALUResult = PreALUResult;
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assign CondMaskB = B;
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assign CondShiftA = A;
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end
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@ -35,12 +35,13 @@ module bitmanipalu #(parameter WIDTH=32) (
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input logic [1:0] BSelect, // Binary encoding of if it's a ZBA_ZBB_ZBC_ZBS instruction
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input logic [2:0] ZBBSelect, // ZBB mux select signal
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input logic [2:0] Funct3, // Funct3 field of opcode indicates operation to perform
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input logic CompLT, // Less-Than flag from comparator
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input logic LT, // less than flag
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input logic LTU, // less than unsigned flag
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input logic [2:0] BALUControl, // ALU Control signals for B instructions in Execute Stage
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input logic [WIDTH-1:0] ALUResult, FullResult, // ALUResult, FullResult signals
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input logic [WIDTH-1:0] PreALUResult, FullResult,// PreALUResult, FullResult signals
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output logic [WIDTH-1:0] CondMaskB, // B is conditionally masked for ZBS instructions
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output logic [WIDTH-1:0] CondShiftA, // A is conditionally shifted for ShAdd instructions
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output logic [WIDTH-1:0] Result); // Result
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output logic [WIDTH-1:0] ALUResult); // Result
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logic [WIDTH-1:0] ZBBResult, ZBCResult; // ZBB, ZBC Result
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logic [WIDTH-1:0] MaskB; // BitMask of B
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@ -84,16 +85,16 @@ module bitmanipalu #(parameter WIDTH=32) (
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// ZBB Unit
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if (`ZBB_SUPPORTED) begin: zbb
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zbb #(WIDTH) ZBB(.A, .RevA, .B, .W64, .lt(CompLT), .ZBBSelect, .ZBBResult);
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zbb #(WIDTH) ZBB(.A, .RevA, .B, .W64, .LT, .LTU, .BUnsigned(Funct3[0]), .ZBBSelect, .ZBBResult);
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end else assign ZBBResult = 0;
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// Result Select Mux
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always_comb
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case (BSelect)
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// 00: ALU, 01: ZBA/ZBS, 10: ZBB, 11: ZBC
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2'b00: Result = ALUResult;
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2'b01: Result = FullResult; // NOTE: We don't use ALUResult because ZBA/ZBS instructions don't sign extend the MSB of the right-hand word.
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2'b10: Result = ZBBResult;
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2'b11: Result = ZBCResult;
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2'b00: ALUResult = PreALUResult;
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2'b01: ALUResult = FullResult; // NOTE: We don't use ALUResult because ZBA/ZBS instructions don't sign extend the MSB of the right-hand word.
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2'b10: ALUResult = ZBBResult;
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2'b11: ALUResult = ZBCResult;
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endcase
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endmodule
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@ -48,7 +48,6 @@ module bmuctrl(
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output logic [1:0] BSelectE, // Indicates if ZBA_ZBB_ZBC_ZBS instruction in one-hot encoding
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output logic [2:0] ZBBSelectE, // ZBB mux select signal
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output logic BRegWriteE, // Indicates if it is a R type B instruction in Execute
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output logic BComparatorSignedE, // Indicates if comparator signed in Execute Stage
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output logic [2:0] BALUControlE // ALU Control signals for B instructions in Execute Stage
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);
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@ -56,7 +55,6 @@ module bmuctrl(
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logic [2:0] Funct3D; // Funct3 field in Decode stage
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logic [6:0] Funct7D; // Funct7 field in Decode stage
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logic [4:0] Rs2D; // Rs2 source register in Decode stage
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logic BComparatorSignedD; // Indicates if comparator signed (max, min instruction) in Decode Stage
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logic RotateD; // Indicates if rotate instruction in Decode Stage
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logic MaskD; // Indicates if zbs instruction in Decode Stage
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logic PreShiftD; // Indicates if sh1add, sh2add, sh3add instruction in Decode Stage
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@ -112,10 +110,10 @@ module bmuctrl(
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BMUControlsD = `BMUCTRLW'b000_10_010_1_1_0_1_0_0_0_0_0; // rev8
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17'b0010011_0010100_101: if (Rs2D[4:0] == 5'b00111)
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BMUControlsD = `BMUCTRLW'b000_10_010_1_1_0_1_0_0_0_0_0; // orc.b
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17'b0110011_0000101_110: BMUControlsD = `BMUCTRLW'b000_10_111_1_0_0_1_0_0_0_0_0; // max
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17'b0110011_0000101_111: BMUControlsD = `BMUCTRLW'b000_10_111_1_0_0_1_0_0_0_0_0; // maxu
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17'b0110011_0000101_100: BMUControlsD = `BMUCTRLW'b000_10_011_1_0_0_1_0_0_0_0_0; // min
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17'b0110011_0000101_101: BMUControlsD = `BMUCTRLW'b000_10_011_1_0_0_1_0_0_0_0_0; // minu
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17'b0110011_0000101_110: BMUControlsD = `BMUCTRLW'b000_10_111_1_0_0_1_1_0_0_0_0; // max
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17'b0110011_0000101_111: BMUControlsD = `BMUCTRLW'b000_10_111_1_0_0_1_1_0_0_0_0; // maxu
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17'b0110011_0000101_100: BMUControlsD = `BMUCTRLW'b000_10_011_1_0_0_1_1_0_0_0_0; // min
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17'b0110011_0000101_101: BMUControlsD = `BMUCTRLW'b000_10_011_1_0_0_1_1_0_0_0_0; // minu
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endcase
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if (`XLEN==32)
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casez({OpD, Funct7D, Funct3D})
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@ -174,12 +172,9 @@ module bmuctrl(
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// Pack BALUControl Signals
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assign BALUControlD = {RotateD, MaskD, PreShiftD};
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// Comparator should perform signed comparison when min/max instruction. We have overlap in funct3 with some branch instructions so we use opcode to differentiate betwen min/max and branches
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assign BComparatorSignedD = (Funct3D[2]^Funct3D[0]) & ~OpD[6];
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// Choose ALUSelect brom BMU for BMU operations, Funct3 for IEU operations, or 0 for addition
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assign ALUSelectD = BALUOpD ? BALUSelectD : (ALUOpD ? Funct3D : 3'b000);
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// BMU Execute stage pipieline control register
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flopenrc#(10) controlregBMU(clk, reset, FlushE, ~StallE, {BSelectD, ZBBSelectD, BRegWriteD, BComparatorSignedD, BALUControlD}, {BSelectE, ZBBSelectE, BRegWriteE, BComparatorSignedE, BALUControlE});
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flopenrc#(9) controlregBMU(clk, reset, FlushE, ~StallE, {BSelectD, ZBBSelectD, BRegWriteD, BALUControlD}, {BSelectE, ZBBSelectE, BRegWriteE, BALUControlE});
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endmodule
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@ -30,20 +30,20 @@
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`include "wally-config.vh"
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module clmul #(parameter WIDTH=32) (
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input logic [WIDTH-1:0] A, B, // Operands
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input logic [WIDTH-1:0] X, Y, // Operands
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output logic [WIDTH-1:0] ClmulResult); // ZBS result
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logic [(WIDTH*WIDTH)-1:0] s; // intermediary signals for carry-less multiply
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logic [(WIDTH*WIDTH)-1:0] S; // intermediary signals for carry-less multiply
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integer i,j;
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always_comb begin
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for (i=0;i<WIDTH;i++) begin: outer
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s[WIDTH*i]=A[0]&B[i];
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S[WIDTH*i] = X[0] & Y[i];
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for (j=1;j<=i;j++) begin: inner
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s[WIDTH*i+j] = (A[j]&B[i-j])^s[WIDTH*i+j-1];
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S[WIDTH*i+j] = (X[j] & Y[i-j]) ^ S[WIDTH*i+j-1];
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end
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ClmulResult[i] = s[WIDTH*i+j-1];
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ClmulResult[i] = S[WIDTH*i+j-1];
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end
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end
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endmodule
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@ -33,21 +33,25 @@
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module zbb #(parameter WIDTH=32) (
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input logic [WIDTH-1:0] A, RevA, B, // Operands
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input logic W64, // Indicates word operation
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input logic lt, // lt flag
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input logic LT, // lt flag
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input logic LTU, // ltu flag
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input logic BUnsigned, // max/min (signed) flag
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input logic [2:0] ZBBSelect, // ZBB Result select signal
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output logic [WIDTH-1:0] ZBBResult); // ZBB result
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logic lt; // lt given signed/unsigned
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logic [WIDTH-1:0] CntResult; // count result
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logic [WIDTH-1:0] MinMaxResult; // min, max result
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logic [WIDTH-1:0] ByteResult; // byte results
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logic [WIDTH-1:0] ExtResult; // sign/zero extend results
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mux2 #(1) ltmux(LT, LTU, BUnsigned , lt);
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cnt #(WIDTH) cnt(.A, .RevA, .B(B[1:0]), .W64, .CntResult);
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byteUnit #(WIDTH) bu(.A, .ByteSelect(B[0]), .ByteResult);
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ext #(WIDTH) ext(.A, .ExtSelect({~B[2], {B[2] & B[0]}}), .ExtResult);
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// ZBBSelect[2] differentiates between min(u) vs max(u) instruction
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mux2 #(WIDTH) minmaxmux(B, A, lt^ZBBSelect[2], MinMaxResult);
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mux2 #(WIDTH) minmaxmux(B, A, ZBBSelect[2]^lt, MinMaxResult);
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// ZBB Result select mux
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mux4 #(WIDTH) zbbresultmux(CntResult, ExtResult, ByteResult, MinMaxResult, ZBBSelect[1:0], ZBBResult);
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@ -36,19 +36,16 @@ module zbc #(parameter WIDTH=32) (
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logic [WIDTH-1:0] ClmulResult, RevClmulResult;
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logic [WIDTH-1:0] RevB;
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logic [WIDTH-1:0] x,y;
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logic [1:0] select;
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logic [WIDTH-1:0] X, Y;
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assign select = ~Funct3[1:0];
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bitreverse #(WIDTH) brB(B, RevB);
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bitreverse #(WIDTH) brB(.A(B), .RevA(RevB));
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mux3 #(WIDTH) xmux({RevA[WIDTH-2:0], {1'b0}}, RevA, A, ~Funct3[1:0], X);
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mux3 #(WIDTH) ymux({{1'b0}, RevB[WIDTH-2:0]}, RevB, B, ~Funct3[1:0], Y);
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mux3 #(WIDTH) xmux({RevA[WIDTH-2:0], {1'b0}}, RevA, A, select, x);
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mux3 #(WIDTH) ymux({{1'b0},RevB[WIDTH-2:0]}, RevB, B, select, y);
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clmul #(WIDTH) clm(.A(x), .B(y), .ClmulResult(ClmulResult));
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clmul #(WIDTH) clm(.X, .Y, .ClmulResult);
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bitreverse #(WIDTH) brClmulResult(.A(ClmulResult), .RevA(RevClmulResult));
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bitreverse #(WIDTH) brClmulResult(ClmulResult, RevClmulResult);
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mux2 #(WIDTH) zbcresultmux(ClmulResult, RevClmulResult, Funct3[1], ZBCResult);
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endmodule
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@ -125,7 +125,6 @@ module controller(
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logic IntDivM; // Integer divide instruction
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logic [1:0] BSelectD; // One-Hot encoding if it's ZBA_ZBB_ZBC_ZBS instruction in decode stage
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logic [2:0] ZBBSelectD; // ZBB Mux Select Signal
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logic BComparatorSignedE; // Indicates if max, min (signed comarison) instruction in Execute Stage
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logic IFunctD, RFunctD, MFunctD; // Detect I, R, and M-type RV32IM/Rv64IM instructions
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logic LFunctD, SFunctD, BFunctD; // Detect load, store, branch instructions
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logic JFunctD; // detect jalr instruction
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@ -257,7 +256,7 @@ module controller(
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bmuctrl bmuctrl(.clk, .reset, .StallD, .FlushD, .InstrD, .ALUOpD, .BSelectD, .ZBBSelectD,
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.BRegWriteD, .BALUSrcBD, .BW64D, .BSubArithD, .IllegalBitmanipInstrD, .StallE, .FlushE,
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.ALUSelectD, .BSelectE, .ZBBSelectE, .BRegWriteE, .BComparatorSignedE, .BALUControlE);
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.ALUSelectD, .BSelectE, .ZBBSelectE, .BRegWriteE, .BALUControlE);
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if (`ZBA_SUPPORTED) begin
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// ALU Decoding is more comprehensive when ZBA is supported. slt and slti conflicts with sh1add, sh1add.uw
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assign sltD = (Funct3D == 3'b010 & (~(Funct7D[4]) | ~OpD[5])) ;
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@ -285,7 +284,6 @@ module controller(
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assign BSelectE = 2'b00;
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assign BSelectD = 2'b00;
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assign ZBBSelectE = 3'b000;
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assign BComparatorSignedE = 1'b0;
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assign BALUControlE = 3'b0;
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end
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@ -313,8 +311,7 @@ module controller(
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// Branch Logic
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// The comparator handles both signed and unsigned branches using BranchSignedE
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// Hence, only eq and lt flags are needed
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// We also want comparator to handle signed comparison on a max/min bitmanip instruction
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assign BranchSignedE = (~(Funct3E[2:1] == 2'b11) & BranchE) | BComparatorSignedE;
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assign BranchSignedE = (~(Funct3E[2:1] == 2'b11) & BranchE);
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assign {eqE, ltE} = FlagsE;
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mux2 #(1) branchflagmux(eqE, ltE, Funct3E[2], BranchFlagE);
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assign BranchTakenE = BranchFlagE ^ Funct3E[0];
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@ -114,7 +114,7 @@ module datapath (
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comparator #(`XLEN) comp(ForwardedSrcAE, ForwardedSrcBE, BranchSignedE, FlagsE);
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mux2 #(`XLEN) srcamux(ForwardedSrcAE, PCE, ALUSrcAE, SrcAE);
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mux2 #(`XLEN) srcbmux(ForwardedSrcBE, ImmExtE, ALUSrcBE, SrcBE);
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alu #(`XLEN) alu(SrcAE, SrcBE, W64E, SubArithE, ALUSelectE, BSelectE, ZBBSelectE, Funct3E, FlagsE[0], BALUControlE, ALUResultE, IEUAdrE);
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alu #(`XLEN) alu(SrcAE, SrcBE, W64E, SubArithE, ALUSelectE, BSelectE, ZBBSelectE, Funct3E, BALUControlE, ALUResultE, IEUAdrE);
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mux2 #(`XLEN) altresultmux(ImmExtE, PCLinkE, JumpE, AltResultE);
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mux2 #(`XLEN) ieuresultmux(ALUResultE, AltResultE, ALUResultSrcE, IEUResultE);
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@ -1,7 +1,8 @@
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///////////////////////////////////////////
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<///////////////////////////////////////////
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//
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// Written: me@KatherineParry.com
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// Modified: 7/5/2022
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// Modified: 4/2/2023
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//
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// Purpose: Testbench for Testfloat
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//
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@ -32,75 +33,74 @@
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module testbenchfp;
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parameter TEST="none";
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string Tests[]; // list of tests to be run
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logic [2:0] OpCtrl[]; // list of op controls
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logic [2:0] Unit[]; // list of units being tested
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logic WriteInt[]; // Is being written to integer resgiter
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logic [2:0] Frm[4:0] = {3'b100, 3'b010, 3'b011, 3'b001, 3'b000}; // rounding modes: rne-000, rz-001, ru-011, rd-010, rnm-100
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logic [1:0] Fmt[]; // list of formats for the other units
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string Tests[]; // list of tests to be run
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logic [2:0] OpCtrl[]; // list of op controls
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logic [2:0] Unit[]; // list of units being tested
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logic WriteInt[]; // Is being written to integer resgiter
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logic [2:0] Frm[4:0] = {3'b100, 3'b010, 3'b011, 3'b001, 3'b000}; // rounding modes: rne-000, rz-001, ru-011, rd-010, rnm-100
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logic [1:0] Fmt[]; // list of formats for the other units
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logic clk=0;
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logic [31:0] TestNum=0; // index for the test
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logic [31:0] OpCtrlNum=0; // index for OpCtrl
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logic [31:0] errors=0; // how many errors
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logic [31:0] VectorNum=0; // index for test vector
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logic [31:0] FrmNum=0; // index for rounding mode
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logic [`FLEN*4+7:0] TestVectors[8388609:0]; // list of test vectors
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logic clk=0;
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logic [31:0] TestNum=0; // index for the test
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logic [31:0] OpCtrlNum=0; // index for OpCtrl
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logic [31:0] errors=0; // how many errors
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logic [31:0] VectorNum=0; // index for test vector
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logic [31:0] FrmNum=0; // index for rounding mode
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logic [`FLEN*4+7:0] TestVectors[8388609:0]; // list of test vectors
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logic [1:0] FmtVal; // value of the current Fmt
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logic [2:0] UnitVal, OpCtrlVal, FrmVal; // value of the currnet Unit/OpCtrl/FrmVal
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logic WriteIntVal; // value of the current WriteInt
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logic [`FLEN-1:0] X, Y, Z; // inputs read from TestFloat
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logic [`XLEN-1:0] SrcA; // integer input
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logic [`FLEN-1:0] Ans; // correct answer from TestFloat
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logic [`FLEN-1:0] Res; // result from other units
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logic [4:0] AnsFlg; // correct flags read from testfloat
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logic [4:0] ResFlg, Flg; // Result flags
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logic [`FMTBITS-1:0] ModFmt; // format - 10 = half, 00 = single, 01 = double, 11 = quad
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logic [`FLEN-1:0] FpRes, FpCmpRes; // Results from each unit
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logic [`XLEN-1:0] IntRes, CmpRes; // Results from each unit
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logic [4:0] FmaFlg, CvtFlg, DivFlg, CmpFlg; // Outputed flags
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logic AnsNaN, ResNaN, NaNGood;
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||||
logic Xs, Ys, Zs; // sign of the inputs
|
||||
logic [`NE-1:0] Xe, Ye, Ze; // exponent of the inputs
|
||||
logic [`NF:0] Xm, Ym, Zm; // mantissas of the inputs
|
||||
logic XNaN, YNaN, ZNaN; // is the input NaN
|
||||
logic XSNaN, YSNaN, ZSNaN; // is the input a signaling NaN
|
||||
logic XSubnorm, ZSubnorm; // is the input denormalized
|
||||
logic XInf, YInf, ZInf; // is the input infinity
|
||||
logic XZero, YZero, ZZero; // is the input zero
|
||||
logic XExpMax, YExpMax, ZExpMax; // is the input's exponent all ones
|
||||
logic [`CVTLEN-1:0] CvtLzcInE; // input to the Leading Zero Counter (priority encoder)
|
||||
logic IntZero;
|
||||
logic CvtResSgnE;
|
||||
logic [`NE:0] CvtCalcExpE; // the calculated expoent
|
||||
logic [`LOGCVTLEN-1:0] CvtShiftAmtE; // how much to shift by
|
||||
logic [`DIVb:0] Quot;
|
||||
logic CvtResSubnormUfE;
|
||||
logic DivStart, FDivBusyE, OldFDivBusyE;
|
||||
logic reset = 1'b0;
|
||||
logic [$clog2(`NF+2)-1:0] XZeroCnt, YZeroCnt;
|
||||
logic [`DURLEN-1:0] Dur;
|
||||
logic [1:0] FmtVal; // value of the current Fmt
|
||||
logic [2:0] UnitVal, OpCtrlVal, FrmVal; // value of the currnet Unit/OpCtrl/FrmVal
|
||||
logic WriteIntVal; // value of the current WriteInt
|
||||
logic [`FLEN-1:0] X, Y, Z; // inputs read from TestFloat
|
||||
logic [`XLEN-1:0] SrcA; // integer input
|
||||
logic [`FLEN-1:0] Ans; // correct answer from TestFloat
|
||||
logic [`FLEN-1:0] Res; // result from other units
|
||||
logic [4:0] AnsFlg; // correct flags read from testfloat
|
||||
logic [4:0] ResFlg, Flg; // Result flags
|
||||
logic [`FMTBITS-1:0] ModFmt; // format - 10 = half, 00 = single, 01 = double, 11 = quad
|
||||
logic [`FLEN-1:0] FpRes, FpCmpRes; // Results from each unit
|
||||
logic [`XLEN-1:0] IntRes, CmpRes; // Results from each unit
|
||||
logic [4:0] FmaFlg, CvtFlg, DivFlg, CmpFlg; // Outputed flags
|
||||
logic AnsNaN, ResNaN, NaNGood;
|
||||
logic Xs, Ys, Zs; // sign of the inputs
|
||||
logic [`NE-1:0] Xe, Ye, Ze; // exponent of the inputs
|
||||
logic [`NF:0] Xm, Ym, Zm; // mantissas of the inputs
|
||||
logic XNaN, YNaN, ZNaN; // is the input NaN
|
||||
logic XSNaN, YSNaN, ZSNaN; // is the input a signaling NaN
|
||||
logic XSubnorm, ZSubnorm; // is the input denormalized
|
||||
logic XInf, YInf, ZInf; // is the input infinity
|
||||
logic XZero, YZero, ZZero; // is the input zero
|
||||
logic XExpMax, YExpMax, ZExpMax; // is the input's exponent all ones
|
||||
logic [`CVTLEN-1:0] CvtLzcInE; // input to the Leading Zero Counter (priority encoder)
|
||||
logic IntZero;
|
||||
logic CvtResSgnE;
|
||||
logic [`NE:0] CvtCalcExpE; // the calculated expoent
|
||||
logic [`LOGCVTLEN-1:0] CvtShiftAmtE; // how much to shift by
|
||||
logic [`DIVb:0] Quot;
|
||||
logic CvtResSubnormUfE;
|
||||
logic DivStart, FDivBusyE, OldFDivBusyE;
|
||||
logic reset = 1'b0;
|
||||
logic [$clog2(`NF+2)-1:0] XZeroCnt, YZeroCnt;
|
||||
logic [`DURLEN-1:0] Dur;
|
||||
|
||||
// in-between FMA signals
|
||||
logic Mult;
|
||||
logic Ss;
|
||||
logic [`NE+1:0] Pe;
|
||||
logic [`NE+1:0] Se;
|
||||
logic ASticky;
|
||||
logic KillProd;
|
||||
logic [$clog2(3*`NF+5)-1:0] SCnt;
|
||||
logic [3*`NF+3:0] Sm;
|
||||
logic InvA;
|
||||
logic NegSum;
|
||||
logic As;
|
||||
logic Ps;
|
||||
logic DivSticky;
|
||||
logic DivDone;
|
||||
logic DivNegSticky;
|
||||
logic [`NE+1:0] DivCalcExp;
|
||||
logic divsqrtop;
|
||||
logic Mult;
|
||||
logic Ss;
|
||||
logic [`NE+1:0] Pe;
|
||||
logic [`NE+1:0] Se;
|
||||
logic ASticky;
|
||||
logic KillProd;
|
||||
logic [$clog2(3*`NF+5)-1:0] SCnt;
|
||||
logic [3*`NF+3:0] Sm;
|
||||
logic InvA;
|
||||
logic NegSum;
|
||||
logic As;
|
||||
logic Ps;
|
||||
logic DivSticky;
|
||||
logic DivDone;
|
||||
logic DivNegSticky;
|
||||
logic [`NE+1:0] DivCalcExp;
|
||||
logic divsqrtop;
|
||||
|
||||
|
||||
///////////////////////////////////////////////////////////////////////////////////////////////
|
||||
@ -126,28 +126,28 @@ module testbenchfp;
|
||||
$display("TEST is %s", TEST);
|
||||
if (`Q_SUPPORTED) begin // if Quad percision is supported
|
||||
if (TEST === "cvtint"| TEST === "all") begin // if testing integer conversion
|
||||
// add the 128-bit cvtint tests to the to-be-tested list
|
||||
Tests = {Tests, f128rv32cvtint};
|
||||
// add the op-codes for these tests to the op-code list
|
||||
OpCtrl = {OpCtrl, `FROM_UI_OPCTRL, `FROM_I_OPCTRL, `TO_UI_OPCTRL, `TO_I_OPCTRL};
|
||||
WriteInt = {WriteInt, 1'b0, 1'b0, 1'b1, 1'b1};
|
||||
// add what unit is used and the fmt to their lists (one for each test)
|
||||
for(int i = 0; i<20; i++) begin
|
||||
Unit = {Unit, `CVTINTUNIT};
|
||||
Fmt = {Fmt, 2'b11};
|
||||
end
|
||||
if (`XLEN == 64) begin // if 64-bit integers are supported add their conversions
|
||||
Tests = {Tests, f128rv64cvtint};
|
||||
// add the op-codes for these tests to the op-code list
|
||||
OpCtrl = {OpCtrl, `FROM_UL_OPCTRL, `FROM_L_OPCTRL, `TO_UL_OPCTRL, `TO_L_OPCTRL};
|
||||
WriteInt = {WriteInt, 1'b0, 1'b0, 1'b1, 1'b1};
|
||||
// add what unit is used and the fmt to their lists (one for each test)
|
||||
for(int i = 0; i<20; i++) begin
|
||||
Unit = {Unit, `CVTINTUNIT};
|
||||
Fmt = {Fmt, 2'b11};
|
||||
end
|
||||
end
|
||||
end
|
||||
// add the 128-bit cvtint tests to the to-be-tested list
|
||||
Tests = {Tests, f128rv32cvtint};
|
||||
// add the op-codes for these tests to the op-code list
|
||||
OpCtrl = {OpCtrl, `FROM_UI_OPCTRL, `FROM_I_OPCTRL, `TO_UI_OPCTRL, `TO_I_OPCTRL};
|
||||
WriteInt = {WriteInt, 1'b0, 1'b0, 1'b1, 1'b1};
|
||||
// add what unit is used and the fmt to their lists (one for each test)
|
||||
for(int i = 0; i<20; i++) begin
|
||||
Unit = {Unit, `CVTINTUNIT};
|
||||
Fmt = {Fmt, 2'b11};
|
||||
end
|
||||
if (`XLEN == 64) begin // if 64-bit integers are supported add their conversions
|
||||
Tests = {Tests, f128rv64cvtint};
|
||||
// add the op-codes for these tests to the op-code list
|
||||
OpCtrl = {OpCtrl, `FROM_UL_OPCTRL, `FROM_L_OPCTRL, `TO_UL_OPCTRL, `TO_L_OPCTRL};
|
||||
WriteInt = {WriteInt, 1'b0, 1'b0, 1'b1, 1'b1};
|
||||
// add what unit is used and the fmt to their lists (one for each test)
|
||||
for(int i = 0; i<20; i++) begin
|
||||
Unit = {Unit, `CVTINTUNIT};
|
||||
Fmt = {Fmt, 2'b11};
|
||||
end
|
||||
end
|
||||
end
|
||||
if (TEST === "cvtfp" | TEST === "all") begin // if the floating-point conversions are being tested
|
||||
if(`D_SUPPORTED) begin // if double precision is supported
|
||||
// add the 128 <-> 64 bit conversions to the to-be-tested list
|
||||
@ -270,27 +270,27 @@ module testbenchfp;
|
||||
end
|
||||
if (`D_SUPPORTED) begin // if double precision is supported
|
||||
if (TEST === "cvtint"| TEST === "all") begin // if integer conversion is being tested
|
||||
Tests = {Tests, f64rv32cvtint};
|
||||
// add the op-codes for these tests to the op-code list
|
||||
OpCtrl = {OpCtrl, `FROM_UI_OPCTRL, `FROM_I_OPCTRL, `TO_UI_OPCTRL, `TO_I_OPCTRL};
|
||||
WriteInt = {WriteInt, 1'b0, 1'b0, 1'b1, 1'b1};
|
||||
// add what unit is used and the fmt to their lists (one for each test)
|
||||
for(int i = 0; i<20; i++) begin
|
||||
Unit = {Unit, `CVTINTUNIT};
|
||||
Fmt = {Fmt, 2'b01};
|
||||
end
|
||||
if (`XLEN == 64) begin // if 64-bit integers are being supported
|
||||
Tests = {Tests, f64rv64cvtint};
|
||||
// add the op-codes for these tests to the op-code list
|
||||
OpCtrl = {OpCtrl, `FROM_UL_OPCTRL, `FROM_L_OPCTRL, `TO_UL_OPCTRL, `TO_L_OPCTRL};
|
||||
WriteInt = {WriteInt, 1'b0, 1'b0, 1'b1, 1'b1};
|
||||
// add what unit is used and the fmt to their lists (one for each test)
|
||||
for(int i = 0; i<20; i++) begin
|
||||
Unit = {Unit, `CVTINTUNIT};
|
||||
Fmt = {Fmt, 2'b01};
|
||||
end
|
||||
end
|
||||
end
|
||||
Tests = {Tests, f64rv32cvtint};
|
||||
// add the op-codes for these tests to the op-code list
|
||||
OpCtrl = {OpCtrl, `FROM_UI_OPCTRL, `FROM_I_OPCTRL, `TO_UI_OPCTRL, `TO_I_OPCTRL};
|
||||
WriteInt = {WriteInt, 1'b0, 1'b0, 1'b1, 1'b1};
|
||||
// add what unit is used and the fmt to their lists (one for each test)
|
||||
for(int i = 0; i<20; i++) begin
|
||||
Unit = {Unit, `CVTINTUNIT};
|
||||
Fmt = {Fmt, 2'b01};
|
||||
end
|
||||
if (`XLEN == 64) begin // if 64-bit integers are being supported
|
||||
Tests = {Tests, f64rv64cvtint};
|
||||
// add the op-codes for these tests to the op-code list
|
||||
OpCtrl = {OpCtrl, `FROM_UL_OPCTRL, `FROM_L_OPCTRL, `TO_UL_OPCTRL, `TO_L_OPCTRL};
|
||||
WriteInt = {WriteInt, 1'b0, 1'b0, 1'b1, 1'b1};
|
||||
// add what unit is used and the fmt to their lists (one for each test)
|
||||
for(int i = 0; i<20; i++) begin
|
||||
Unit = {Unit, `CVTINTUNIT};
|
||||
Fmt = {Fmt, 2'b01};
|
||||
end
|
||||
end
|
||||
end
|
||||
if (TEST === "cvtfp" | TEST === "all") begin // if floating point conversions are being tested
|
||||
if(`F_SUPPORTED) begin // if single precision is supported
|
||||
// add the 64 <-> 32 bit conversions to the to-be-tested list
|
||||
@ -397,27 +397,27 @@ module testbenchfp;
|
||||
end
|
||||
if (`F_SUPPORTED) begin // if single precision being supported
|
||||
if (TEST === "cvtint"| TEST === "all") begin // if integer conversion is being tested
|
||||
Tests = {Tests, f32rv32cvtint};
|
||||
// add the op-codes for these tests to the op-code list
|
||||
OpCtrl = {OpCtrl, `FROM_UI_OPCTRL, `FROM_I_OPCTRL, `TO_UI_OPCTRL, `TO_I_OPCTRL};
|
||||
WriteInt = {WriteInt, 1'b0, 1'b0, 1'b1, 1'b1};
|
||||
// add what unit is used and the fmt to their lists (one for each test)
|
||||
for(int i = 0; i<20; i++) begin
|
||||
Unit = {Unit, `CVTINTUNIT};
|
||||
Fmt = {Fmt, 2'b00};
|
||||
end
|
||||
if (`XLEN == 64) begin // if 64-bit integers are supported
|
||||
Tests = {Tests, f32rv64cvtint};
|
||||
// add the op-codes for these tests to the op-code list
|
||||
OpCtrl = {OpCtrl, `FROM_UL_OPCTRL, `FROM_L_OPCTRL, `TO_UL_OPCTRL, `TO_L_OPCTRL};
|
||||
WriteInt = {WriteInt, 1'b0, 1'b0, 1'b1, 1'b1};
|
||||
// add what unit is used and the fmt to their lists (one for each test)
|
||||
for(int i = 0; i<20; i++) begin
|
||||
Unit = {Unit, `CVTINTUNIT};
|
||||
Fmt = {Fmt, 2'b00};
|
||||
end
|
||||
end
|
||||
end
|
||||
Tests = {Tests, f32rv32cvtint};
|
||||
// add the op-codes for these tests to the op-code list
|
||||
OpCtrl = {OpCtrl, `FROM_UI_OPCTRL, `FROM_I_OPCTRL, `TO_UI_OPCTRL, `TO_I_OPCTRL};
|
||||
WriteInt = {WriteInt, 1'b0, 1'b0, 1'b1, 1'b1};
|
||||
// add what unit is used and the fmt to their lists (one for each test)
|
||||
for(int i = 0; i<20; i++) begin
|
||||
Unit = {Unit, `CVTINTUNIT};
|
||||
Fmt = {Fmt, 2'b00};
|
||||
end
|
||||
if (`XLEN == 64) begin // if 64-bit integers are supported
|
||||
Tests = {Tests, f32rv64cvtint};
|
||||
// add the op-codes for these tests to the op-code list
|
||||
OpCtrl = {OpCtrl, `FROM_UL_OPCTRL, `FROM_L_OPCTRL, `TO_UL_OPCTRL, `TO_L_OPCTRL};
|
||||
WriteInt = {WriteInt, 1'b0, 1'b0, 1'b1, 1'b1};
|
||||
// add what unit is used and the fmt to their lists (one for each test)
|
||||
for(int i = 0; i<20; i++) begin
|
||||
Unit = {Unit, `CVTINTUNIT};
|
||||
Fmt = {Fmt, 2'b00};
|
||||
end
|
||||
end
|
||||
end
|
||||
if (TEST === "cvtfp" | TEST === "all") begin // if floating point conversion is being tested
|
||||
if(`ZFH_SUPPORTED) begin
|
||||
// add the 32 <-> 16 bit conversions to the to-be-tested list
|
||||
@ -508,27 +508,27 @@ module testbenchfp;
|
||||
end
|
||||
if (`ZFH_SUPPORTED) begin // if half precision supported
|
||||
if (TEST === "cvtint"| TEST === "all") begin // if in conversions are being tested
|
||||
Tests = {Tests, f16rv32cvtint};
|
||||
// add the op-codes for these tests to the op-code list
|
||||
OpCtrl = {OpCtrl, `FROM_UI_OPCTRL, `FROM_I_OPCTRL, `TO_UI_OPCTRL, `TO_I_OPCTRL};
|
||||
WriteInt = {WriteInt, 1'b0, 1'b0, 1'b1, 1'b1};
|
||||
// add what unit is used and the fmt to their lists (one for each test)
|
||||
for(int i = 0; i<20; i++) begin
|
||||
Unit = {Unit, `CVTINTUNIT};
|
||||
Fmt = {Fmt, 2'b10};
|
||||
end
|
||||
if (`XLEN == 64) begin // if 64-bit integers are supported
|
||||
Tests = {Tests, f16rv64cvtint};
|
||||
// add the op-codes for these tests to the op-code list
|
||||
OpCtrl = {OpCtrl, `FROM_UL_OPCTRL, `FROM_L_OPCTRL, `TO_UL_OPCTRL, `TO_L_OPCTRL};
|
||||
WriteInt = {WriteInt, 1'b0, 1'b0, 1'b1, 1'b1};
|
||||
// add what unit is used and the fmt to their lists (one for each test)
|
||||
for(int i = 0; i<20; i++) begin
|
||||
Unit = {Unit, `CVTINTUNIT};
|
||||
Fmt = {Fmt, 2'b10};
|
||||
end
|
||||
end
|
||||
end
|
||||
Tests = {Tests, f16rv32cvtint};
|
||||
// add the op-codes for these tests to the op-code list
|
||||
OpCtrl = {OpCtrl, `FROM_UI_OPCTRL, `FROM_I_OPCTRL, `TO_UI_OPCTRL, `TO_I_OPCTRL};
|
||||
WriteInt = {WriteInt, 1'b0, 1'b0, 1'b1, 1'b1};
|
||||
// add what unit is used and the fmt to their lists (one for each test)
|
||||
for(int i = 0; i<20; i++) begin
|
||||
Unit = {Unit, `CVTINTUNIT};
|
||||
Fmt = {Fmt, 2'b10};
|
||||
end
|
||||
if (`XLEN == 64) begin // if 64-bit integers are supported
|
||||
Tests = {Tests, f16rv64cvtint};
|
||||
// add the op-codes for these tests to the op-code list
|
||||
OpCtrl = {OpCtrl, `FROM_UL_OPCTRL, `FROM_L_OPCTRL, `TO_UL_OPCTRL, `TO_L_OPCTRL};
|
||||
WriteInt = {WriteInt, 1'b0, 1'b0, 1'b1, 1'b1};
|
||||
// add what unit is used and the fmt to their lists (one for each test)
|
||||
for(int i = 0; i<20; i++) begin
|
||||
Unit = {Unit, `CVTINTUNIT};
|
||||
Fmt = {Fmt, 2'b10};
|
||||
end
|
||||
end
|
||||
end
|
||||
if (TEST === "cmp" | TEST === "all") begin // if comparisions are being tested
|
||||
// add the correct tests/op-ctrls/unit/fmt to their lists
|
||||
Tests = {Tests, f16cmp};
|
||||
@ -656,7 +656,8 @@ module testbenchfp;
|
||||
end
|
||||
|
||||
// extract the inputs (X, Y, Z, SrcA) and the output (Ans, AnsFlg) from the current test vector
|
||||
readvectors readvectors (.clk, .Fmt(FmtVal), .ModFmt, .TestVector(TestVectors[VectorNum]), .VectorNum, .Ans(Ans), .AnsFlg(AnsFlg), .SrcA,
|
||||
readvectors readvectors (.clk, .Fmt(FmtVal), .ModFmt, .TestVector(TestVectors[VectorNum]),
|
||||
.VectorNum, .Ans(Ans), .AnsFlg(AnsFlg), .SrcA,
|
||||
.Xs, .Ys, .Zs, .Unit(UnitVal),
|
||||
.Xe, .Ye, .Ze, .TestNum, .OpCtrl(OpCtrlVal),
|
||||
.Xm, .Ym, .Zm, .DivStart,
|
||||
@ -680,7 +681,7 @@ module testbenchfp;
|
||||
///////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// instantiate devices under test
|
||||
if (TEST === "fma"| TEST === "mul" | TEST === "add" | TEST === "all") begin : fma
|
||||
if (TEST === "fma"| TEST === "mul" | TEST === "add" | TEST === "sub" | TEST === "all") begin : fma
|
||||
fma fma(.Xs(Xs), .Ys(Ys), .Zs(Zs),
|
||||
.Xe(Xe), .Ye(Ye), .Ze(Ze),
|
||||
.Xm(Xm), .Ym(Ym), .Zm(Zm),
|
||||
@ -1331,4 +1332,4 @@ module readvectors (
|
||||
.Xm, .Ym, .Zm, .XNaN, .YNaN, .ZNaN, .XSNaN, .YSNaN, .ZSNaN,
|
||||
.XSubnorm, .XZero, .YZero, .ZZero, .XInf, .YInf, .ZInf,
|
||||
.XEn, .YEn, .ZEn, .XExpMax);
|
||||
endmodule
|
||||
endmodule
|
||||
|
||||
4
tests/fp/combined_IF_vectors/IF_vectors/README
Normal file
4
tests/fp/combined_IF_vectors/IF_vectors/README
Normal file
@ -0,0 +1,4 @@
|
||||
This folder holds the archtest and testfloat vectors necessary fo evaluating performance
|
||||
of standalone intdiv vs combined IFdivsqrt
|
||||
|
||||
to generate vectors, uncomment line 8 in create_all_vectors.sh
|
||||
8
tests/fp/combined_IF_vectors/create_IF_vectors.sh
Executable file
8
tests/fp/combined_IF_vectors/create_IF_vectors.sh
Executable file
@ -0,0 +1,8 @@
|
||||
#!/bin/sh
|
||||
# create test vectors for stand alone int
|
||||
|
||||
./extract_testfloat_vectors.py
|
||||
./extract_arch_vectors.py
|
||||
|
||||
# to create tvs for evaluation of combined IFdivsqrt
|
||||
#./combined_IF_vectors/create_IF_vectors.sh
|
||||
251
tests/fp/combined_IF_vectors/extract_arch_vectors.py
Executable file
251
tests/fp/combined_IF_vectors/extract_arch_vectors.py
Executable file
@ -0,0 +1,251 @@
|
||||
#! /usr/bin/python3
|
||||
|
||||
# author: Alessandro Maiuolo
|
||||
# contact: amaiuolo@g.hmc.edu
|
||||
# date created: 3-29-2023
|
||||
|
||||
# extract all arch test vectors
|
||||
import os
|
||||
wally = os.popen('echo $WALLY').read().strip()
|
||||
|
||||
def ext_bits(my_string):
|
||||
target_len = 32 # we want 128 bits, div by 4 bc hex notation
|
||||
zeroes_to_add = target_len - len(my_string)
|
||||
return zeroes_to_add*"0" + my_string
|
||||
|
||||
def twos_comp(b, x):
|
||||
if b == 32:
|
||||
return hex(0x100000000 - int(x,16))[2:]
|
||||
elif b == 64:
|
||||
return hex(0x10000000000000000 - int(x,16))[2:]
|
||||
else:
|
||||
return "UNEXPECTED_BITSIZE"
|
||||
|
||||
def unpack_rf(packed):
|
||||
bin_u = bin(int(packed, 16))[2:].zfill(8) # translate to binary
|
||||
flags = hex(int(bin_u[3:],2))[2:].zfill(2)
|
||||
rounding_mode = hex(int(bin_u[:3],2))[2:]
|
||||
return flags, rounding_mode
|
||||
|
||||
# rounding mode dictionary
|
||||
round_dict = {
|
||||
"rne":"0",
|
||||
"rnm":"4",
|
||||
"ru":"3",
|
||||
"rz":"1",
|
||||
"rd":"2",
|
||||
"dyn":"7"
|
||||
}
|
||||
|
||||
# fcsr dictionary
|
||||
fcsr_dict = {
|
||||
"0":"rne",
|
||||
"128":"rnm",
|
||||
"96":"ru",
|
||||
"32":"rz",
|
||||
"64":"rd",
|
||||
"224":"dyn"
|
||||
}
|
||||
|
||||
print("creating arch test vectors")
|
||||
|
||||
class Config:
|
||||
def __init__(self, bits, letter, op, filt, op_code):
|
||||
self.bits = bits
|
||||
self.letter = letter
|
||||
self.op = op
|
||||
self.filt = filt
|
||||
self.op_code = op_code
|
||||
|
||||
def create_vectors(my_config):
|
||||
suite_folder_num = my_config.bits
|
||||
if my_config.bits == 64 and my_config.letter == "F": suite_folder_num = 32
|
||||
source_dir1 = "{}/addins/riscv-arch-test/riscv-test-suite/rv{}i_m/{}/src/".format(wally, suite_folder_num, my_config.letter)
|
||||
source_dir2 = "{}/tests/riscof/work/riscv-arch-test/rv{}i_m/{}/src/".format(wally, my_config.bits, my_config.letter)
|
||||
dest_dir = "{}/tests/fp/combined_IF_vectors/IF_vectors/".format(wally)
|
||||
all_vectors1 = os.listdir(source_dir1)
|
||||
|
||||
filt_vectors1 = [v for v in all_vectors1 if my_config.filt in v]
|
||||
# print(filt_vectors1)
|
||||
filt_vectors2 = [v + "/ref/Reference-sail_c_simulator.signature" for v in all_vectors1 if my_config.filt in v]
|
||||
|
||||
# iterate through all vectors
|
||||
for i in range(len(filt_vectors1)):
|
||||
vector1 = filt_vectors1[i]
|
||||
vector2 = filt_vectors2[i]
|
||||
operation = my_config.op_code
|
||||
rounding_mode = "X"
|
||||
flags = "XX"
|
||||
# use name to create our new tv
|
||||
dest_file = open("{}cvw_{}_{}.tv".format(dest_dir, my_config.bits, vector1[:-2]), 'a')
|
||||
# open vectors
|
||||
src_file1 = open(source_dir1 + vector1,'r')
|
||||
src_file2 = open(source_dir2 + vector2,'r')
|
||||
# for each test in the vector
|
||||
reading = True
|
||||
src_file2.readline() #skip first bc junk
|
||||
# print(my_config.bits, my_config.letter)
|
||||
if my_config.letter == "F" and my_config.bits == 64:
|
||||
reading = True
|
||||
# print("trigger 64F")
|
||||
#skip first 2 lines bc junk
|
||||
src_file2.readline()
|
||||
while reading:
|
||||
# get answer and flags from Ref...signature
|
||||
# answers are before deadbeef (first line of 4)
|
||||
# flags are after deadbeef (third line of 4)
|
||||
answer = src_file2.readline().strip()
|
||||
deadbeef = src_file2.readline().strip()
|
||||
# print(answer)
|
||||
if not (answer == "e7d4b281" and deadbeef == "6f5ca309"): # if there is still stuff to read
|
||||
# get flags
|
||||
packed = src_file2.readline().strip()[6:]
|
||||
flags, rounding_mode = unpack_rf(packed)
|
||||
# skip 00000000 buffer
|
||||
src_file2.readline()
|
||||
|
||||
# parse through .S file
|
||||
detected = False
|
||||
done = False
|
||||
op1val = "0"
|
||||
op2val = "0"
|
||||
while not (detected or done):
|
||||
# print("det1")
|
||||
line = src_file1.readline()
|
||||
# print(line)
|
||||
if "op1val" in line:
|
||||
# print("det2")
|
||||
# parse line
|
||||
op1val = line.split("op1val")[1].split("x")[1].split(";")[0]
|
||||
if my_config.op != "fsqrt": # sqrt doesn't have two input vals
|
||||
op2val = line.split("op2val")[1].split("x")[1].strip()
|
||||
if op2val[-1] == ";": op2val = op2val[:-1] # remove ; if it's there
|
||||
else:
|
||||
op2val = 32*"X"
|
||||
# go to next test in vector
|
||||
detected = True
|
||||
elif "RVTEST_CODE_END" in line:
|
||||
done = True
|
||||
# put it all together
|
||||
if not done:
|
||||
translation = "{}_{}_{}_{}_{}_{}".format(operation, ext_bits(op1val), ext_bits(op2val), ext_bits(answer.strip()), flags, rounding_mode)
|
||||
dest_file.write(translation + "\n")
|
||||
else:
|
||||
# print("read false")
|
||||
reading = False
|
||||
elif my_config.letter == "M" and my_config.bits == 64:
|
||||
reading = True
|
||||
#skip first 2 lines bc junk
|
||||
src_file2.readline()
|
||||
while reading:
|
||||
# print("trigger 64M")
|
||||
# get answer from Ref...signature
|
||||
# answers span two lines and are reversed
|
||||
answer2 = src_file2.readline().strip()
|
||||
answer1 = src_file2.readline().strip()
|
||||
answer = answer1 + answer2
|
||||
# print(answer1,answer2)
|
||||
if not (answer2 == "e7d4b281" and answer1 == "6f5ca309"): # if there is still stuff to read
|
||||
# parse through .S file
|
||||
detected = False
|
||||
done = False
|
||||
op1val = "0"
|
||||
op2val = "0"
|
||||
while not (detected or done):
|
||||
# print("det1")
|
||||
line = src_file1.readline()
|
||||
# print(line)
|
||||
if "op1val" in line:
|
||||
# print("det2")
|
||||
# parse line
|
||||
op1val = line.split("op1val")[1].split("x")[1].split(";")[0]
|
||||
if "-" in line.split("op1val")[1].split("x")[0]: # neg sign handling
|
||||
op1val = twos_comp(my_config.bits, op1val)
|
||||
if my_config.op != "fsqrt": # sqrt doesn't have two input vals, unnec here but keeping for later
|
||||
op2val = line.split("op2val")[1].split("x")[1].strip()
|
||||
if op2val[-1] == ";": op2val = op2val[:-1] # remove ; if it's there
|
||||
if "-" in line.split("op2val")[1].split("x")[0]: # neg sign handling
|
||||
op2val = twos_comp(my_config.bits, op2val)
|
||||
# go to next test in vector
|
||||
detected = True
|
||||
elif "RVTEST_CODE_END" in line:
|
||||
done = True
|
||||
# ints don't have flags
|
||||
flags = "XX"
|
||||
# put it all together
|
||||
if not done:
|
||||
translation = "{}_{}_{}_{}_{}_{}".format(operation, ext_bits(op1val), ext_bits(op2val), ext_bits(answer.strip()), flags.strip(), rounding_mode)
|
||||
dest_file.write(translation + "\n")
|
||||
else:
|
||||
# print("read false")
|
||||
reading = False
|
||||
else:
|
||||
while reading:
|
||||
# get answer and flags from Ref...signature
|
||||
answer = src_file2.readline()
|
||||
# print(answer)
|
||||
packed = src_file2.readline()[6:]
|
||||
# print(packed)
|
||||
if len(packed.strip())>0: # if there is still stuff to read
|
||||
# print("packed")
|
||||
# parse through .S file
|
||||
detected = False
|
||||
done = False
|
||||
op1val = "0"
|
||||
op2val = "0"
|
||||
while not (detected or done):
|
||||
# print("det1")
|
||||
line = src_file1.readline()
|
||||
# print(line)
|
||||
if "op1val" in line:
|
||||
# print("det2")
|
||||
# parse line
|
||||
op1val = line.split("op1val")[1].split("x")[1].split(";")[0]
|
||||
if "-" in line.split("op1val")[1].split("x")[0]: # neg sign handling
|
||||
op1val = twos_comp(my_config.bits, op1val)
|
||||
if my_config.op != "fsqrt": # sqrt doesn't have two input vals
|
||||
op2val = line.split("op2val")[1].split("x")[1].strip()
|
||||
if op2val[-1] == ";": op2val = op2val[:-1] # remove ; if it's there
|
||||
if "-" in line.split("op2val")[1].split("x")[0]: # neg sign handling
|
||||
op2val = twos_comp(my_config.bits, op2val)
|
||||
# go to next test in vector
|
||||
detected = True
|
||||
elif "RVTEST_CODE_END" in line:
|
||||
done = True
|
||||
# rounding mode for float
|
||||
if not done and (my_config.op == "fsqrt" or my_config.op == "fdiv"):
|
||||
flags, rounding_mode = unpack_rf(packed)
|
||||
|
||||
# put it all together
|
||||
if not done:
|
||||
translation = "{}_{}_{}_{}_{}_{}".format(operation, ext_bits(op1val), ext_bits(op2val), ext_bits(answer.strip()), flags, rounding_mode)
|
||||
dest_file.write(translation + "\n")
|
||||
else:
|
||||
# print("read false")
|
||||
reading = False
|
||||
print("out")
|
||||
dest_file.close()
|
||||
src_file1.close()
|
||||
src_file2.close()
|
||||
|
||||
config_list = [
|
||||
Config(32, "M", "div", "div_", 0),
|
||||
Config(32, "F", "fdiv", "fdiv", 1),
|
||||
Config(32, "F", "fsqrt", "fsqrt", 2),
|
||||
Config(32, "M", "rem", "rem-", 3),
|
||||
Config(32, "M", "divu", "divu-", 4),
|
||||
Config(32, "M", "remu", "remu-", 5),
|
||||
Config(64, "M", "div", "div-", 0),
|
||||
Config(64, "F", "fdiv", "fdiv", 1),
|
||||
Config(64, "F", "fsqrt", "fsqrt", 2),
|
||||
Config(64, "M", "rem", "rem-", 3),
|
||||
Config(64, "M", "divu", "divu-", 4),
|
||||
Config(64, "M", "remu", "remu-", 5),
|
||||
Config(64, "M", "divw", "divw-", 6),
|
||||
Config(64, "M", "divuw", "divuw-", 7),
|
||||
Config(64, "M", "remw", "remw-", 8),
|
||||
Config(64, "M", "remuw", "remuw-", 9)
|
||||
]
|
||||
|
||||
for c in config_list:
|
||||
create_vectors(c)
|
||||
79
tests/fp/combined_IF_vectors/extract_testfloat_vectors.py
Executable file
79
tests/fp/combined_IF_vectors/extract_testfloat_vectors.py
Executable file
@ -0,0 +1,79 @@
|
||||
#! /usr/bin/python3
|
||||
# extract sqrt and float div testfloat vectors
|
||||
|
||||
# author: Alessandro Maiuolo
|
||||
# contact: amaiuolo@g.hmc.edu
|
||||
# date created: 3-29-2023
|
||||
|
||||
import os
|
||||
wally = os.popen('echo $WALLY').read().strip()
|
||||
# print(wally)
|
||||
|
||||
def ext_bits(my_string):
|
||||
target_len = 32 # we want 128 bits, div by 4 bc hex notation
|
||||
zeroes_to_add = target_len - len(my_string)
|
||||
return zeroes_to_add*"0" + my_string
|
||||
|
||||
# rounding mode dictionary
|
||||
round_dict = {
|
||||
"rne":"0",
|
||||
"rnm":"4",
|
||||
"ru":"3",
|
||||
"rz":"1",
|
||||
"rd":"2",
|
||||
"dyn":"7"
|
||||
}
|
||||
|
||||
|
||||
print("creating testfloat div test vectors")
|
||||
|
||||
source_dir = "{}/tests/fp/vectors/".format(wally)
|
||||
dest_dir = "{}/tests/fp/combined_IF_vectors/IF_vectors/".format(wally)
|
||||
all_vectors = os.listdir(source_dir)
|
||||
|
||||
div_vectors = [v for v in all_vectors if "div" in v]
|
||||
|
||||
# iterate through all float div vectors
|
||||
for vector in div_vectors:
|
||||
# use name to determine configs
|
||||
config_list = vector.split(".")[0].split("_")
|
||||
operation = "1" #float div
|
||||
rounding_mode = round_dict[str(config_list[2])]
|
||||
# use name to create our new tv
|
||||
dest_file = open(dest_dir + "cvw_" + vector, 'a')
|
||||
# open vector
|
||||
src_file = open(source_dir + vector,'r')
|
||||
# for each test in the vector
|
||||
for i in src_file.readlines():
|
||||
translation = "" # this stores the test that we are currently working on
|
||||
[input_1, input_2, answer, flags] = i.split("_") # separate inputs, answer, and flags
|
||||
# put it all together, strip nec for removing \n on the end of the flags
|
||||
translation = "{}_{}_{}_{}_{}_{}".format(operation, ext_bits(input_1), ext_bits(input_2), ext_bits(answer), flags.strip(), rounding_mode)
|
||||
dest_file.write(translation + "\n")
|
||||
dest_file.close()
|
||||
src_file.close()
|
||||
|
||||
|
||||
print("creating testfloat sqrt test vectors")
|
||||
|
||||
sqrt_vectors = [v for v in all_vectors if "sqrt" in v]
|
||||
|
||||
# iterate through all float div vectors
|
||||
for vector in sqrt_vectors:
|
||||
# use name to determine configs
|
||||
config_list = vector.split(".")[0].split("_")
|
||||
operation = "2" #sqrt
|
||||
rounding_mode = round_dict[str(config_list[2])]
|
||||
# use name to create our new tv
|
||||
dest_file = open(dest_dir + "cvw_" + vector, 'a')
|
||||
# open vector
|
||||
src_file = open(source_dir + vector,'r')
|
||||
# for each test in the vector
|
||||
for i in src_file.readlines():
|
||||
translation = "" # this stores the test that we are currently working on
|
||||
[input_1, answer, flags] = i.split("_") # separate inputs, answer, and flags
|
||||
# put it all together, strip nec for removing \n on the end of the flags
|
||||
translation = "{}_{}_{}_{}_{}_{}".format(operation, ext_bits(input_1), "X"*32, ext_bits(answer), flags.strip(), rounding_mode)
|
||||
dest_file.write(translation + "\n")
|
||||
dest_file.close()
|
||||
src_file.close()
|
||||
@ -3,3 +3,6 @@
|
||||
mkdir -p vectors
|
||||
./create_vectors.sh
|
||||
./remove_spaces.sh
|
||||
|
||||
# to create tvs for evaluation of combined IFdivsqrt
|
||||
#./combined_IF_vectors/create_IF_vectors.sh
|
||||
Loading…
Reference in New Issue
Block a user