Removed unused signals

pipelined/src/ifu/decompress.sv

@@ -52,7 +52,7 @@ module decompress (
   assign rs2p = {2'b01, instr16[4:2]};
   assign rdp = {2'b01, instr16[4:2]};
   
-  // many compressed immediate formats
+  // extract compressed immediate formats
   assign immCILSP = {4'b0000, instr16[3:2], instr16[12], instr16[6:4], 2'b00};
   assign immCILSPD = {3'b000, instr16[4:2], instr16[12], instr16[6:5], 3'b000};
   assign immCSS = {4'b0000, instr16[8:7], instr16[12:9], 2'b00}; 

pipelined/src/privileged/csr.sv

@@ -37,7 +37,7 @@ module csr #(parameter
     SIP = 12'h144
   ) (
   input  logic             clk, reset,
-  input  logic             FlushE, FlushM, FlushW,
+  input  logic             FlushM, FlushW,
   input  logic             StallE, StallM, StallW,
   input  logic [31:0]      InstrM, 
   input  logic [`XLEN-1:0] PCM, SrcAM, IEUAdrM, PCNext2F,
@@ -203,7 +203,7 @@ module csr #(parameter
               .CSRMWriteM, .CSRSWriteM, .CSRWriteValM, .CSRAdrM, 
               .MExtInt, .SExtInt, .MTimerInt, .MSwInt,
               .MIP_REGW, .MIE_REGW, .MIP_REGW_writeable);
-  csrsr csrsr(.clk, .reset, .StallW,
+  csrsr csrsr(.clk, .reset, .StallW, 
               .WriteMSTATUSM, .WriteMSTATUSHM, .WriteSSTATUSM, 
               .TrapM, .FRegWriteM, .NextPrivilegeModeM, .PrivilegeModeW,
               .mretM, .sretM, .WriteFRMM, .WriteFFLAGSM, .CSRWriteValM, .SelHPTW,
@@ -212,7 +212,7 @@ module csr #(parameter
               .STATUS_MIE, .STATUS_SIE, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_TVM,
               .STATUS_FS, .BigEndianM);
   csrc  counters(.clk, .reset,
-              .StallE, .StallM, .StallW, .FlushM,
+              .StallE, .StallM, .FlushM,
               .InstrValidNotFlushedM, .LoadStallD, .CSRMWriteM,
               .DirPredictionWrongM, .BTBPredPCWrongM, .RASPredPCWrongM, .PredictionInstrClassWrongM,
               .InstrClassM, .DCacheMiss, .DCacheAccess, .ICacheMiss, .ICacheAccess,

pipelined/src/privileged/csrc.sv

@@ -42,7 +42,7 @@ module csrc #(parameter
   TIMEH = 12'hC81
 ) (
     input logic 	     clk, reset,
-    input logic 	     StallE, StallM, StallW,
+    input logic 	     StallE, StallM, 
     input logic        FlushM, 
     input logic 	     InstrValidNotFlushedM, LoadStallD, CSRMWriteM,
     input logic 	     DirPredictionWrongM,

pipelined/src/privileged/privdec.sv

@@ -38,7 +38,6 @@ module privdec (
   input  logic         PrivilegedM, IllegalIEUInstrFaultM, IllegalCSRAccessM, IllegalFPUInstrM, 
   input  logic [1:0]   PrivilegeModeW, 
   input  logic         STATUS_TSR, STATUS_TVM, STATUS_TW,
-  input  logic [1:0]   STATUS_FS,
   output logic         IllegalInstrFaultM,
   output logic         EcallFaultM, BreakpointFaultM,
   output logic         sretM, mretM, wfiM, sfencevmaM);

pipelined/src/privileged/privileged.sv

@@ -113,7 +113,7 @@ module privileged (
 
    privdec pmd(.clk, .reset, .StallM, .InstrM(InstrM[31:20]), 
               .PrivilegedM, .IllegalIEUInstrFaultM, .IllegalCSRAccessM, .IllegalFPUInstrM, 
-              .PrivilegeModeW, .STATUS_TSR, .STATUS_TVM, .STATUS_TW, .STATUS_FS, .IllegalInstrFaultM, 
+              .PrivilegeModeW, .STATUS_TSR, .STATUS_TVM, .STATUS_TW, .IllegalInstrFaultM, 
               .EcallFaultM, .BreakpointFaultM,
               .sretM, .mretM, .wfiM, .sfencevmaM);
 
@@ -121,7 +121,7 @@ module privileged (
   // Control and Status Registers
   ///////////////////////////////////////////
   csr csr(.clk, .reset,
-          .FlushE, .FlushM, .FlushW,
+          .FlushM, .FlushW,
           .StallE, .StallM, .StallW,
           .InstrM, .PCM, .SrcAM, .IEUAdrM, .PCNext2F,
           .CSRReadM, .CSRWriteM, .TrapM, .mretM, .sretM, .wfiM, .IntPendingM, .InterruptM,

pipelined/src/uncore/uart_apb.sv

@@ -42,14 +42,6 @@ module uart_apb (
   input  logic             PENABLE,
   output logic [`XLEN-1:0] PRDATA,
   output logic             PREADY,
-/*
-  input  logic             HCLK, HRESETn, 
-  input  logic             HSELUART,
-  input  logic [2:0]       HADDR,
-  input  logic             HWRITE,
-  input  logic [`XLEN-1:0] PWDATA,
-  output logic [`XLEN-1:0] HREADUART,
-  output logic             HRESPUART, HREADYUART, */
   (* mark_debug = "true" *) input  logic             SIN, DSRb, DCDb, CTSb, RIb,    // from E1A driver from RS232 interface
   (* mark_debug = "true" *) output logic             SOUT, RTSb, DTRb, // to E1A driver to RS232 interface
   (* mark_debug = "true" *) output logic             OUT1b, OUT2b, INTR, TXRDYb, RXRDYb);         // to CPU