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Merged cacheable with seluncachedadr.

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This commit is contained in:
Ross Thompson 2022-10-17 12:34:14 -05:00
parent 6ab6467777
commit 2c80c2b35f
4 changed files with 13 additions and 16 deletions
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8
pipelined/src/ebu/ahbcacheinterface.sv
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@ -53,7 +53,7 @@ module ahbcacheinterface #(parameter WORDSPERLINE, LINELEN, LOGWPL, CACHE_ENABLE
input logic [1:0] CacheBusRW,
output logic CacheBusAck,
output logic [LINELEN-1:0] FetchBuffer,
output logic SelUncachedAdr,
input logic Cacheable,
// lsu/ifu interface
input logic [`PA_BITS-1:0] PAdr,
@ -77,13 +77,13 @@ module ahbcacheinterface #(parameter WORDSPERLINE, LINELEN, LOGWPL, CACHE_ENABLE
.q(FetchBuffer[(index+1)*`XLEN-1:index*`XLEN]));
end
mux2 #(`PA_BITS) localadrmux(CacheBusAdr, PAdr, SelUncachedAdr, LocalHADDR);
mux2 #(`PA_BITS) localadrmux(PAdr, CacheBusAdr, Cacheable, LocalHADDR);
assign HADDR = ({{`PA_BITS-LOGWPL{1'b0}}, WordCount} << $clog2(`XLEN/8)) + LocalHADDR;
mux2 #(3) sizemux(.d0(`XLEN == 32 ? 3'b010 : 3'b011), .d1(Funct3), .s(SelUncachedAdr), .y(HSIZE));
mux2 #(3) sizemux(.d0(Funct3), .d1(`XLEN == 32 ? 3'b010 : 3'b011), .s(Cacheable), .y(HSIZE));
buscachefsm #(WordCountThreshold, LOGWPL, CACHE_ENABLED) AHBBuscachefsm(
.HCLK, .HRESETn, .BusRW, .CPUBusy, .BusCommitted, .BusStall, .CaptureEn, .SelBusWord,
.CacheBusRW, .CacheBusAck, .SelUncachedAdr, .WordCount, .WordCountDelayed,
.CacheBusRW, .CacheBusAck, .WordCount, .WordCountDelayed,
.HREADY, .HTRANS, .HWRITE, .HBURST);
endmodule

4
pipelined/src/ebu/buscachefsm.sv
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@ -49,7 +49,6 @@ module buscachefsm #(parameter integer WordCountThreshold,
output logic CacheBusAck,
// lsu interface
output logic SelUncachedAdr,
output logic [LOGWPL-1:0] WordCount, WordCountDelayed,
output logic SelBusWord,
@ -134,9 +133,6 @@ module buscachefsm #(parameter integer WordCountThreshold,
(CurrState == CACHE_FETCH) |
(CurrState == CACHE_EVICT);
assign BusCommitted = CurrState != ADR_PHASE;
assign SelUncachedAdr = (CurrState == ADR_PHASE & |BusRW) |
(CurrState == DATA_PHASE) |
(CurrState == MEM3);
// AHB bus interface
assign HTRANS = (CurrState == ADR_PHASE & HREADY & (|BusRW | |CacheBusRW)) |

5
pipelined/src/ifu/ifu.sv
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@ -212,7 +212,6 @@ module ifu (
logic [LINELEN-1:0] FetchBuffer;
logic [`PA_BITS-1:0] ICacheBusAdr;
logic ICacheBusAck;
logic SelUncachedAdr;
logic [1:0] CacheBusRW, BusRW;
@ -241,14 +240,14 @@ module ifu (
.HRDATA,
.CacheBusRW, .HSIZE(IFUHSIZE), .HBURST(IFUHBURST), .HTRANS(IFUHTRANS),
.Funct3(3'b010), .HADDR(IFUHADDR), .HREADY(IFUHREADY), .HWRITE(IFUHWRITE), .CacheBusAdr(ICacheBusAdr),
.WordCount(), .SelUncachedAdr, .SelBusWord(),
.WordCount(), .Cacheable(CacheableF), .SelBusWord(),
.CacheBusAck(ICacheBusAck),
.FetchBuffer, .PAdr(PCPF),
.BusRW, .CPUBusy,
.BusStall, .BusCommitted(BusCommittedF));
mux3 #(32) UnCachedDataMux(.d0(ICacheInstrF), .d1(FetchBuffer[32-1:0]), .d2(IROMInstrF),
.s({SelIROM, SelUncachedAdr}), .y(InstrRawF[31:0]));
.s({SelIROM, ~CacheableF}), .y(InstrRawF[31:0]));
end else begin : passthrough
assign IFUHADDR = PCPF;
logic CaptureEn;

12
pipelined/src/lsu/lsu.sv
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@ -231,21 +231,23 @@ module lsu (
logic DCacheWriteLine;
logic DCacheFetchLine;
logic [AHBWLOGBWPL-1:0] WordCount;
logic SelUncachedAdr, DCacheBusAck;
logic DCacheBusAck;
logic SelBusWord;
logic [`XLEN-1:0] PreHWDATA; //*** change name
logic [`XLEN/8-1:0] ByteMaskMDelay;
logic [1:0] CacheBusRW, BusRW;
localparam integer LLENPOVERAHBW = `LLEN / `AHBW;
logic CacheableOrFlushCacheM;
assign BusRW = ~CacheableM & ~IgnoreRequest & ~SelDTIM ? LSURWM : '0;
assign CacheableOrFlushCacheM = CacheableM | FlushDCacheM;
cache #(.LINELEN(`DCACHE_LINELENINBITS), .NUMLINES(`DCACHE_WAYSIZEINBYTES*8/LINELEN),
.NUMWAYS(`DCACHE_NUMWAYS), .LOGBWPL(LLENLOGBWPL), .WORDLEN(`LLEN), .MUXINTERVAL(`LLEN), .DCACHE(1)) dcache(
.clk, .reset, .CPUBusy, .SelBusWord, .RW(LSURWM), .Atomic(LSUAtomicM),
.FlushCache(FlushDCacheM), .NextAdr(IEUAdrE[11:0]), .PAdr(PAdrM),
.ByteMask(ByteMaskM), .WordCount(WordCount[AHBWLOGBWPL-1:AHBWLOGBWPL-LLENLOGBWPL]),
.FinalWriteData(LSUWriteDataM), .Cacheable(CacheableM), .SelReplay,
.FinalWriteData(LSUWriteDataM), .Cacheable(CacheableOrFlushCacheM), .SelReplay,
.CacheStall(DCacheStallM), .CacheMiss(DCacheMiss), .CacheAccess(DCacheAccess),
.IgnoreRequestTLB, .TrapM, .CacheCommitted(DCacheCommittedM),
.CacheBusAdr(DCacheBusAdr), .ReadDataWord(DCacheReadDataWordM),
@ -258,14 +260,14 @@ module lsu (
.WordCount, .SelBusWord,
.Funct3(LSUFunct3M), .HADDR(LSUHADDR), .CacheBusAdr(DCacheBusAdr), .CacheBusRW,
.CacheBusAck(DCacheBusAck), .FetchBuffer, .PAdr(PAdrM),
.SelUncachedAdr, .BusRW, .CPUBusy,
.Cacheable(CacheableOrFlushCacheM), .BusRW, .CPUBusy,
.BusStall, .BusCommitted(BusCommittedM));
// FetchBuffer[`AHBW-1:0] needs to be duplicated LLENPOVERAHBW times.
// DTIMReadDataWordM should be increased to LLEN.
mux3 #(`LLEN) UnCachedDataMux(.d0(DCacheReadDataWordM), .d1({LLENPOVERAHBW{FetchBuffer[`XLEN-1:0]}}),
.d2({{`LLEN-`XLEN{1'b0}}, DTIMReadDataWordM[`XLEN-1:0]}),
.s({SelDTIM, SelUncachedAdr}), .y(ReadDataWordMuxM));
.s({SelDTIM, ~(CacheableOrFlushCacheM)}), .y(ReadDataWordMuxM));
// When AHBW is less than LLEN need extra muxes to select the subword from cache's read data.
logic [`AHBW-1:0] DCacheReadDataWordAHB;
@ -278,7 +280,7 @@ module lsu (
assign DCacheReadDataWordAHB = AHBWordSets[WordCount[$clog2(LLENPOVERAHBW)-1:0]];
end else assign DCacheReadDataWordAHB = DCacheReadDataWordM[`AHBW-1:0];
mux2 #(`XLEN) LSUHWDATAMux(.d0(DCacheReadDataWordAHB), .d1(LSUWriteDataM[`AHBW-1:0]),
.s(SelUncachedAdr), .y(PreHWDATA));
.s(~(CacheableOrFlushCacheM)), .y(PreHWDATA));
flopen #(`AHBW) wdreg(clk, LSUHREADY, PreHWDATA, LSUHWDATA); // delay HWDATA by 1 cycle per spec