forked from Github_Repos/cvw
expanded ifu coverage including 4 added directed tests and 1 exclusion, expanded fpu coverage including 6 directed tests and 2 multiline exclusions.
This commit is contained in:
Sydney Riley
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6c1f9de8c2
commit
440e41bb3e
@ -146,10 +146,13 @@ module fctrl (
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ControlsD = `FCTRLW'b1_0_01_00_000_0_0_0; // fcvt.s.(d/q/h)
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7'b0100001: if (Rs2D[4:2] == 3'b000 & SupportedFmt2 & Rs2D[1:0] != 2'b01)
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ControlsD = `FCTRLW'b1_0_01_00_001_0_0_0; // fcvt.d.(s/h/q)
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// coverage off
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// We are turning off coverage because rv64gc configuration doesn't support quad or half
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7'b0100010: if (Rs2D[4:2] == 3'b000 & SupportedFmt2 & Rs2D[1:0] != 2'b10)
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ControlsD = `FCTRLW'b1_0_01_00_010_0_0_0; // fcvt.h.(s/d/q)
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7'b0100011: if (Rs2D[4:2] == 3'b000 & SupportedFmt2 & Rs2D[1:0] != 2'b11)
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ControlsD = `FCTRLW'b1_0_01_00_011_0_0_0; // fcvt.q.(s/h/d)
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// coverage on
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7'b1101000: case(Rs2D)
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5'b00000: ControlsD = `FCTRLW'b1_0_01_00_101_0_0_0; // fcvt.s.w w->s
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5'b00001: ControlsD = `FCTRLW'b1_0_01_00_100_0_0_0; // fcvt.s.wu wu->s
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@ -174,6 +177,9 @@ module fctrl (
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5'b00010: ControlsD = `FCTRLW'b0_1_01_00_011_0_0_1; // fcvt.l.d d->l
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5'b00011: ControlsD = `FCTRLW'b0_1_01_00_010_0_0_1; // fcvt.lu.d d->lu
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endcase
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//coverage off
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// turning coverage off here because rv64gc configuration does not support floating point halfs and quads
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// verified that these branches will not ever be taken in rv64gc configuration.
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7'b1101010: case(Rs2D)
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5'b00000: ControlsD = `FCTRLW'b1_0_01_00_101_0_0_0; // fcvt.h.w w->h
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5'b00001: ControlsD = `FCTRLW'b1_0_01_00_100_0_0_0; // fcvt.h.wu wu->h
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@ -197,7 +203,8 @@ module fctrl (
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5'b00001: ControlsD = `FCTRLW'b0_1_01_00_000_0_0_1; // fcvt.wu.q q->wu
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5'b00010: ControlsD = `FCTRLW'b0_1_01_00_011_0_0_1; // fcvt.l.q q->l
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5'b00011: ControlsD = `FCTRLW'b0_1_01_00_010_0_0_1; // fcvt.lu.q q->lu
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endcase
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endcase
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// coverage on
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endcase
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endcase
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/* verilator lint_off CASEINCOMPLETE */
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@ -135,10 +135,16 @@ module decompress (
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IllegalCompInstrD = 1;
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InstrD = {16'b0, instr16}; // preserve instruction for mtval on trap
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end
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// coverage off
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// are excluding this branch from coverage because in rv64gc XLEN is always 64 and thus greater than 32 bits
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// This branch will only be taken if instr16[12:10] == 3'b111 and 'XLEN !> 32, because all other
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// possible values for instr16[12:10] are covered by branches above. XLEN !> 32
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// will never occur in rv64gc so this branch can not be covered
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else begin // illegal instruction
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IllegalCompInstrD = 1;
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InstrD = {16'b0, instr16}; // preserve instruction for mtval on trap
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end
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// coverage on
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5'b01101: InstrD = {immCJ, 5'b00000, 7'b1101111}; // c.j
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5'b01110: InstrD = {immCB[11:5], 5'b00000, rs1p, 3'b000, immCB[4:0], 7'b1100011}; // c.beqz
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5'b01111: InstrD = {immCB[11:5], 5'b00000, rs1p, 3'b001, immCB[4:0], 7'b1100011}; // c.bnez
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@ -55,7 +55,23 @@ main:
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fcvt.l.q a0, ft3
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fcvt.lu.q a0, ft3
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// Tests verfying that half and quad floating point convertion instructions are not supported by rv64gc
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# fcvt.h.d ft3, ft0 // Somehow this instruction is taking the route on line 124
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// idea: enable the Q extension for this to work properly? A: Q and halfs not supported in rv64gc
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# fcvt.h.w ft3, a0
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# fcvt.w.h a0, ft0
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# fcvt.q.w ft3, a0
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# fcvt.w.q a0, ft0
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# fcvt.q.d ft3, ft0
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.word 0x38007553 // Testing the all False case for 119 - funct7 under, op = 101 0011
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.word 0x40000053 // Line 145 All False Test case - illegal instruction?
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.word 0xd0400053 // Line 156 All False Test case - illegal instruction?
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.word 0xc0400053 // Line 162 All False Test case - illegal instruction?
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.word 0xd2400053 // Line 168 All False Test case - illegal instruction?
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.word 0xc2400053 // Line 174 All False Test case - illegal instruction?
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# Test illegal instructions are detected
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.word 0x00000007 // illegal floating-point load (bad Funct3)
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.word 0x00000027 // illegal floating-point store (bad Funct3)
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@ -32,9 +32,26 @@ main:
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csrs mstatus, t0
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# calling compressed floating point load double instruction
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//.halfword 0x2000 // CL type compressed floating-point ld-->funct3,imm,rs1',imm,rd',op
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//.hword 0x2000 // CL type compressed floating-point ld-->funct3,imm,rs1',imm,rd',op
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// binary version 0000 0000 0000 0000 0010 0000 0000 0000
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mv s0, sp
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c.fld fs0, 0(s0)
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c.fsd fs0, 0(s0)
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// c.fldsp fs0, 0
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.hword 0x2002
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// c.fsdsp fs0, 0
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.hword 0xA002
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# set XLEN to 64
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li t0, 0x200000000
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csrs mstatus, t0
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//# Illegal compressed instruction with op = 01, instr[15:10] = 100111, and 0's everywhere else
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//.hword 0x9C01
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# Illegal compressed instruction
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.hword 0x9C41
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j done
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