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Merge branch 'main' of https://github.com/openhwgroup/cvw

Browse Source 
This merges the branch predictor improvements into the main repo.
This commit is contained in:
Ross Thompson 2023-01-29 15:24:20 -06:00
commit a9a7054e2f
147 changed files with 1449 additions and 23206 deletions
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7
.gitignore vendored
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@ -76,7 +76,7 @@ synthDC/runs/
synthDC/newRuns
synthDC/ppa/PPAruns
synthDC/ppa/plots
synthDC/plots/
synthDC/wallyplots/
synthDC/runArchive
synthDC/hdl
/pipelined/regression/power.saif
@ -129,3 +129,8 @@ tests/custom/crt0/*.a
fpga/src/sdc/*
fpga/src/sdc.tar.gz
fpga/src/CopiedFiles_do_not_add_to_repo/*
/pipelined/regression/branch.log
/fpga/generator/sim/imp-funcsim.v
/fpga/generator/sim/imp-timesim.sdf
/fpga/generator/sim/imp-timesim.v
/fpga/generator/sim/syn-funcsim.v

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addins/docker/README.md
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@ -1,48 +0,0 @@
Installing Wally, RISC-V tools, and Imperas tests from source gives you maximum control, but has several disadvantages:
-Building the executables takes several hours.
-Linux is poorly standardized, and the build steps might not work on your version
-The source files are constantly changing, and the versions you download might not be compatible with this textbook flow.
Docker is a tools to run applications in a prepackaged container
including all of the operating system support required. Wally offers
a ~30GB container image with the open-source tools pre-installed from
Section D.1. In particular, using the container solves the long build
time for gcc and the fussy installation of sail. The container runs on
any platform supporting Docker, including Windows and Mac as well as
Linux. It can access files outside the container, including local
installation of CAD tools such as Questa, and a local clone of the
core-v-wally repository.
Docker can be run on most operating systems, including Linux, Windows,
and Mac. The Wally Docker container is hosted at DockerHub
(http://docker.io).
Podman is a more secure and easier-to-use variation of Docker for
Linux developed by RedHat. Both Docker and Podman run the same
containers.
This directory has a copy of the file utilized to create the Docker
for the toolchain discussed in the text. To build this docker, you can
type the following where the last argument is the name where you want
to store your docker.
docker build -t docker.io/wallysoc/wally-docker:latest .
This can also be changed if you make a mistake by using the tag
command. For example, if I wanted to change my docker from
wally-docker to wally-docker2, I would type:
docker tag wallysoc/wally-docker:latest docker.io/wallysoc/wally-docker2:latest
Once you build your docker, you can run it as given in the Readme.
However, you can also push it to DockerHub with the following command.
docker push docker.io/wallysoc/wally-docker:latest
To run your docker, you can type the following at a command prompt or
terminal.
docker run -it -p 8080:8080 docker.io/wallysoc/wally-docker

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addins/imperas-riscv-tests
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@ -1 +0,0 @@
/opt/riscv/imperas-riscv-tests/

246
bin/libppa.pl Executable file
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@ -0,0 +1,246 @@
#!/bin/perl -W
###########################################
## libppa.pl
##
## Written: David_Harris@hmc.edu
## Created: 28 January 2023
##
## Purpose: Extract PPA information from Liberty files
## presently characterizes Skywater 90 and TSMC28hpc+
##
## The user will need to change $libpath to point to the desired library in your local installation
## and for TSMC change the $cellname to the actual name of the inverter.
##
## A component of the CORE-V-WALLY configurable RISC-V project.
##
## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
##
## SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
##
## Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
## except in compliance with the License, or, at your option, the Apache License version 2.0. You
## may obtain a copy of the License at
##
## https:##solderpad.org/licenses/SHL-2.1/
##
## Unless required by applicable law or agreed to in writing, any work distributed under the
## License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
## either express or implied. See the License for the specific language governing permissions
## and limitations under the License.
################################################################################################
use strict;
use warnings;
# global variables for simplicity
my @index1; my @index2;
my @values;
my @cr; my @cf; my @rt; my @ft;
# cell and corners to analyze
my $libpath; my $libbase; my $cellname; my @corners;
# Sky90
$libpath ="/opt/riscv/cad/lib/sky90/sky90_sc/V1.7.4/lib";
$libbase = "scc9gena_";
$cellname = "scc9gena_inv_1";
@corners = ("tt_1.2v_25C", "tt_1.08v_25C", "tt_1.32v_25C", "tt_1.2v_-40C", "tt_1.2v_85C", "tt_1.2v_125C", "ss_1.2v_25C", "ss_1.08v_-40C", "ss_1.08v_25C", "ss_1.08v_125C", "ff_1.2v_25C", "ff_1.32v_-40C", "ff_1.32v_25C", "ff_1.32v_125C");
printf("Library $libbase Cell $cellname\n");
foreach my $corner (@corners) {
&analyzeCell($corner);
}
# TSMC
$libpath = "/proj/models/tsmc28/libraries/28nmtsmc/tcbn28hpcplusbwp30p140_190a/TSMCHOME/digital/Front_End/timing_power_noise/NLDM/tcbn28hpcplusbwp30p140_180a";
$libbase = "tcbn28hpcplusbwp30p140";
$cellname = "INVD1..."; // replace this with the full name of the library cell
@corners = ("tt0p9v25c", "tt0p8v25c", "tt1v25c", "tt0p9v85c", "ssg0p9vm40c", "ssg0p9v125c", "ssg0p81vm40c", "ssg0p81v125c", "ffg0p88vm40c", "ffg0p88v125c", "ffg0p99vm40c", "ffg0p99v125c");
printf("\nLibrary $libbase Cell $cellname\n");
foreach my $corner (@corners) {
&analyzeCell($corner);
}
#############
# subroutines
#############
sub analyzeCell {
my $corner = shift;
my $fname = $libpath."/".$libbase.$corner.".lib";
open (FILE, $fname) || die("Can't read $fname");
my $incell = 0;
my $inleakage = 0;
my $inpin = 0;
my $incellrise = 0;
my $incellfall = 0;
my $inrisetrans = 0;
my $infalltrans = 0;
my $inindex = 0;
my $invalues = 0;
my $searchstring = "cell (".$cellname.")";
my $area; my $leakage; my $cap;
while (<FILE>) {
if (index($_, $searchstring) != -1) { $incell = 1;}
elsif ($incell) {
if (/cell \(/) {
$incell = 0;
close(FILE);
last;
}
if (/area\s*:\s*(.*);/) { $area = $1; }
if (/cell_leakage_power\s*:\s*(.*);/) { $leakage = $1; $inleakage = 2; }
if ($inleakage == 0 && /leakage_power/) { $inleakage = 1; }
if ($inleakage == 1 && /value\s*:\s*(.*);/) {
$leakage = $1;
$inleakage = 2;
}
if ($inpin == 0 && /pin/) { $inpin = 1; }
if ($inpin == 1 && /\s+capacitance\s*:\s*(.*);/) {
$cap = $1;
$inpin = 2;
}
if ($inindex == 0 && /index_1/) { $inindex = 1; }
if ($inindex == 1) {
if (/index_1\s*\(\"(.*)\"\);/) { @index1 = split(/, /, $1); }
if (/index_2\s*\(\"(.*)\"\);/) { @index2 = split(/, /, $1); $inindex = 2; }
}
if ($incellrise == 0 && /cell_rise/) { $incellrise = 1; $invalues = 0;}
if ($incellfall == 0 && /cell_fall/) { $incellfall = 1; $invalues = 0; }
if ($inrisetrans == 0 && /rise_trans/) { $inrisetrans = 1; $invalues = 0; }
if ($infalltrans == 0 && /fall_trans/) { $infalltrans = 1; $invalues = 0; }
if ($incellrise == 1 || $incellfall == 1 || $inrisetrans == 1 || $infalltrans == 1) {
if (/values/) { $invalues = 1; @values = (); }
elsif ($invalues == 1) {
if (/\);/) {
$invalues = 2;
if ($incellrise == 1) { @cr = &parseVals(); $incellrise = 2; }
if ($incellfall == 1) { @cf = &parseVals(); $incellfall = 2; }
if ($inrisetrans == 1) { @rt = &parseVals(); $inrisetrans = 2; }
if ($infalltrans == 1) { @ft = &parseVals(); $infalltrans = 2; }
}
elsif (/\"(.*)\"/) { push(@values, $1); }
}
}
# print $_;
}
}
my $delay = &computeDelay($cap);
my $cornerr = sprintf("%20s", $corner);
my $delayr = sprintf("%2.1f", $delay*1000);
my $leakager = sprintf("%3.1f", $leakage);
print("$cornerr: Delay $delayr Leakage: $leakager capacitance: $cap\n");
#print("$cellname $corner: Area $area Leakage: $leakage capacitance: $cap delay $delay\n");
#print(" index1: @index1\n");
#print(" index2: @index2\n");
#print("Cell Rise\n"); printMatrix(\@cr);
#print("Cell Fall\n"); printMatrix(\@cf);
#print("Rise Trans\n"); printMatrix(\@rt);
#print("Fall Trans\n"); printMatrix(\@ft);
}
sub computeDelay {
# relies on cr, cf, rt, ft, index1, index2
# index1 for rows of matrix (different trans times, units of ns)
# index2 for cols of matrix (different load capacitances, units of pF)
# first, given true load, create a rise/fall delay and transition
# as a function of trans time, interpolated
my $cap = shift;
my $fo4cap = 4*$cap;
my @cri = &interp2(\@cr, $fo4cap);
my @cfi = &interp2(\@cf, $fo4cap);
my @rti = &interp2(\@rt, $fo4cap);
my @fti = &interp2(\@ft, $fo4cap);
# initially guess second smallest transition time
my $tt = $index1[1];
# assume falling input with this transition, compute rise delay & trans
my $cr0 = &interp1(\@cri, \@index1, $tt);
my $rt0 = &interp1(\@rti, \@index1, $tt);
# now assuming rising input with rt0, compute fall delay & trans
my $cf1 = &interp1(\@cfi, \@index1, $rt0);
my $ft1 = &interp1(\@fti, \@index1, $rt0);
# now assuming falling input with ft1, compute rise delay & trans
my $cr2 = &interp1(\@cri, \@index1, $ft1);
my $rt2 = &interp1(\@rti, \@index1, $ft1);
# now assuming rising input with rt2, compute fall delay & trans
my $cf3 = &interp1(\@cfi, \@index1, $rt2);
my $ft3 = &interp1(\@fti, \@index1, $rt2);
# delay is average of rising and falling
my $delay = ($cr2 + $cf3)/2;
return $delay;
# print("tt $tt cr0 $cr0 rt0 $rt0\n");
# print("cf1 $cf1 ft1 $ft1 cr2 $cr2 rt2 $rt2 cf3 $cf3 ft3 $ft3 delay $delay\n");
}
sub interp2 {
my $matref = shift;
my @matrix = @$matref;
my $fo4cap = shift;
my @interp = ();
my $i;
# interpolate row by row
for ($i=0; $i <= $#index1; $i++) {
my @row = @{$matrix[$i]};
#print ("Extracted row $i = @row\n");
$interp[$i] = &interp1(\@row, \@index2, $fo4cap);
}
return @interp;
}
sub interp1 {
my $vecref = shift;
my @vec = @$vecref;
my $indexref = shift;
my @index = @$indexref;
my $x = shift;
# find entry i containing the first index greater than x
my $i = 0;
while ($index[$i] < $x) {$i++}
my $start = $index[$i-1];
my $end = $index[$i];
my $fract = ($x-$start)/($end-$start);
my $interp = $vec[$i-1] + ($vec[$i] - $vec[$i-1])*$fract;
# print ("Interpolating $x as $interp from i $i start $start end $end based on index @index and vec @vec\n");
return $interp;
}
sub parseVals {
# relies on global variables @values, @index1, @index2
my @vals;
my $i; my $j;
for ($i=0; $i <= $#index1; $i++) {
my @row = split(/, /,$values[$i]);
for ($j = 0; $j <= $#index2; $j++) {
$vals[$i][$j] = $row[$j];
}
}
return @vals;
}
sub printMatrix {
my $mat = shift;
my @matrix = @$mat;
my $i; my $j;
for ($i=0; $i <= $#index1; $i++) {
for ($j = 0; $j <= $#index2; $j++) {
print($matrix[$i][$j]." ");
}
print("\n");
}
}

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@ -0,0 +1,206 @@
D Wally Toolchain Docker Container
Installing RISC-V tools from source gives you maximum control, but has several disadvantages:
* Building the executables takes several hours.
* Linux is poorly standardized, and the build steps might not work on your version
* The source files are constantly changing, and the versions you download might not be compatible with this textbook flow.
Docker is a tools to run applications in a prepackaged container including all of the operating system support required. Wally offers a ~30GB container image with the open-source tools pre-installed from Section D.1. In particular, using the container solves the long build time for gcc and the fussy installation of sail. The container runs on any platform supporting Docker, including Windows and Mac as well as Linux. It can access files outside the container, including local installation of CAD tools such as Questa, and a local clone of the core-v-wally repository.
Docker can be run on most operating systems, including Linux, Windows, and Mac. The Wally Docker container is hosted at DockerHub (http://docker.io).
Podman is a more secure and easier-to-use variation of Docker for Linux developed by RedHat. Both Docker and Podman run the same containers.
D.3.1 Podman Installation on Linux
A system administrator must install Podman if it is not already present.
For Ubuntu 20.10 or later:
$ sudo apt-get -y install podman
For RedHat / Rocky:
$ sudo yum -y install podman
D.3.2 Pulling the Wally Container
Once Podman is installed, a user can pull the Wally container image. The user must sign up for a free account at docker.io, and will be prompted for the credentials when running podman login.
$ podman login docker.io
$ podman pull docker.io/wallysoc/wally-docker:latest
D.3.3 Running the Docker Container in Podman
To activate podman with GUI support, first identify your display port in the /tmp/.X11-unix file as shown below. For example, the user ben is on port X51.
$ ls -la /tmp/.X11-unix/
drwxrwxrwt 2 root root 4096 Jan 6 05:01 .
drwxrwxrwt 122 root root 40960 Jan 17 08:09 ..
srwxrwxrwx 1 root root 0 Jan 5 08:48 X0
srwxrwxrwx 1 xwalter xwalter 0 Jan 5 09:21 X50
srwxrwxrwx 1 ben ben 0 Jan 6 05:01 X51
Then run podman with the display number after the X (51 in this case). The -v options also mount the user’s home directory (/home/ben) and cad tools (/cad) to be visible from the container. Change these as necessary based on your local system configuration.
$ podman run -it --net=host -e DISPLAY=:51 -v /tmp/.X11-unix:/tmp/.X11-unix -v /home/ben:/home/ben -v /cad:/cad -p 8080:8080 docker.io/wallysoc/wally-docker
Podman sets up all the RISC-V software in the same location of /opt/riscv as the cad user as discussed previously. This shared directory is called $RISCV. This environmental variable should also be set up within the Docker container automatically and ready to use once the container is run. It is important to understand that Docker containers are self-contained, and any data created within your container is lost when you exit the container. Therefore, be sure to work in your mounted home directory (e.g. /home/ben) to permanently save your work outside the container.
To have permission to write to your mounted home directory, you must become root inside the Wally container. This is an acceptable practice as the security will be maintained within podman for the user that runs podman. To become root once inside your container:
$ su # when prompted for password, enter wally
D.3.4 Cleaning up a Podman Container
The Docker container image is large, so users may need to clean up a container when they aren’t using it anymore.
The images that are loaded can be examined, once you pull the Wally container, by typing:
$ podman images
To remove individual podman images, the following Linux command will remove the specific podman image where the image name is obtained from the podman images command (this command also works equally well using the <Image_ID> instead of the <Image_name>, as well).
$ podman rmi -f <Image_name>
D.3.5 Running the Docker Container on Windows or MacOS
Docker Desktop is easiest to use for Mac OS or Windows and can be installed by downloading from http://docker.com. Once the desktop application is installed, users can log into their DockerHub account through the Docker Desktop application and manage their containers easily.
*** with Questa
*** questa unavailable native on Mac
D.3.6 Regenerating the Docker File
We use the following steps to generate the Docker file. You can adapt them is you wish to make your own custom Docker image, such as one with commercial CAD tools installed in your local environment.
*** how to use this
# Compliance Development Environment Image
FROM debian
# UPDATE / UPGRADE
RUN apt update
# INSTALL
RUN apt install -y git gawk make texinfo bison flex build-essential python libz-
dev libexpat-dev autoconf device-tree-compiler ninja-build libpixman-1-dev build
-essential ncurses-base ncurses-bin libncurses5-dev dialog curl wget ftp libgmp-
dev python3-pip pkg-config libglib2.0-dev opam build-essential z3 pkg-config zl
ib1g-dev verilator cpio bc vim emacs gedit nano
RUN pip3 install chardet==3.0.4
RUN pip3 install urllib3==1.22
RUN pip3 install testresources
RUN pip3 install riscof --ignore-installed PyYAML
RUN echo "root:wally" | chpasswd
# ADD RISCV
WORKDIR /opt/riscv
# Create a user group 'xyzgroup'
ARG USERNAME=cad
ARG USER_UID=1000
ARG USER_GID=$USER_UID
# Create the user
RUN groupadd --gid $USER_GID $USERNAME \
&& useradd --uid $USER_UID --gid $USER_GID -m $USERNAME \
# [Optional] Add sudo support. Omit if you don't need to install software af
ter connecting.
&& apt-get update \
&& apt-get install -y sudo \
&& echo $USERNAME ALL=\(root\) NOPASSWD:ALL > /etc/sudoers.d/$USERNAME \
&& chmod 0440 /etc/sudoers.d/$USERNAME
# Change RISCV user
run chown -Rf cad:cad /opt
# Add cad user
USER $USERNAME
# SET ENVIRONMENT VARIABLES
ENV RISCV=/opt/riscv
ENV PATH=$PATH:$RISCV/bin
# TOOLCHAIN
RUN git clone https://github.com/riscv/riscv-gnu-toolchain && \
cd riscv-gnu-toolchain && \
./configure --prefix=${RISCV} --enable-multilib --with-multilib-generator="r
v32e-ilp32e--;rv32i-ilp32--;rv32im-ilp32--;rv32iac-ilp32--;rv32imac-ilp32--;rv32
imafc-ilp32f--;rv32imafdc-ilp32d--;rv64i-lp64--;rv64ic-lp64--;rv64iac-lp64--;rv6
4imac-lp64--;rv64imafdc-lp64d--;rv64im-lp64--;" && \
make --jobs && \
make install
# elf2hex
ENV PATH=$RISCV/riscv-gnu-toolchain/bin:$PATH
WORKDIR /opt/riscv
RUN git clone https://github.com/sifive/elf2hex.git && \
cd elf2hex && \
autoreconf -i && \
./configure --target=riscv64-unknown-elf --prefix=$RISCV && \
make && \
make install
# QEMU
WORKDIR /opt/riscv
RUN git clone --recurse-submodules https://github.com/qemu/qemu && \
cd qemu && \
./configure --target-list=riscv64-softmmu --prefix=$RISCV && \
make --jobs && \
make install
# Spike
WORKDIR /opt/riscv
RUN git clone https://github.com/riscv-software-src/riscv-isa-sim && \
mkdir riscv-isa-sim/build && \
cd riscv-isa-sim/build && \
../configure --prefix=$RISCV --enable-commitlog && \
make --jobs && \
make install && \
cd ../arch_test_target/spike/device && \
sed -i 's/--isa=rv32ic/--isa=rv32iac/' rv32i_m/privilege/Makefile.include && \
sed -i 's/--isa=rv64ic/--isa=rv64iac/' rv64i_m/privilege/Makefile.include
# SAIL
WORKDIR /opt/riscv
RUN opam init -y --disable-sandboxing
RUN opam switch create ocaml-base-compiler.4.06.1
RUN opam install sail -y
RUN eval $(opam config env) && \
cd $RISCV && \
git clone https://github.com/riscv/sail-riscv.git && \
cd sail-riscv && \
make && \
ARCH=RV32 make && \
ARCH=RV64 make && \
ln -s $RISCV/sail-riscv/c_emulator/riscv_sim_RV64 $RISCV/bin/riscv_sim_RV64 &&
\
ln -s $RISCV/sail-riscv/c_emulator/riscv_sim_RV32 $RISCV/bin/riscv_sim_RV32
# Buildroot
WORKDIR /opt/riscv
RUN git clone --recurse-submodules https://stineje:ghp_kXIHqiMSv4tFec2BCAvrhSrIh
3KNUD06IejU@github.com/davidharrishmc/riscv-wally.git
ENV export WALLY=/opt/riscv/riscv-wally
RUN git clone https://github.com/buildroot/buildroot.git && \
cd buildroot && \
git checkout 2021.05 && \
cp -r /opt/riscv/riscv-wally/linux/buildroot-config-src/wally ./board && \
cp ./board/wally/main.config .config && \
make --jobs
# change to cad's hometown
WORKDIR /home/cad
D.3.7 Integrating Commercial CAD Tools into a Local Docker Container
RISC-V System-on-Chip Design Lecture Notes
© 2023 D. Harris, J. Stine, , R. Thompson, and S. Harris
These notes may be used and modified for educational and/or non-commercial purposes so long as the source is attributed.

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@ -1,3 +1,28 @@
###########################################
## Dockerfile
##
## Written: james.stine@okstate.edu 28 January 2023
## Modified:
##
## Purpose: Dockerfile for Wally docker container creation
##
## A component of the CORE-V-WALLY configurable RISC-V project.
##
## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
##
## SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
##
## Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
## except in compliance with the License, or, at your option, the Apache License version 2.0. You
## may obtain a copy of the License at
##
## https:##solderpad.org#licenses#SHL-2.1#
##
## Unless required by applicable law or agreed to in writing, any work distributed under the
## License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
## either express or implied. See the License for the specific language governing permissions
## and limitations under the License.
################################################################################################
# Compliance Development Environment Image
FROM debian

2
examples/C/sum/Makefile
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@ -4,7 +4,7 @@ $(TARGET).objdump: $(TARGET)
riscv64-unknown-elf-objdump -S -D $(TARGET) > $(TARGET).objdump
$(TARGET): $(TARGET).c Makefile
riscv64-unknown-elf-gcc -o $(TARGET) -g -O\
riscv64-unknown-elf-gcc -o $(TARGET) -gdwarf-2 -O\
-march=rv64gc -mabi=lp64d -mcmodel=medany \
-nostdlib -static -lm -fno-tree-loop-distribute-patterns \
-T../common/test.ld -I../common \

33
pipelined/config/buildroot/wally-config.vh
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@ -11,18 +11,19 @@
//
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
//
// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
// is furnished to do so, subject to the following conditions:
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
//
// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
// may obtain a copy of the License at
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
///////////////////////////////////////////
// https://solderpad.org/licenses/SHL-2.1/
//
// Unless required by applicable law or agreed to in writing, any work distributed under the
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
// either express or implied. See the License for the specific language governing permissions
// and limitations under the License.
////////////////////////////////////////////////////////////////////////////////////////////////
// include shared configuration
`include "wally-shared.vh"
@ -41,12 +42,11 @@
`define ZICOUNTERS_SUPPORTED 1
`define ZFH_SUPPORTED 0
`define COUNTERS 32
`define DESIGN_COMPILER 0
// LSU microarchitectural Features
`define BUS 1
`define DCACHE 1
`define ICACHE 1
`define BUS_SUPPORTED 1
`define DCACHE_SUPPORTED 1
`define ICACHE_SUPPORTED 1
`define VIRTMEM_SUPPORTED 1
`define VECTORED_INTERRUPTS_SUPPORTED 1
`define BIGENDIAN_SUPPORTED 1
@ -126,9 +126,10 @@
// Interrupt configuration
`define PLIC_NUM_SRC 53
`define PLIC_UART_ID 10
`define PLIC_GPIO_ID 3
`define BPRED_ENABLED 1
`define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
`define BPRED_SUPPORTED 1
`define BPRED_TYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
`define TESTSBP 0
`define BPRED_SIZE 10

38
pipelined/config/fpga/wally-config.vh
View File

@ -11,25 +11,25 @@
//
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
//
// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
// is furnished to do so, subject to the following conditions:
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
//
// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
// may obtain a copy of the License at
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
///////////////////////////////////////////
// https://solderpad.org/licenses/SHL-2.1/
//
// Unless required by applicable law or agreed to in writing, any work distributed under the
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
// either express or implied. See the License for the specific language governing permissions
// and limitations under the License.
////////////////////////////////////////////////////////////////////////////////////////////////
// include shared configuration
`include "wally-shared.vh"
`define FPGA 1
`define QEMU 0
`define DESIGN_COMPILER 0
// RV32 or RV64: XLEN = 32 or 64
`define XLEN 64
@ -43,12 +43,11 @@
`define ZICOUNTERS_SUPPORTED 1
`define ZFH_SUPPORTED 0
`define COUNTERS 32
`define DESIGN_COMPILER 0
// LSU microarchitectural Features
`define BUS 1
`define DCACHE 1
`define ICACHE 1
`define BUS_SUPPORTED 1
`define DCACHE_SUPPORTED 1
`define ICACHE_SUPPORTED 1
`define VIRTMEM_SUPPORTED 1
`define VECTORED_INTERRUPTS_SUPPORTED 1
`define BIGENDIAN_SUPPORTED 1
@ -72,7 +71,7 @@
`define IDIV_ON_FPU 1
// Legal number of PMP entries are 0, 16, or 64
`define PMP_ENTRIES 64
`define PMP_ENTRIES 16
// Address space
`define RESET_VECTOR 64'h0000000000001000
@ -136,11 +135,10 @@
// Interrupt configuration
`define PLIC_NUM_SRC 53
`define PLIC_UART_ID 10
`define PLIC_GPIO_ID 3
`define TWO_BIT_PRELOAD "../config/fpga/twoBitPredictor.txt"
`define BTB_PRELOAD "../config/fpga/BTBPredictor.txt"
`define BPRED_ENABLED 1
`define BPTYPE "BPSPECULATIVEGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE or BPSPECULATIVEGLOBAL or BPSPECULATIVEGSHARE or BPOLDGSHARE or BPOLDGSHARE2
`define BPRED_SUPPORTED 1
`define BPRED_TYPE "BPSPECULATIVEGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE or BPSPECULATIVEGLOBAL or BPSPECULATIVEGSHARE or BPOLDGSHARE or BPOLDGSHARE2
`define TESTSBP 1
`define BPRED_SIZE 10

34
pipelined/config/rv32e/wally-config.vh
View File

@ -11,25 +11,25 @@
//
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
//
// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
// is furnished to do so, subject to the following conditions:
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
//
// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
// may obtain a copy of the License at
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
///////////////////////////////////////////
// https://solderpad.org/licenses/SHL-2.1/
//
// Unless required by applicable law or agreed to in writing, any work distributed under the
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
// either express or implied. See the License for the specific language governing permissions
// and limitations under the License.
////////////////////////////////////////////////////////////////////////////////////////////////
// include shared configuration
`include "wally-shared.vh"
`define FPGA 0
`define QEMU 0
`define DESIGN_COMPILER 0
// RV32 or RV64: XLEN = 32 or 64
`define XLEN 32
@ -46,9 +46,9 @@
`define ZFH_SUPPORTED 0
// LSU microarchitectural Features
`define BUS 1
`define DCACHE 0
`define ICACHE 0
`define BUS_SUPPORTED 1
`define DCACHE_SUPPORTED 0
`define ICACHE_SUPPORTED 0
`define VIRTMEM_SUPPORTED 0
`define VECTORED_INTERRUPTS_SUPPORTED 0
`define BIGENDIAN_SUPPORTED 0
@ -69,7 +69,7 @@
// Integer Divider Configuration
// IDIV_BITSPERCYCLE must be 1, 2, or 4
`define IDIV_BITSPERCYCLE 1
`define IDIV_ON_FPU 1
`define IDIV_ON_FPU 0
// Legal number of PMP entries are 0, 16, or 64
`define PMP_ENTRIES 0
@ -132,8 +132,8 @@
`define PLIC_GPIO_ID 3
`define PLIC_UART_ID 10
`define BPRED_ENABLED 0
`define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
`define BPRED_SUPPORTED 0
`define BPRED_TYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
`define TESTSBP 0
`define BPRED_SIZE 10

35
pipelined/config/rv32gc/wally-config.vh
View File

@ -11,25 +11,25 @@
//
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
//
// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
// is furnished to do so, subject to the following conditions:
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
//
// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
// may obtain a copy of the License at
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
///////////////////////////////////////////
// https://solderpad.org/licenses/SHL-2.1/
//
// Unless required by applicable law or agreed to in writing, any work distributed under the
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
// either express or implied. See the License for the specific language governing permissions
// and limitations under the License.
////////////////////////////////////////////////////////////////////////////////////////////////
// include shared configuration
`include "wally-shared.vh"
`define FPGA 0
`define QEMU 0
`define DESIGN_COMPILER 0
// RV32 or RV64: XLEN = 32 or 64
`define XLEN 32
@ -45,9 +45,9 @@
`define ZFH_SUPPORTED 0
// LSU microarchitectural Features
`define BUS 1
`define DCACHE 1
`define ICACHE 1
`define BUS_SUPPORTED 1
`define DCACHE_SUPPORTED 1
`define ICACHE_SUPPORTED 1
`define VIRTMEM_SUPPORTED 1
`define VECTORED_INTERRUPTS_SUPPORTED 1
`define BIGENDIAN_SUPPORTED 1
@ -68,7 +68,7 @@
// Integer Divider Configuration
// IDIV_BITSPERCYCLE must be 1, 2, or 4
`define IDIV_BITSPERCYCLE 4
`define IDIV_ON_FPU 1
`define IDIV_ON_FPU 0
// Legal number of PMP entries are 0, 16, or 64
`define PMP_ENTRIES 16
@ -131,9 +131,8 @@
`define PLIC_GPIO_ID 3
`define PLIC_UART_ID 10
`define BPRED_ENABLED 1
//`define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
`define BPTYPE "BPSPECULATIVEGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
`define BPRED_SUPPORTED 1
`define BPRED_TYPE "BPSPECULATIVEGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
`define TESTSBP 0
`define BPRED_SIZE 10

36
pipelined/config/rv32i/wally-config.vh
View File

@ -11,25 +11,25 @@
//
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
//
// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
// is furnished to do so, subject to the following conditions:
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
//
// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
// may obtain a copy of the License at
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
///////////////////////////////////////////
// https://solderpad.org/licenses/SHL-2.1/
//
// Unless required by applicable law or agreed to in writing, any work distributed under the
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
// either express or implied. See the License for the specific language governing permissions
// and limitations under the License.
////////////////////////////////////////////////////////////////////////////////////////////////
// include shared configuration
`include "wally-shared.vh"
`define FPGA 0
`define QEMU 0
`define DESIGN_COMPILER 0
// RV32 or RV64: XLEN = 32 or 64
`define XLEN 32
@ -46,9 +46,9 @@
`define ZFH_SUPPORTED 0
// LSU microarchitectural Features
`define BUS 0
`define DCACHE 0
`define ICACHE 0
`define BUS_SUPPORTED 0
`define DCACHE_SUPPORTED 0
`define ICACHE_SUPPORTED 0
`define VIRTMEM_SUPPORTED 0
`define VECTORED_INTERRUPTS_SUPPORTED 1
`define BIGENDIAN_SUPPORTED 0
@ -69,10 +69,10 @@
// Integer Divider Configuration
// IDIV_BITSPERCYCLE must be 1, 2, or 4
`define IDIV_BITSPERCYCLE 4
`define IDIV_ON_FPU 1
`define IDIV_ON_FPU 0
// Legal number of PMP entries are 0, 16, or 64
`define PMP_ENTRIES 64
`define PMP_ENTRIES 0
// Address space
`define RESET_VECTOR 32'h80000000
@ -132,8 +132,8 @@
`define PLIC_GPIO_ID 3
`define PLIC_UART_ID 10
`define BPRED_ENABLED 1
`define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
`define BPRED_SUPPORTED 0
`define BPRED_TYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
`define TESTSBP 0
`define BPRED_SIZE 10

34
pipelined/config/rv32ic/wally-config.vh
View File

@ -11,25 +11,25 @@
//
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
//
// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
// is furnished to do so, subject to the following conditions:
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
//
// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
// may obtain a copy of the License at
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
///////////////////////////////////////////
// https://solderpad.org/licenses/SHL-2.1/
//
// Unless required by applicable law or agreed to in writing, any work distributed under the
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
// either express or implied. See the License for the specific language governing permissions
// and limitations under the License.
////////////////////////////////////////////////////////////////////////////////////////////////
// include shared configuration
`include "wally-shared.vh"
`define FPGA 0
`define QEMU 0
`define DESIGN_COMPILER 0
// RV32 or RV64: XLEN = 32 or 64
`define XLEN 32
@ -45,9 +45,9 @@
`define ZFH_SUPPORTED 0
// LSU microarchitectural Features
`define BUS 1
`define DCACHE 0
`define ICACHE 0
`define BUS_SUPPORTED 1
`define DCACHE_SUPPORTED 0
`define ICACHE_SUPPORTED 0
`define VIRTMEM_SUPPORTED 0
`define VECTORED_INTERRUPTS_SUPPORTED 1
`define BIGENDIAN_SUPPORTED 0
@ -68,7 +68,7 @@
// Integer Divider Configuration
// IDIV_BITSPERCYCLE must be 1, 2, or 4
`define IDIV_BITSPERCYCLE 4
`define IDIV_ON_FPU 1
`define IDIV_ON_FPU 0
// Legal number of PMP entries are 0, 16, or 64
`define PMP_ENTRIES 0
@ -131,8 +131,8 @@
`define PLIC_GPIO_ID 3
`define PLIC_UART_ID 10
`define BPRED_ENABLED 1
`define BPTYPE "BPSPECULATIVEGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
`define BPRED_SUPPORTED 0
`define BPRED_TYPE "BPSPECULATIVEGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
`define TESTSBP 0
`define BPRED_SIZE 10

34
pipelined/config/rv64fpquad/wally-config.vh
View File

@ -11,25 +11,25 @@
//
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
//
// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
// is furnished to do so, subject to the following conditions:
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
//
// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
// may obtain a copy of the License at
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
///////////////////////////////////////////
// https://solderpad.org/licenses/SHL-2.1/
//
// Unless required by applicable law or agreed to in writing, any work distributed under the
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
// either express or implied. See the License for the specific language governing permissions
// and limitations under the License.
////////////////////////////////////////////////////////////////////////////////////////////////
// include shared configuration
`include "wally-shared.vh"
`define FPGA 0
`define QEMU 0
`define DESIGN_COMPILER 0
// RV32 or RV64: XLEN = 32 or 64
`define XLEN 64
@ -46,9 +46,9 @@
`define ZFH_SUPPORTED 1
// LSU microarchitectural Features
`define BUS 1
`define DCACHE 1
`define ICACHE 1
`define BUS_SUPPORTED 1
`define DCACHE_SUPPORTED 1
`define ICACHE_SUPPORTED 1
`define VIRTMEM_SUPPORTED 1
`define VECTORED_INTERRUPTS_SUPPORTED 1
`define BIGENDIAN_SUPPORTED 1
@ -72,7 +72,7 @@
`define IDIV_ON_FPU 1
// Legal number of PMP entries are 0, 16, or 64
`define PMP_ENTRIES 64
`define PMP_ENTRIES 16
// Address space
`define RESET_VECTOR 64'h0000000080000000
@ -134,8 +134,8 @@
`define PLIC_GPIO_ID 3
`define PLIC_UART_ID 10
`define BPRED_ENABLED 1
`define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
`define BPRED_SUPPORTED 1
`define BPRED_TYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
`define TESTSBP 0
`define BPRED_SIZE 10

35
pipelined/config/rv64gc/wally-config.vh
View File

@ -11,25 +11,25 @@
//
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
//
// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
// is furnished to do so, subject to the following conditions:
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
//
// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
// may obtain a copy of the License at
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
///////////////////////////////////////////
// https://solderpad.org/licenses/SHL-2.1/
//
// Unless required by applicable law or agreed to in writing, any work distributed under the
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
// either express or implied. See the License for the specific language governing permissions
// and limitations under the License.
////////////////////////////////////////////////////////////////////////////////////////////////
// include shared configuration
`include "wally-shared.vh"
`define FPGA 0
`define QEMU 0
`define DESIGN_COMPILER 0
// RV32 or RV64: XLEN = 32 or 64
`define XLEN 64
@ -46,9 +46,9 @@
`define ZFH_SUPPORTED 0
// LSU microarchitectural Features
`define BUS 1
`define DCACHE 1
`define ICACHE 1
`define BUS_SUPPORTED 1
`define DCACHE_SUPPORTED 1
`define ICACHE_SUPPORTED 1
`define VIRTMEM_SUPPORTED 1
`define VECTORED_INTERRUPTS_SUPPORTED 1
`define BIGENDIAN_SUPPORTED 1
@ -134,11 +134,8 @@
`define PLIC_GPIO_ID 3
`define PLIC_UART_ID 10
`define BPRED_ENABLED 1
`define BPTYPE "BPSPECULATIVEGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE or BPSPECULATIVEGLOBAL or BPSPECULATIVEGSHARE or BPOLDGSHARE or BPOLDGSHARE2
//`define BPTYPE "BPSPECULATIVEGLOBAL" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE or BPSPECULATIVEGLOBAL or BPSPECULATIVEGSHARE or BPOLDGSHARE or BPOLDGSHARE2
//`define BPTYPE "BPGLOBAL" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE or BPSPECULATIVEGLOBAL or BPSPECULATIVEGSHARE or BPOLDGSHARE or BPOLDGSHARE2
//`define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE or BPSPECULATIVEGLOBAL or BPSPECULATIVEGSHARE or BPOLDGSHARE or BPOLDGSHARE2//`define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE or BPSPECULATIVEGLOBAL or BPSPECULATIVEGSHARE or BPOLDGSHARE or BPOLDGSHARE2
`define BPRED_SUPPORTED 1
`define BPRED_TYPE "BPSPECULATIVEGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE or BPSPECULATIVEGLOBAL or BPSPECULATIVEGSHARE or BPOLDGSHARE or BPOLDGSHARE2
`define TESTSBP 0
`define BPRED_SIZE 10

34
pipelined/config/rv64i/wally-config.vh
View File

@ -11,25 +11,25 @@
//
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
//
// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
// is furnished to do so, subject to the following conditions:
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
//
// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
// may obtain a copy of the License at
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
///////////////////////////////////////////
// https://solderpad.org/licenses/SHL-2.1/
//
// Unless required by applicable law or agreed to in writing, any work distributed under the
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
// either express or implied. See the License for the specific language governing permissions
// and limitations under the License.
////////////////////////////////////////////////////////////////////////////////////////////////
// include shared configuration
`include "wally-shared.vh"
`define FPGA 0
`define QEMU 0
`define DESIGN_COMPILER 0
// RV32 or RV64: XLEN = 32 or 64
`define XLEN 64
@ -46,9 +46,9 @@
`define ZFH_SUPPORTED 0
// LSU microarchitectural Features
`define BUS 0
`define DCACHE 0
`define ICACHE 0
`define BUS_SUPPORTED 0
`define DCACHE_SUPPORTED 0
`define ICACHE_SUPPORTED 0
`define VIRTMEM_SUPPORTED 0
`define VECTORED_INTERRUPTS_SUPPORTED 1
`define BIGENDIAN_SUPPORTED 0
@ -69,7 +69,7 @@
// Integer Divider Configuration
// IDIV_BITSPERCYCLE must be 1, 2, or 4
`define IDIV_BITSPERCYCLE 4
`define IDIV_ON_FPU 1
`define IDIV_ON_FPU 0
// Legal number of PMP entries are 0, 16, or 64
`define PMP_ENTRIES 0
@ -134,8 +134,8 @@
`define PLIC_GPIO_ID 3
`define PLIC_UART_ID 10
`define BPRED_ENABLED 0
`define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
`define BPRED_SUPPORTED 0
`define BPRED_TYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
`define TESTSBP 0
`define BPRED_SIZE 10

21
pipelined/config/shared/wally-constants.vh
View File

@ -15,18 +15,19 @@
//
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
//
// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
// is furnished to do so, subject to the following conditions:
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
//
// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
// may obtain a copy of the License at
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
///////////////////////////////////////////
// https://solderpad.org/licenses/SHL-2.1/
//
// Unless required by applicable law or agreed to in writing, any work distributed under the
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
// either express or implied. See the License for the specific language governing permissions
// and limitations under the License.
////////////////////////////////////////////////////////////////////////////////////////////////
// constants defining different privilege modes
// defined in Table 1.1 of the privileged spec

21
pipelined/config/shared/wally-shared.vh
View File

@ -9,18 +9,19 @@
//
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
//
// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
// is furnished to do so, subject to the following conditions:
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
//
// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
// may obtain a copy of the License at
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
///////////////////////////////////////////
// https://solderpad.org/licenses/SHL-2.1/
//
// Unless required by applicable law or agreed to in writing, any work distributed under the
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
// either express or implied. See the License for the specific language governing permissions
// and limitations under the License.
////////////////////////////////////////////////////////////////////////////////////////////////
// division constants
`define RADIX 32'h4

3
pipelined/regression/regression-wally
View File

@ -204,9 +204,6 @@ def main():
# Count the number of failures
if num_fail:
print(f"{bcolors.FAIL}Regression failed with %s failed configurations{bcolors.ENDC}" % num_fail)
# Remind the user to try `make allclean`, since it may be needed if test
# cases have changed
print("Reminder: have you run `make allclean`?")
else:
print(f"{bcolors.OKGREEN}SUCCESS! All tests ran without failures{bcolors.ENDC}")
return num_fail

6
pipelined/src/cache/cacheLRU.sv vendored
View File

@ -81,8 +81,8 @@ module cacheLRU
// expand HitWay as HitWay[3], {{2}{HitWay[2]}}, {{4}{HitWay[1]}, {{8{HitWay[0]}}, ...
for(row = 0; row < LOGNUMWAYS; row++) begin
localparam integer DuplicationFactor = 2**(LOGNUMWAYS-row-1);
localparam integer StartIndex = NUMWAYS-2 - DuplicationFactor + 1;
localparam integer EndIndex = NUMWAYS-2 - 2 * DuplicationFactor + 2;
localparam StartIndex = NUMWAYS-2 - DuplicationFactor + 1;
localparam EndIndex = NUMWAYS-2 - 2 * DuplicationFactor + 2;
assign WayExpanded[StartIndex : EndIndex] = {{DuplicationFactor}{WayEncoded[row]}};
end
@ -109,8 +109,6 @@ module cacheLRU
for(s = NUMWAYS/2-1; s >= 0; s--) begin
localparam int0 = (NUMWAYS/2-1-s)*2;
localparam int1 = int0 + 1;
//localparam int0 = s*2;
//localparam int1 = int0 + 1;
assign Intermediate[s] = CurrLRU[s] ? int1[LOGNUMWAYS-1:0] : int0[LOGNUMWAYS-1:0];
end

16
pipelined/src/cache/cacheway.sv vendored
View File

@ -55,11 +55,11 @@ module cacheway #(parameter NUMLINES=512, LINELEN = 256, TAGLEN = 26,
output logic DirtyWay, // This way is dirty
output logic [TAGLEN-1:0] TagWay); // THis way's tag if valid
localparam integer WORDSPERLINE = LINELEN/`XLEN;
localparam integer BYTESPERLINE = LINELEN/8;
localparam WORDSPERLINE = LINELEN/`XLEN;
localparam BYTESPERLINE = LINELEN/8;
localparam LOGWPL = $clog2(WORDSPERLINE);
localparam LOGXLENBYTES = $clog2(`XLEN/8);
localparam integer BYTESPERWORD = `XLEN/8;
localparam BYTESPERWORD = `XLEN/8;
logic [NUMLINES-1:0] ValidBits;
logic [NUMLINES-1:0] DirtyBits;
@ -128,12 +128,12 @@ module cacheway #(parameter NUMLINES=512, LINELEN = 256, TAGLEN = 26,
// Data Array
/////////////////////////////////////////////////////////////////////////////////////////////
genvar words;
genvar words;
localparam integer SRAMLEN = 128;
localparam integer NUMSRAM = LINELEN/SRAMLEN;
localparam integer SRAMLENINBYTES = SRAMLEN/8;
localparam integer LOGNUMSRAM = $clog2(NUMSRAM);
localparam SRAMLEN = 128;
localparam NUMSRAM = LINELEN/SRAMLEN;
localparam SRAMLENINBYTES = SRAMLEN/8;
localparam LOGNUMSRAM = $clog2(NUMSRAM);
for(words = 0; words < NUMSRAM; words++) begin: word
ram1p1rwbe #(.DEPTH(NUMLINES), .WIDTH(SRAMLEN)) CacheDataMem(.clk, .ce(CacheEn), .addr(CAdr),

4
pipelined/src/cache/subcachelineread.sv vendored
View File

@ -30,8 +30,8 @@
`include "wally-config.vh"
module subcachelineread #(parameter LINELEN, WORDLEN,
parameter MUXINTERVAL // The number of bits between mux. Set to 16 for I$ to support compressed. Set to `LLEN for D$
)(
parameter MUXINTERVAL )( // The number of bits between mux. Set to 16 for I$ to support compressed. Set to `LLEN for D$
input logic [$clog2(LINELEN/8) - $clog2(MUXINTERVAL/8) - 1 : 0] PAdr, // Physical address
input logic [LINELEN-1:0] ReadDataLine,// Read data of the whole cacheline
output logic [WORDLEN-1:0] ReadDataWord // read data of selected word.

1
pipelined/src/cache/ts1n28hpcpsvtb64x128m4swbaso_180a_tt1v25c.v vendored
View File

@ -1 +0,0 @@
/proj/wally/memory/ts1n28hpcpsvtb64x128m4sw_180a/VERILOG/ts1n28hpcpsvtb64x128m4sw_180a_tt1v25c.v

20
pipelined/src/ebu/ahbcacheinterface.sv
View File

@ -30,10 +30,10 @@
`include "wally-config.vh"
module ahbcacheinterface #(
parameter integer BEATSPERLINE, // Number of AHBW words (beats) in cacheline
parameter integer AHBWLOGBWPL, // Log2 of ^
parameter integer LINELEN, // Number of bits in cacheline
parameter integer LLENPOVERAHBW // Number of AHB beats in a LLEN word. AHBW cannot be larger than LLEN. (implementation limitation)
parameter BEATSPERLINE, // Number of AHBW words (beats) in cacheline
parameter AHBWLOGBWPL, // Log2 of ^
parameter LINELEN, // Number of bits in cacheline
parameter LLENPOVERAHBW // Number of AHB beats in a LLEN word. AHBW cannot be larger than LLEN. (implementation limitation)
)(
input logic HCLK, HRESETn,
// bus interface controls
@ -72,12 +72,12 @@ module ahbcacheinterface #(
output logic BusCommitted); // Bus is busy with an in flight memory operation and it is not safe to take an interrupt
localparam integer BeatCountThreshold = BEATSPERLINE - 1; // Largest beat index
logic [`PA_BITS-1:0] LocalHADDR; // Address after selecting between cached and uncached operation
logic [AHBWLOGBWPL-1:0] BeatCountDelayed; // Beat within the cache line in the second (Data) cache stage
logic CaptureEn; // Enable updating the Fetch buffer with valid data from HRDATA
logic [`AHBW/8-1:0] BusByteMaskM; // Byte enables within a word. For cache request all 1s
logic [`AHBW-1:0] PreHWDATA; // AHB Address phase write data
localparam BeatCountThreshold = BEATSPERLINE - 1; // Largest beat index
logic [`PA_BITS-1:0] LocalHADDR; // Address after selecting between cached and uncached operation
logic [AHBWLOGBWPL-1:0] BeatCountDelayed; // Beat within the cache line in the second (Data) cache stage
logic CaptureEn; // Enable updating the Fetch buffer with valid data from HRDATA
logic [`AHBW/8-1:0] BusByteMaskM; // Byte enables within a word. For cache request all 1s
logic [`AHBW-1:0] PreHWDATA; // AHB Address phase write data
genvar index;

4
pipelined/src/ebu/buscachefsm.sv
View File

@ -32,8 +32,8 @@
// HCLK and clk must be the same clock!
module buscachefsm #(
parameter integer BeatCountThreshold, // Largest beat index
parameter integer AHBWLOGBWPL // Log2 of BEATSPERLINE
parameter BeatCountThreshold, // Largest beat index
parameter AHBWLOGBWPL // Log2 of BEATSPERLINE
)(
input logic HCLK,
input logic HRESETn,

28
pipelined/src/generic/mem/ram1p1rwbe.sv
View File

@ -49,17 +49,25 @@ module ram1p1rwbe #(parameter DEPTH=128, WIDTH=256) (
// ***************************************************************************
// TRUE SRAM macro
// ***************************************************************************
if (`USE_SRAM == 1) begin
if (`USE_SRAM == 1 && WIDTH == 128 && `XLEN == 64) begin
genvar index;
// 64 x 128-bit SRAM
// check if the size is ok, complain if not***
logic [WIDTH-1:0] BitWriteMask;
for (index=0; index < WIDTH; index++)
assign BitWriteMask[index] = bwe[index/8];
TS1N28HPCPSVTB64X128M4SW sram(
.CLK(clk), .CEB(~ce), .WEB(~we),
.A(addr), .D(din),
.BWEB(~BitWriteMask), .Q(dout));
// 64 x 128-bit SRAM
logic [WIDTH-1:0] BitWriteMask;
for (index=0; index < WIDTH; index++)
assign BitWriteMask[index] = bwe[index/8];
ram1p1rwbe_64x128 sram1A (.CLK(clk), .CEB(~ce), .WEB(~we),
.A(addr), .D(din),
.BWEB(~BitWriteMask), .Q(dout));
end else if (`USE_SRAM == 1 && WIDTH == 44 && `XLEN == 64) begin
genvar index;
// 64 x 44-bit SRAM
logic [WIDTH-1:0] BitWriteMask;
for (index=0; index < WIDTH; index++)
assign BitWriteMask[index] = bwe[index/8];
ram1p1rwbe_64x44 sram1B (.CLK(clk), .CEB(~ce), .WEB(~we),
.A(addr), .D(din),
.BWEB(~BitWriteMask), .Q(dout));
// ***************************************************************************
// READ first SRAM model

40
pipelined/src/generic/mem/ram1p1rwbe_64x128.sv Executable file
View File

@ -0,0 +1,40 @@
///////////////////////////////////////////
// ram1p1rwbe_64x128.sv
//
// Written: james.stine@okstate.edu 28 January 2023
// Modified:
//
// Purpose: RAM wrapper for instantiating RAM IP
//
// A component of the CORE-V-WALLY configurable RISC-V project.
//
// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
//
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
//
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
// may obtain a copy of the License at
//
// https://solderpad.org/licenses/SHL-2.1/
//
// Unless required by applicable law or agreed to in writing, any work distributed under the
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
// either express or implied. See the License for the specific language governing permissions
// and limitations under the License.
////////////////////////////////////////////////////////////////////////////////////////////////
module ram1p1rwbe_64x128(
input logic CLK,
input logic CEB,
input logic WEB,
input logic [5:0] A,
input logic [127:0] D,
input logic [127:0] BWEB,
output logic [127:0] Q
);
// replace "generic64x128RAM" with "TS1N..64X128.." module from your memory vendor
generic64x128RAM sramIP (.CLK, .CEB, .WEB, .A, .D, .BWEB, .Q);
endmodule

33
pipelined/src/bmu/bmu.sv → pipelined/src/generic/mem/ram1p1rwbe_64x44.sv
View File

@ -1,16 +1,11 @@
///////////////////////////////////////////
// bmu.sv
// ram1p1rwbe_64x44.sv
//
// Written: kekim@g.hmc.edu, David_Harris@hmc.edu 20 January 2023
// Written: james.stine@okstate.edu 28 January 2023
// Modified:
//
// Purpose: Bit manipulation extensions Zba, Zbb, Zbc, Zbs
// Single-cycle operation in Execute stage
// Purpose: RAM wrapper for instantiating RAM IP
//
// Documentation: n/a
// See RISC-V Bit-Manipulation ISA-extensions
// Version 1.0.0-38-g865e7a7, 2021-06-28: Release candidate
//
// A component of the CORE-V-WALLY configurable RISC-V project.
//
// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
@ -29,17 +24,17 @@
// and limitations under the License.
////////////////////////////////////////////////////////////////////////////////////////////////
`include "wally-config.vh"
module bmu(
input logic [`XLEN-1:0] ForwardedSrcAE, ForwardedSrcBE, // inputs A and B from IEU forwarding mux output
input logic [31:0] InstrD, // instruction
output logic BMUE, // bit manipulation instruction
output logic [`XLEN-1:0] BMUResultE // bit manipulation result
module ram1p1rwbe_64x44(
input logic CLK,
input logic CEB,
input logic WEB,
input logic [5:0] A,
input logic [127:0] D,
input logic [127:0] BWEB,
output logic [127:0] Q
);
// replace "generic64x44RAM" with "TS1N..64X44.." module from your memory vendor
generic64x44RAM sramIP (.CLK, .CEB, .WEB, .A, .D, .BWEB, .Q);
endmodule // mdu
endmodule

0
pipelined/src/generic/mem/ram2p1rwbe.sv → pipelined/src/generic/mem/ram2p1r1wbe.sv
View File

48
pipelined/src/generic/mem/ram2p1r1wbe_1024x69.sv Executable file
View File

@ -0,0 +1,48 @@
///////////////////////////////////////////
// ram2p1rwbe_1024x69.sv
//
// Written: james.stine@okstate.edu 28 January 2023
// Modified:
//
// Purpose: RAM wrapper for instantiating RAM IP
//
// A component of the CORE-V-WALLY configurable RISC-V project.
//
// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
//
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
//
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
// may obtain a copy of the License at
//
// https://solderpad.org/licenses/SHL-2.1/
//
// Unless required by applicable law or agreed to in writing, any work distributed under the
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
// either express or implied. See the License for the specific language governing permissions
// and limitations under the License.
////////////////////////////////////////////////////////////////////////////////////////////////
module ram2p1r1wbe_1024x69(
input logic CLKA,
input logic CLKB,
input logic CEBA,
input logic CEBB,
input logic WEBA,
input logic WEBB,
input logic [9:0] AA,
input logic [9:0] AB,
input logic [68:0] DA,
input logic [68:0] DB,
input logic [68:0] BWEBA,
input logic [68:0] BWEBB,
output logic [68:0] QA,
output logic [68:0] QB
);
// replace "generic1024x69RAM" with "TSDN..1024X69.." module from your memory vendor
generic1024x69RAM sramIP (.CLKA, .CLKB, .CEBA, .CEBB, .WEBA, .WEBB,
.AA, .AB, .DA, .DB, .BWEBA, .BWEBB, .QA, .QB);
endmodule

38
pipelined/src/generic/mem/rom1p1r_128x32.sv Executable file
View File

@ -0,0 +1,38 @@
///////////////////////////////////////////
// rom1p1r_128x32.sv
//
// Written: james.stine@okstate.edu 28 January 2023
// Modified:
//
// Purpose: RAM wrapper for instantiating RAM IP
//
// A component of the CORE-V-WALLY configurable RISC-V project.
//
// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
//
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
//
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
// may obtain a copy of the License at
//
// https://solderpad.org/licenses/SHL-2.1/
//
// Unless required by applicable law or agreed to in writing, any work distributed under the
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
// either express or implied. See the License for the specific language governing permissions
// and limitations under the License.
////////////////////////////////////////////////////////////////////////////////////////////////
module rom1p1r_128x32(
input logic CLK,
input logic CEB,
input logic [6:0] A,
output logic [31:0] Q
);
// replace "generic128x32ROM" with "TS3N..128X32.." module from your memory vendor
generic64x128ROM sramIP (.CLK, .CEB, .A, .Q);
endmodule

4
pipelined/src/ieu/controller.sv
View File

@ -200,7 +200,7 @@ module controller(
// Fences
// Ordinary fence is presently a nop
// fence.i flushes the D$ and invalidates the I$ if Zifencei is supported and I$ is implemented
if (`ZIFENCEI_SUPPORTED & `ICACHE) begin:fencei
if (`ZIFENCEI_SUPPORTED & `ICACHE_SUPPORTED) begin:fencei
logic FenceID;
assign FenceID = FenceXD & (Funct3D == 3'b001); // is it a FENCE.I instruction?
assign InvalidateICacheD = FenceID;
@ -249,5 +249,5 @@ module controller(
// the synchronous DTIM cannot read immediately after write
// a cache cannot read or write immediately after a write
assign StoreStallD = MemRWE[0] & ((MemRWD[1] | (MemRWD[0] & `DCACHE)) | (|AtomicD));
assign StoreStallD = MemRWE[0] & ((MemRWD[1] | (MemRWD[0] & `DCACHE_SUPPORTED)) | (|AtomicD));
endmodule

8
pipelined/src/ieu/datapath.sv
View File

@ -48,7 +48,6 @@ module datapath (
output logic [1:0] FlagsE, // Comparison flags ({eq, lt})
output logic [`XLEN-1:0] IEUAdrE, // Address computed by ALU
output logic [`XLEN-1:0] ForwardedSrcAE, ForwardedSrcBE, // ALU sources before the mux chooses between them and PCE to put in srcA/B
input logic BMUE, // Bit manipulation instruction
// Memory stage signals
input logic StallM, FlushM, // Stall, flush Memory stage
input logic FWriteIntM, FCvtIntW, // FPU writes integer register file, FPU converts float to int
@ -64,7 +63,6 @@ module datapath (
input logic [`XLEN-1:0] ReadDataW, // Read data from LSU
input logic [`XLEN-1:0] CSRReadValW, // CSR read result
input logic [`XLEN-1:0] MDUResultW, // MDU (Multiply/divide unit) result
input logic [`XLEN-1:0] BMUResultE, // bit manipulation unit result
input logic [`XLEN-1:0] FIntDivResultW, // FPU's integer divide result
// Hazard Unit signals
output logic [4:0] Rs1D, Rs2D, Rs1E, Rs2E, // Register sources to read in Decode or Execute stage
@ -81,7 +79,6 @@ module datapath (
logic [`XLEN-1:0] ImmExtE; // Extended immediate in Execute stage
logic [`XLEN-1:0] SrcAE, SrcBE; // ALU operands
logic [`XLEN-1:0] ALUResultE, AltResultE, IEUResultE; // ALU result, Alternative result (ImmExtE or PC+4), result of execution stage
logic [`XLEN-1:0] IEUBResultE; // IEUResultE before optional bit manipulation mux
// Memory stage signals
logic [`XLEN-1:0] IEUResultM; // Result from execution stage
logic [`XLEN-1:0] IFResultM; // Result from either IEU or single-cycle FPU op writing an integer register
@ -114,10 +111,7 @@ module datapath (
mux2 #(`XLEN) srcbmux(ForwardedSrcBE, ImmExtE, ALUSrcBE, SrcBE);
alu #(`XLEN) alu(SrcAE, SrcBE, ALUControlE, Funct3E, ALUResultE, IEUAdrE);
mux2 #(`XLEN) altresultmux(ImmExtE, PCLinkE, JumpE, AltResultE);
mux2 #(`XLEN) ieuresultmux(ALUResultE, AltResultE, ALUResultSrcE, IEUBResultE);
if (`B_SUPPORTED)
mux2 #(`XLEN) bmuresultmux(IEUResultE, BMUResultE, BMUE, IEUResultE);
else assign IEUResultE = IEUBResultE;
mux2 #(`XLEN) ieuresultmux(ALUResultE, AltResultE, ALUResultSrcE, IEUResultE);
// Memory stage pipeline register
flopenrc #(`XLEN) SrcAMReg(clk, reset, FlushM, ~StallM, SrcAE, SrcAM);

6
pipelined/src/ieu/ieu.sv
View File

@ -43,7 +43,6 @@ module ieu (
output logic IntDivE, W64E, // Integer divide, RV64 W-type instruction
output logic [2:0] Funct3E, // Funct3 instruction field
output logic [`XLEN-1:0] ForwardedSrcAE, ForwardedSrcBE, // ALU src inputs before the mux choosing between them and PCE to put in srcA/B
input logic BMUE, // This is a bit manipulation instruction
output logic [4:0] RdE, // Destination register
// Memory stage signals
input logic SquashSCW, // Squash store conditional, from LSU
@ -60,7 +59,6 @@ module ieu (
input logic [`XLEN-1:0] FIntDivResultW, // Integer divide result from FPU fdivsqrt)
input logic [`XLEN-1:0] CSRReadValW, // CSR read value,
input logic [`XLEN-1:0] MDUResultW, // multiply/divide unit result
input logic [`XLEN-1:0] BMUResultE, // bit manipulation unit result
input logic [`XLEN-1:0] FCvtIntResW, // FPU's float to int conversion result
input logic FCvtIntW, // FPU converts float to int
output logic [4:0] RdW, // Destination register
@ -105,10 +103,10 @@ module ieu (
datapath dp(
.clk, .reset, .ImmSrcD, .InstrD, .StallE, .FlushE, .ForwardAE, .ForwardBE,
.ALUControlE, .Funct3E, .ALUSrcAE, .ALUSrcBE, .ALUResultSrcE, .JumpE, .BranchSignedE,
.PCE, .PCLinkE, .FlagsE, .IEUAdrE, .ForwardedSrcAE, .ForwardedSrcBE, .BMUE,
.PCE, .PCLinkE, .FlagsE, .IEUAdrE, .ForwardedSrcAE, .ForwardedSrcBE,
.StallM, .FlushM, .FWriteIntM, .FIntResM, .SrcAM, .WriteDataM, .FCvtIntW,
.StallW, .FlushW, .RegWriteW, .IntDivW, .SquashSCW, .ResultSrcW, .ReadDataW, .FCvtIntResW,
.CSRReadValW, .MDUResultW, .BMUResultE, .FIntDivResultW, .Rs1D, .Rs2D, .Rs1E, .Rs2E, .RdE, .RdM, .RdW);
.CSRReadValW, .MDUResultW, .FIntDivResultW, .Rs1D, .Rs2D, .Rs1E, .Rs2E, .RdE, .RdM, .RdW);
forward fw(
.Rs1D, .Rs2D, .Rs1E, .Rs2E, .RdE, .RdM, .RdW,

4
pipelined/src/ifu/brpred/RAsPredictor.sv → pipelined/src/ifu/bpred/RAsPredictor.sv
View File

@ -29,8 +29,8 @@
`include "wally-config.vh"
module RASPredictor #(parameter int StackSize = 16
)(input logic clk,
module RASPredictor #(parameter int StackSize = 16 )(
input logic clk,
input logic reset,
input logic StallF, StallD, StallE, StallM, FlushD, FlushE, FlushM,
input logic [3:0] WrongPredInstrClassD, // Prediction class is wrong

72
pipelined/src/ifu/brpred/bpred.sv → pipelined/src/ifu/bpred/bpred.sv
View File

@ -31,40 +31,40 @@
`define INSTR_CLASS_PRED 1
module bpred (
input logic clk, reset,
input logic StallF, StallD, StallE, StallM, StallW,
input logic FlushD, FlushE, FlushM, FlushW,
// Fetch stage
// the prediction
input logic [31:0] InstrD, // Decompressed decode stage instruction. Used to decode instruction class
input logic [`XLEN-1:0] PCNextF, // Next Fetch Address
input logic [`XLEN-1:0] PCPlus2or4F, // PCF+2/4
output logic [`XLEN-1:0] PCNext1F, // Branch Predictor predicted or corrected fetch address on miss prediction
output logic [`XLEN-1:0] NextValidPCE, // Address of next valid instruction after the instruction in the Memory stage
input logic clk, reset,
input logic StallF, StallD, StallE, StallM, StallW,
input logic FlushD, FlushE, FlushM, FlushW,
// Fetch stage
// the prediction
input logic [31:0] InstrD, // Decompressed decode stage instruction. Used to decode instruction class
input logic [`XLEN-1:0] PCNextF, // Next Fetch Address
input logic [`XLEN-1:0] PCPlus2or4F, // PCF+2/4
output logic [`XLEN-1:0] PCNext1F, // Branch Predictor predicted or corrected fetch address on miss prediction
output logic [`XLEN-1:0] NextValidPCE, // Address of next valid instruction after the instruction in the Memory stage
// Update Predictor
input logic [`XLEN-1:0] PCF, // Fetch stage instruction address
input logic [`XLEN-1:0] PCD, // Decode stage instruction address. Also the address the branch predictor took
input logic [`XLEN-1:0] PCE, // Execution stage instruction address
input logic [`XLEN-1:0] PCM, // Memory stage instruction address
// Update Predictor
input logic [`XLEN-1:0] PCF, // Fetch stage instruction address
input logic [`XLEN-1:0] PCD, // Decode stage instruction address. Also the address the branch predictor took
input logic [`XLEN-1:0] PCE, // Execution stage instruction address
input logic [`XLEN-1:0] PCM, // Memory stage instruction address
input logic [31:0] PostSpillInstrRawF, // Instruction
input logic [31:0] PostSpillInstrRawF, // Instruction
// Branch and jump outcome
input logic PCSrcE, // Executation stage branch is taken
input logic [`XLEN-1:0] IEUAdrE, // The branch/jump target address
input logic [`XLEN-1:0] PCLinkE, // The address following the branch instruction. (AKA Fall through address)
output logic [3:0] InstrClassM, // The valid instruction class. 1-hot encoded as jalr, ret, jr (not ret), j, br
output logic JumpOrTakenBranchM, // The valid instruction class. 1-hot encoded as jalr, ret, jr (not ret), j, br
// Branch and jump outcome
input logic PCSrcE, // Executation stage branch is taken
input logic [`XLEN-1:0] IEUAdrE, // The branch/jump target address
input logic [`XLEN-1:0] PCLinkE, // The address following the branch instruction. (AKA Fall through address)
output logic [3:0] InstrClassM, // The valid instruction class. 1-hot encoded as jalr, ret, jr (not ret), j, br
output logic JumpOrTakenBranchM, // The valid instruction class. 1-hot encoded as jalr, ret, jr (not ret), j, br
// Report branch prediction status
output logic BPPredWrongE, // Prediction is wrong
output logic BPPredWrongM, // Prediction is wrong
output logic DirPredictionWrongM, // Prediction direction is wrong
output logic BTBPredPCWrongM, // Prediction target wrong
output logic RASPredPCWrongM, // RAS prediction is wrong
output logic PredictionInstrClassWrongM // Class prediction is wrong
);
// Report branch prediction status
output logic BPPredWrongE, // Prediction is wrong
output logic BPPredWrongM, // Prediction is wrong
output logic DirPredictionWrongM, // Prediction direction is wrong
output logic BTBPredPCWrongM, // Prediction target wrong
output logic RASPredPCWrongM, // RAS prediction is wrong
output logic PredictionInstrClassWrongM // Class prediction is wrong
);
logic PredValidF;
logic [1:0] DirPredictionF;
@ -97,34 +97,34 @@ module bpred (
// Part 1 branch direction prediction
// look into the 2 port Sram model. something is wrong.
if (`BPTYPE == "BPTWOBIT") begin:Predictor
if (`BPRED_TYPE == "BPTWOBIT") begin:Predictor
twoBitPredictor DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .FlushD, .FlushE, .FlushM,
.PCNextF, .PCM, .DirPredictionF, .DirPredictionWrongE,
.BranchInstrE(InstrClassE[0]), .BranchInstrM(InstrClassM[0]), .PCSrcE);
end else if (`BPTYPE == "BPGLOBAL") begin:Predictor
end else if (`BPRED_TYPE == "BPGLOBAL") begin:Predictor
globalhistory DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .FlushD, .FlushE, .FlushM,
.PCNextF, .PCM, .DirPredictionF, .DirPredictionWrongE,
.BranchInstrE(InstrClassE[0]), .BranchInstrM(InstrClassM[0]), .PCSrcE);
end else if (`BPTYPE == "BPSPECULATIVEGLOBAL") begin:Predictor
end else if (`BPRED_TYPE == "BPSPECULATIVEGLOBAL") begin:Predictor
speculativeglobalhistory #(10) DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW,
.PCNextF, .PCF, .PCD, .PCE, .PCM, .DirPredictionF, .DirPredictionWrongE,
.BranchInstrF(PredInstrClassF[0]), .BranchInstrD(InstrClassD[0]), .BranchInstrE(InstrClassE[0]), .BranchInstrM(InstrClassM[0]),
.BranchInstrW(InstrClassW[0]), .WrongPredInstrClassD, .PCSrcE);
end else if (`BPTYPE == "BPGSHARE") begin:Predictor
end else if (`BPRED_TYPE == "BPGSHARE") begin:Predictor
gshare DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .FlushD, .FlushE, .FlushM,
.PCNextF, .PCE, .DirPredictionF, .DirPredictionWrongE,
.BranchInstrE(InstrClassE[0]), .BranchInstrM(InstrClassM[0]), .PCSrcE);
end else if (`BPTYPE == "BPSPECULATIVEGSHARE") begin:Predictor
end else if (`BPRED_TYPE == "BPSPECULATIVEGSHARE") begin:Predictor
speculativegshare DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW,
.PCNextF, .PCF, .PCD, .PCE, .PCM, .DirPredictionF, .DirPredictionWrongE,
.BranchInstrF(PredInstrClassF[0]), .BranchInstrD(InstrClassD[0]), .BranchInstrE(InstrClassE[0]), .BranchInstrM(InstrClassM[0]),
.BranchInstrW(InstrClassW[0]), .WrongPredInstrClassD, .PCSrcE);
end else if (`BPTYPE == "BPLOCALPAg") begin:Predictor
end else if (`BPRED_TYPE == "BPLOCALPAg") begin:Predictor
// *** Fix me
/* -----\/----- EXCLUDED -----\/-----
localHistoryPredictor DirPredictor(.clk,

28
pipelined/src/ifu/brpred/btb.sv → pipelined/src/ifu/bpred/btb.sv
View File

@ -30,21 +30,19 @@
`include "wally-config.vh"
module btb
#(parameter int Depth = 10
)
(input logic clk,
input logic reset,
input logic StallF, StallD, StallM, FlushD, FlushM,
input logic [`XLEN-1:0] PCNextF, PCF, PCD, PCE, // PC at various stages
output logic [`XLEN-1:0] PredPCF, // BTB's guess at PC
output logic [3:0] BTBPredInstrClassF, // BTB's guess at instruction class
output logic PredValidF, // BTB's guess is valid
// update
input logic PredictionInstrClassWrongE, // BTB's instruction class guess was wrong
input logic [`XLEN-1:0] IEUAdrE, // Branch/jump target address to insert into btb
input logic [3:0] InstrClassE // Instruction class to insert into btb
);
module btb #(parameter int Depth = 10 ) (
input logic clk,
input logic reset,
input logic StallF, StallD, StallM, FlushD, FlushM,
input logic [`XLEN-1:0] PCNextF, PCF, PCD, PCE, // PC at various stages
output logic [`XLEN-1:0] PredPCF, // BTB's guess at PC
output logic [3:0] BTBPredInstrClassF, // BTB's guess at instruction class
output logic PredValidF, // BTB's guess is valid
// update
input logic PredictionInstrClassWrongE, // BTB's instruction class guess was wrong
input logic [`XLEN-1:0] IEUAdrE, // Branch/jump target address to insert into btb
input logic [3:0] InstrClassE // Instruction class to insert into btb
);
localparam TotalDepth = 2 ** Depth;
logic [TotalDepth-1:0] ValidBits;

31
pipelined/src/ifu/brpred/foldedgshare.sv → pipelined/src/ifu/bpred/foldedgshare.sv
View File

@ -28,22 +28,19 @@
`include "wally-config.vh"
module foldedgshare
#(parameter int k = 16,
parameter int depth = 10
)
(input logic clk,
input logic reset,
input logic StallF, StallD, StallE, StallM, StallW,
input logic FlushD, FlushE, FlushM, FlushW,
module foldedgshare #(parameter k = 16, depth = 10) (
input logic clk,
input logic reset,
input logic StallF, StallD, StallE, StallM, StallW,
input logic FlushD, FlushE, FlushM, FlushW,
// input logic [`XLEN-1:0] LookUpPC,
output logic [1:0] DirPredictionF,
output logic DirPredictionWrongE,
// update
input logic [`XLEN-1:0] PCNextF, PCF, PCD, PCE, PCM,
input logic BranchInstrF, BranchInstrD, BranchInstrE, BranchInstrM, BranchInstrW,
input logic PCSrcE
);
output logic [1:0] DirPredictionF,
output logic DirPredictionWrongE,
// update
input logic [`XLEN-1:0] PCNextF, PCF, PCD, PCE, PCM,
input logic BranchInstrF, BranchInstrD, BranchInstrE, BranchInstrM, BranchInstrW,
input logic PCSrcE
);
logic MatchF, MatchD, MatchE, MatchM, MatchW;
logic MatchNextX, MatchXF;
@ -57,13 +54,13 @@ module foldedgshare
logic [k:0] GHRNextD, GHRNextE, GHRNextM, GHRNextW;
logic [k-1:0] IndexNextF, IndexF;
logic [k-1:0] IndexD, IndexE, IndexM, IndexW;
logic [depth-1:0] FinalIndexNextF, FinalIndexW;
logic [depth-1:0] FinalIndexNextF, FinalIndexW;
logic PCSrcM, PCSrcW;
logic [`XLEN-1:0] PCW;
logic [1:0] ForwardNewDirPrediction, ForwardDirPredictionF;
localparam int delta = 2 * depth - k;
localparam delta = 2 * depth - k;
assign IndexNextF = GHRNextF ^ {PCNextF[k+1] ^ PCNextF[1], PCNextF[k:2]};
assign IndexF = GHRF ^ {PCF[k+1] ^ PCF[1], PCF[k:2]};

26
pipelined/src/ifu/brpred/globalhistory.sv → pipelined/src/ifu/bpred/globalhistory.sv
View File

@ -28,20 +28,18 @@
`include "wally-config.vh"
module globalhistory
#(parameter int k = 10
)
(input logic clk,
input logic reset,
input logic StallF, StallD, StallE, StallM,
input logic FlushD, FlushE, FlushM,
// input logic [`XLEN-1:0] LookUpPC,
output logic [1:0] DirPredictionF,
output logic DirPredictionWrongE,
// update
input logic [`XLEN-1:0] PCNextF, PCM,
input logic BranchInstrE, BranchInstrM, PCSrcE
);
module globalhistory #(parameter k = 10) (
input logic clk,
input logic reset,
input logic StallF, StallD, StallE, StallM,
input logic FlushD, FlushE, FlushM,
// input logic [`XLEN-1:0] LookUpPC,
output logic [1:0] DirPredictionF,
output logic DirPredictionWrongE,
// update
input logic [`XLEN-1:0] PCNextF, PCM,
input logic BranchInstrE, BranchInstrM, PCSrcE
);
logic [1:0] DirPredictionD, DirPredictionE;
logic [1:0] NewDirPredictionE, NewDirPredictionM;

25
pipelined/src/ifu/brpred/gshare.sv → pipelined/src/ifu/bpred/gshare.sv
View File

@ -28,20 +28,17 @@
`include "wally-config.vh"
module gshare
#(parameter int k = 10
)
(input logic clk,
input logic reset,
input logic StallF, StallD, StallE, StallM,
input logic FlushD, FlushE, FlushM,
// input logic [`XLEN-1:0] LookUpPC,
output logic [1:0] DirPredictionF,
output logic DirPredictionWrongE,
// update
input logic [`XLEN-1:0] PCNextF, PCE,
input logic BranchInstrE, BranchInstrM, PCSrcE
);
module gshare #(parameter k = 10) (
input logic clk,
input logic reset,
input logic StallF, StallD, StallE, StallM,
input logic FlushD, FlushE, FlushM,
output logic [1:0] DirPredictionF,
output logic DirPredictionWrongE,
// update
input logic [`XLEN-1:0] PCNextF, PCE,
input logic BranchInstrE, BranchInstrM, PCSrcE
);
logic [k-1:0] IndexNextF, IndexE;
logic [1:0] DirPredictionD, DirPredictionE;

29
pipelined/src/ifu/brpred/localHistoryPredictor.sv → pipelined/src/ifu/bpred/localHistoryPredictor.sv
View File

@ -28,23 +28,20 @@
`include "wally-config.vh"
module localHistoryPredictor
#( parameter int m = 6, // 2^m = number of local history branches
parameter int k = 10 // number of past branches stored
)
(input logic clk,
input logic reset,
input logic StallF, StallE,
input logic [`XLEN-1:0] LookUpPC,
output logic [1:0] Prediction,
// update
input logic [`XLEN-1:0] UpdatePC,
input logic UpdateEN, PCSrcE,
input logic [1:0] UpdatePrediction
);
module localHistoryPredictor #(parameter m = 6, // 2^m = number of local history branches
k = 10) ( // number of past branches stored
input logic clk,
input logic reset,
input logic StallF, StallE,
input logic [`XLEN-1:0] LookUpPC,
output logic [1:0] Prediction,
// update
input logic [`XLEN-1:0] UpdatePC,
input logic UpdateEN, PCSrcE,
input logic [1:0] UpdatePrediction
);
logic [2**m-1:0] [k-1:0] LHRNextF;
logic [2**m-1:0][k-1:0] LHRNextF;
logic [k-1:0] LHRF, ForwardLHRNext, LHRFNext;
logic [m-1:0] LookUpPCIndex, UpdatePCIndex;
logic [1:0] PredictionMemory;

26
pipelined/src/ifu/brpred/optgshare.sv → pipelined/src/ifu/bpred/optgshare.sv
View File

@ -28,21 +28,19 @@
`include "wally-config.vh"
module optgshare
#(parameter int k = 10
)
(input logic clk,
input logic reset,
input logic StallF, StallD, StallE, StallM, StallW,
input logic FlushD, FlushE, FlushM, FlushW,
module optgshare #(parameter k = 10) (
input logic clk,
input logic reset,
input logic StallF, StallD, StallE, StallM, StallW,
input logic FlushD, FlushE, FlushM, FlushW,
// input logic [`XLEN-1:0] LookUpPC,
output logic [1:0] DirPredictionF,
output logic DirPredictionWrongE,
// update
input logic [`XLEN-1:0] PCNextF, PCF, PCD, PCE, PCM,
input logic BranchInstrF, BranchInstrD, BranchInstrE, BranchInstrM, BranchInstrW,
input logic PCSrcE
);
output logic [1:0] DirPredictionF,
output logic DirPredictionWrongE,
// update
input logic [`XLEN-1:0] PCNextF, PCF, PCD, PCE, PCM,
input logic BranchInstrF, BranchInstrD, BranchInstrE, BranchInstrM, BranchInstrW,
input logic PCSrcE
);
logic MatchF, MatchD, MatchE, MatchM, MatchW;
logic MatchNextX, MatchXF;

0
pipelined/src/ifu/brpred/satCounter2.sv → pipelined/src/ifu/bpred/satCounter2.sv
View File

29
pipelined/src/ifu/brpred/speculativeglobalhistory.sv → pipelined/src/ifu/bpred/speculativeglobalhistory.sv
View File

@ -28,22 +28,19 @@
`include "wally-config.vh"
module speculativeglobalhistory
#(parameter int k = 10
)
(input logic clk,
input logic reset,
input logic StallF, StallD, StallE, StallM, StallW,
input logic FlushD, FlushE, FlushM, FlushW,
// input logic [`XLEN-1:0] LookUpPC,
output logic [1:0] DirPredictionF,
output logic DirPredictionWrongE,
// update
input logic [`XLEN-1:0] PCNextF, PCF, PCD, PCE, PCM,
input logic BranchInstrF, BranchInstrD, BranchInstrE, BranchInstrM, BranchInstrW,
input logic [3:0] WrongPredInstrClassD,
input logic PCSrcE
);
module speculativeglobalhistory #(parameter k = 10) (
input logic clk,
input logic reset,
input logic StallF, StallD, StallE, StallM, StallW,
input logic FlushD, FlushE, FlushM, FlushW,
output logic [1:0] DirPredictionF,
output logic DirPredictionWrongE,
// update
input logic [`XLEN-1:0] PCNextF, PCF, PCD, PCE, PCM,
input logic BranchInstrF, BranchInstrD, BranchInstrE, BranchInstrM, BranchInstrW,
input logic [3:0] WrongPredInstrClassD,
input logic PCSrcE
);
logic MatchF, MatchD, MatchE;
logic MatchNextX, MatchXF;

28
pipelined/src/ifu/brpred/speculativegshare.sv → pipelined/src/ifu/bpred/speculativegshare.sv
View File

@ -28,21 +28,19 @@
`include "wally-config.vh"
module speculativegshare
#(parameter int k = 10
)
(input logic clk,
input logic reset,
input logic StallF, StallD, StallE, StallM, StallW,
input logic FlushD, FlushE, FlushM, FlushW,
output logic [1:0] DirPredictionF,
output logic DirPredictionWrongE,
// update
input logic [`XLEN-1:0] PCNextF, PCF, PCD, PCE, PCM,
input logic BranchInstrF, BranchInstrD, BranchInstrE, BranchInstrM, BranchInstrW,
input logic [3:0] WrongPredInstrClassD,
input logic PCSrcE
);
module speculativegshare #(parameter int k = 10 ) (
input logic clk,
input logic reset,
input logic StallF, StallD, StallE, StallM, StallW,
input logic FlushD, FlushE, FlushM, FlushW,
output logic [1:0] DirPredictionF,
output logic DirPredictionWrongE,
// update
input logic [`XLEN-1:0] PCNextF, PCF, PCD, PCE, PCM,
input logic BranchInstrF, BranchInstrD, BranchInstrE, BranchInstrM, BranchInstrW,
input logic [3:0] WrongPredInstrClassD,
input logic PCSrcE
);
logic MatchF, MatchD, MatchE;
logic MatchNextX, MatchXF;

24
pipelined/src/ifu/brpred/twoBitPredictor.sv → pipelined/src/ifu/bpred/twoBitPredictor.sv
View File

@ -28,19 +28,17 @@
`include "wally-config.vh"
module twoBitPredictor
#(parameter int k = 10
)
(input logic clk,
input logic reset,
input logic StallF, StallD, StallE, StallM,
input logic FlushD, FlushE, FlushM,
input logic [`XLEN-1:0] PCNextF, PCM,
output logic [1:0] DirPredictionF,
output logic DirPredictionWrongE,
input logic BranchInstrE, BranchInstrM,
input logic PCSrcE
);
module twoBitPredictor #(parameter k = 10) (
input logic clk,
input logic reset,
input logic StallF, StallD, StallE, StallM,
input logic FlushD, FlushE, FlushM,
input logic [`XLEN-1:0] PCNextF, PCM,
output logic [1:0] DirPredictionF,
output logic DirPredictionWrongE,
input logic BranchInstrE, BranchInstrM,
input logic PCSrcE
);
logic [k-1:0] IndexNextF, IndexM;
logic [1:0] PredictionMemory;

16
pipelined/src/ifu/ifu.sv
View File

@ -136,7 +136,7 @@ module ifu (
/////////////////////////////////////////////////////////////////////////////////////////////
if(`C_SUPPORTED) begin : Spill
spill #(`ICACHE) spill(.clk, .reset, .StallD, .FlushD, .PCF, .PCPlus4F, .PCNextF, .InstrRawF,
spill #(`ICACHE_SUPPORTED) spill(.clk, .reset, .StallD, .FlushD, .PCF, .PCPlus4F, .PCNextF, .InstrRawF,
.InstrDAPageFaultF, .IFUCacheBusStallD, .ITLBMissF, .PCNextFSpill, .PCFSpill, .SelNextSpillF, .PostSpillInstrRawF, .CompressedF);
end else begin : NoSpill
assign PCNextFSpill = PCNextF;
@ -210,13 +210,13 @@ module ifu (
end else begin
assign IFURWF = 2'b10;
end
if (`BUS) begin : bus
if (`BUS_SUPPORTED) begin : bus
// **** must fix words per line vs beats per line as in lsu.
localparam integer WORDSPERLINE = `ICACHE ? `ICACHE_LINELENINBITS/`XLEN : 1;
localparam integer LOGBWPL = `ICACHE ? $clog2(WORDSPERLINE) : 1;
if(`ICACHE) begin : icache
localparam integer LINELEN = `ICACHE ? `ICACHE_LINELENINBITS : `XLEN;
localparam integer LLENPOVERAHBW = `LLEN / `AHBW; // Number of AHB beats in a LLEN word. AHBW cannot be larger than LLEN. (implementation limitation)
localparam WORDSPERLINE = `ICACHE_SUPPORTED ? `ICACHE_LINELENINBITS/`XLEN : 1;
localparam LOGBWPL = `ICACHE_SUPPORTED ? $clog2(WORDSPERLINE) : 1;
if(`ICACHE_SUPPORTED) begin : icache
localparam LINELEN = `ICACHE_SUPPORTED ? `ICACHE_LINELENINBITS : `XLEN;
localparam LLENPOVERAHBW = `LLEN / `AHBW; // Number of AHB beats in a LLEN word. AHBW cannot be larger than LLEN. (implementation limitation)
logic [LINELEN-1:0] FetchBuffer;
logic [`PA_BITS-1:0] ICacheBusAdr;
logic ICacheBusAck;
@ -324,7 +324,7 @@ module ifu (
////////////////////////////////////////////////////////////////////////////////////////////////
// Branch and Jump Predictor
////////////////////////////////////////////////////////////////////////////////////////////////
if (`BPRED_ENABLED) begin : bpred
if (`BPRED_SUPPORTED) begin : bpred
bpred bpred(.clk, .reset,
.StallF, .StallD, .StallE, .StallM, .StallW,
.FlushD, .FlushE, .FlushM, .FlushW,

8
pipelined/src/ifu/spill.sv
View File

@ -50,15 +50,15 @@ module spill #(
output logic CompressedF); // The fetched instruction is compressed
// Spill threshold occurs when all the cache offset PC bits are 1 (except [0]). Without a cache this is just PCF[1]
localparam integer SPILLTHRESHOLD = CACHE_ENABLED ? `ICACHE_LINELENINBITS/32 : 1;
typedef enum logic [1:0] {STATE_READY, STATE_SPILL} statetype;
statetype CurrState, NextState;
localparam SPILLTHRESHOLD = CACHE_ENABLED ? `ICACHE_LINELENINBITS/32 : 1;
logic [`XLEN-1:0] PCPlus2F;
logic TakeSpillF;
logic SpillF;
logic SelSpillF;
logic SpillSaveF;
logic SpillSaveF;
logic [15:0] InstrFirstHalf;
typedef enum logic [1:0] {STATE_READY, STATE_SPILL} statetype;
statetype CurrState, NextState;
////////////////////////////////////////////////////////////////////////////////////////////////////
// PC logic

22
pipelined/src/lsu/lsu.sv
View File

@ -206,7 +206,7 @@ module lsu (
assign {LoadPageFaultM, StoreAmoPageFaultM} = '0;
assign PAdrM = IHAdrM[`PA_BITS-1:0];
assign CacheableM = 1'b1;
assign SelDTIM = `DTIM_SUPPORTED & ~`BUS; // if no PMA then select dtim if there is a DTIM. If there is
assign SelDTIM = `DTIM_SUPPORTED & ~`BUS_SUPPORTED; // if no PMA then select dtim if there is a DTIM. If there is
// a bus then this is always 0. Cannot have both without PMA.
end
@ -236,14 +236,14 @@ module lsu (
.ReadDataWordM(DTIMReadDataWordM[`XLEN-1:0]), .ByteMaskM(ByteMaskM[`XLEN/8-1:0]));
end else begin
end
if (`BUS) begin : bus
if(`DCACHE) begin : dcache
localparam integer LLENWORDSPERLINE = `DCACHE_LINELENINBITS/`LLEN; // Number of LLEN words in cacheline
localparam integer LLENLOGBWPL = $clog2(LLENWORDSPERLINE); // Log2 of ^
localparam integer BEATSPERLINE = `DCACHE_LINELENINBITS/`AHBW; // Number of AHBW words (beats) in cacheline
localparam integer AHBWLOGBWPL = $clog2(BEATSPERLINE); // Log2 of ^
localparam integer LINELEN = `DCACHE_LINELENINBITS; // Number of bits in cacheline
localparam integer LLENPOVERAHBW = `LLEN / `AHBW; // Number of AHB beats in a LLEN word. AHBW cannot be larger than LLEN. (implementation limitation)
if (`BUS_SUPPORTED) begin : bus
if(`DCACHE_SUPPORTED) begin : dcache
localparam LLENWORDSPERLINE = `DCACHE_LINELENINBITS/`LLEN; // Number of LLEN words in cacheline
localparam LLENLOGBWPL = $clog2(LLENWORDSPERLINE); // Log2 of ^
localparam BEATSPERLINE = `DCACHE_LINELENINBITS/`AHBW; // Number of AHBW words (beats) in cacheline
localparam AHBWLOGBWPL = $clog2(BEATSPERLINE); // Log2 of ^
localparam LINELEN = `DCACHE_LINELENINBITS; // Number of bits in cacheline
localparam LLENPOVERAHBW = `LLEN / `AHBW; // Number of AHB beats in a LLEN word. AHBW cannot be larger than LLEN. (implementation limitation)
logic [LINELEN-1:0] FetchBuffer; // Temporary buffer to hold partially fetched cacheline
logic [`PA_BITS-1:0] DCacheBusAdr; // Cacheline address to fetch or writeback.
@ -251,10 +251,10 @@ module lsu (
logic DCacheBusAck; // ahbcacheinterface completed fetch or writeback
logic SelBusBeat; // ahbcacheinterface selects postion in cacheline with BeatCount
logic [1:0] CacheBusRW; // Cache sends request to ahbcacheinterface
logic [1:0] BusRW; // Uncached bus memory access
logic [1:0] BusRW; // Uncached bus memory access
logic CacheableOrFlushCacheM; // Memory address is cacheable or operation is a cache flush
logic [1:0] CacheRWM; // Cache read (10), write (01), AMO (11)
logic [1:0] CacheAtomicM; // Cache AMO
logic [1:0] CacheAtomicM; // Cache AMO
assign BusRW = ~CacheableM & ~IgnoreRequestTLB & ~SelDTIM ? LSURWM : '0;
assign CacheableOrFlushCacheM = CacheableM | FlushDCacheM;

216
pipelined/src/wally/cvw.sv Normal file
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@ -0,0 +1,216 @@
//////////////////////////////////////////
// cvw.sv
//
// Written: David_Harris@hmc.edu 27 January 2022
//
// Purpose: package with shared CORE-V-Wally global parameters
//
// A component of the Wally configurable RISC-V project.
//
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
//
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
//
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
// may obtain a copy of the License at
//
// https://solderpad.org/licenses/SHL-2.1/
//
// Unless required by applicable law or agreed to in writing, any work distributed under the
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
// either express or implied. See the License for the specific language governing permissions
// and limitations under the License.
////////////////////////////////////////////////////////////////////////////////////////////////
// Usiing global `define statements isn't ideal in a large SystemVerilog system because
// of the risk of `define name conflicts across different subsystems.
// Instead, CORE-V-Wally loads the appropriate configuration one time and places it in a package
// that is referenced by all Wally modules but not by other subsystems.
// Load configuration-specific information
`include "wally-config.vh"
// Place configuration in a package
package cvw;
parameter XLEN = `XLEN;
parameter FPGA = `FPGA;
parameter QEMU = `QEMU;
parameter IEEE754 = `IEEE754;
parameter MISA = `MISA;
parameter ZICSR_SUPPORTED = `ZICSR_SUPPORTED;
parameter ZIFENCEI_SUPPORTED = `ZIFENCEI_SUPPORTED;
parameter COUNTERS = `COUNTERS;
parameter ZICOUNTERS_SUPPORTED = `ZICOUNTERS_SUPPORTED;
parameter ZFH_SUPPORTED = `ZFH_SUPPORTED;
parameter BUS_SUPPORTED = `BUS_SUPPORTED;
parameter DCACHE_SUPPORTED = `DCACHE_SUPPORTED;
parameter ICACHE_SUPPORTED = `ICACHE_SUPPORTED;
parameter VIRTMEM_SUPPORTED = `VIRTMEM_SUPPORTED;
parameter VECTORED_INTERRUPTS_SUPPORTED = `VECTORED_INTERRUPTS_SUPPORTED;
parameter BIGENDIAN_SUPPORTED = `BIGENDIAN_SUPPORTED;
parameter ITLB_ENTRIES = `ITLB_ENTRIES;
parameter DTLB_ENTRIES = `DTLB_ENTRIES;
parameter DCACHE_NUMWAYS = `DCACHE_NUMWAYS;
parameter DCACHE_WAYSIZEINBYTES = `DCACHE_WAYSIZEINBYTES;
parameter DCACHE_LINELENINBITS = `DCACHE_LINELENINBITS;
parameter ICACHE_NUMWAYS = `ICACHE_NUMWAYS;
parameter ICACHE_WAYSIZEINBYTES = `ICACHE_WAYSIZEINBYTES;
parameter ICACHE_LINELENINBITS = `ICACHE_LINELENINBITS;
parameter IDIV_BITSPERCYCLE = `IDIV_BITSPERCYCLE;
parameter IDIV_ON_FPU = `IDIV_ON_FPU;
parameter PMP_ENTRIES = `PMP_ENTRIES;
parameter RESET_VECTOR = `RESET_VECTOR;
parameter WFI_TIMEOUT_BIT = `WFI_TIMEOUT_BIT;
parameter DTIM_SUPPORTED = `DTIM_SUPPORTED;
parameter DTIM_BASE = `DTIM_BASE;
parameter DTIM_RANGE = `DTIM_RANGE;
parameter IROM_SUPPORTED = `IROM_SUPPORTED;
parameter IROM_BASE = `IROM_BASE;
parameter IROM_RANGE = `IROM_RANGE;
parameter BOOTROM_SUPPORTED = `BOOTROM_SUPPORTED;
parameter BOOTROM_BASE = `BOOTROM_BASE;
parameter BOOTROM_RANGE = `BOOTROM_RANGE;
parameter UNCORE_RAM_SUPPORTED = `UNCORE_RAM_SUPPORTED;
parameter UNCORE_RAM_BASE = `UNCORE_RAM_BASE;
parameter UNCORE_RAM_RANGE = `UNCORE_RAM_RANGE;
parameter EXT_MEM_SUPPORTED = `EXT_MEM_SUPPORTED;
parameter EXT_MEM_BASE = `EXT_MEM_BASE;
parameter EXT_MEM_RANGE = `EXT_MEM_RANGE;
parameter CLINT_SUPPORTED = `CLINT_SUPPORTED;
parameter CLINT_BASE = `CLINT_BASE;
parameter CLINT_RANGE = `CLINT_RANGE;
parameter GPIO_SUPPORTED = `GPIO_SUPPORTED;
parameter GPIO_BASE = `GPIO_BASE;
parameter GPIO_RANGE = `GPIO_RANGE;
parameter UART_SUPPORTED = `UART_SUPPORTED;
parameter UART_BASE = `UART_BASE;
parameter UART_RANGE = `UART_RANGE;
parameter PLIC_SUPPORTED = `PLIC_SUPPORTED;
parameter PLIC_BASE = `PLIC_BASE;
parameter PLIC_RANGE = `PLIC_RANGE;
parameter SDC_SUPPORTED = `SDC_SUPPORTED;
parameter SDC_BASE = `SDC_BASE;
parameter SDC_RANGE = `SDC_RANGE;
parameter AHBW = `AHBW;
parameter GPIO_LOOPBACK_TEST = `GPIO_LOOPBACK_TEST;
parameter UART_PRESCALE = `UART_PRESCALE;
parameter PLIC_NUM_SRC = `PLIC_NUM_SRC;
parameter PLIC_GPIO_ID = `PLIC_GPIO_ID;
parameter PLIC_UART_ID = `PLIC_UART_ID;
parameter BPRED_SUPPORTED = `BPRED_SUPPORTED;
parameter BPRED_TYPE = `BPRED_TYPE;
parameter TESTSBP = `TESTSBP;
parameter BPRED_SIZE = `BPRED_SIZE;
parameter HPTW_WRITES_SUPPORTED = `HPTW_WRITES_SUPPORTED;
// parameter = `;
// Shared parameters
// constants defining different privilege modes
// defined in Table 1.1 of the privileged spec
parameter M_MODE = (2'b11);
parameter S_MODE = (2'b01);
parameter U_MODE = (2'b00);
// Virtual Memory Constants
parameter VPN_SEGMENT_BITS = (`XLEN == 32 ? 10 : 9);
parameter VPN_BITS = (`XLEN==32 ? (2*`VPN_SEGMENT_BITS) : (4*`VPN_SEGMENT_BITS));
parameter PPN_BITS = (`XLEN==32 ? 22 : 44);
parameter PA_BITS = (`XLEN==32 ? 34 : 56);
parameter SVMODE_BITS = (`XLEN==32 ? 1 : 4);
parameter ASID_BASE = (`XLEN==32 ? 22 : 44);
parameter ASID_BITS = (`XLEN==32 ? 9 : 16);
// constants to check SATP_MODE against
// defined in Table 4.3 of the privileged spec
parameter NO_TRANSLATE = 0;
parameter SV32 = 1;
parameter SV39 = 8;
parameter SV48 = 9;
// macros to define supported modes
parameter A_SUPPORTED = ((`MISA >> 0) % 2 == 1);
parameter B_SUPPORTED = ((`ZBA_SUPPORTED | `ZBB_SUPPORTED | `ZBC_SUPPORTED | `ZBS_SUPPORTED)); // not based on MISA
parameter C_SUPPORTED = ((`MISA >> 2) % 2 == 1);
parameter D_SUPPORTED = ((`MISA >> 3) % 2 == 1);
parameter E_SUPPORTED = ((`MISA >> 4) % 2 == 1);
parameter F_SUPPORTED = ((`MISA >> 5) % 2 == 1);
parameter I_SUPPORTED = ((`MISA >> 8) % 2 == 1);
parameter M_SUPPORTED = ((`MISA >> 12) % 2 == 1);
parameter Q_SUPPORTED = ((`MISA >> 16) % 2 == 1);
parameter S_SUPPORTED = ((`MISA >> 18) % 2 == 1);
parameter U_SUPPORTED = ((`MISA >> 20) % 2 == 1);
// N-mode user-level interrupts are depricated per Andrew Waterman 1/13/21
// logarithm of XLEN, used for number of index bits to select
parameter LOG_XLEN = (`XLEN == 32 ? 5 : 6);
// Number of 64 bit PMP Configuration Register entries (or pairs of 32 bit entries)
parameter PMPCFG_ENTRIES = (`PMP_ENTRIES/8);
// Floating point constants for Quad, Double, Single, and Half precisions
parameter Q_LEN = 32'd128;
parameter Q_NE = 32'd15;
parameter Q_NF = 32'd112;
parameter Q_BIAS = 32'd16383;
parameter Q_FMT = 2'd3;
parameter D_LEN = 32'd64;
parameter D_NE = 32'd11;
parameter D_NF = 32'd52;
parameter D_BIAS = 32'd1023;
parameter D_FMT = 2'd1;
parameter S_LEN = 32'd32;
parameter S_NE = 32'd8;
parameter S_NF = 32'd23;
parameter S_BIAS = 32'd127;
parameter S_FMT = 2'd0;
parameter H_LEN = 32'd16;
parameter H_NE = 32'd5;
parameter H_NF = 32'd10;
parameter H_BIAS = 32'd15;
parameter H_FMT = 2'd2;
// Floating point length FLEN and number of exponent (NE) and fraction (NF) bits
parameter FLEN = (`Q_SUPPORTED ? `Q_LEN : `D_SUPPORTED ? `D_LEN : `S_LEN);
parameter NE = (`Q_SUPPORTED ? `Q_NE : `D_SUPPORTED ? `D_NE : `S_NE);
parameter NF = (`Q_SUPPORTED ? `Q_NF : `D_SUPPORTED ? `D_NF : `S_NF);
parameter FMT = (`Q_SUPPORTED ? 2'd3 : `D_SUPPORTED ? 2'd1 : 2'd0);
parameter BIAS = (`Q_SUPPORTED ? `Q_BIAS : `D_SUPPORTED ? `D_BIAS : `S_BIAS);
// Floating point constants needed for FPU paramerterization
parameter FPSIZES = ((32)'(`Q_SUPPORTED)+(32)'(`D_SUPPORTED)+(32)'(`F_SUPPORTED)+(32)'(`ZFH_SUPPORTED));
parameter FMTBITS = ((32)'(`FPSIZES>=3)+1);
parameter LEN1 = ((`D_SUPPORTED & (`FLEN != `D_LEN)) ? `D_LEN : (`F_SUPPORTED & (`FLEN != `S_LEN)) ? `S_LEN : `H_LEN);
parameter NE1 = ((`D_SUPPORTED & (`FLEN != `D_LEN)) ? `D_NE : (`F_SUPPORTED & (`FLEN != `S_LEN)) ? `S_NE : `H_NE);
parameter NF1 = ((`D_SUPPORTED & (`FLEN != `D_LEN)) ? `D_NF : (`F_SUPPORTED & (`FLEN != `S_LEN)) ? `S_NF : `H_NF);
parameter FMT1 = ((`D_SUPPORTED & (`FLEN != `D_LEN)) ? 2'd1 : (`F_SUPPORTED & (`FLEN != `S_LEN)) ? 2'd0 : 2'd2);
parameter BIAS1 = ((`D_SUPPORTED & (`FLEN != `D_LEN)) ? `D_BIAS : (`F_SUPPORTED & (`FLEN != `S_LEN)) ? `S_BIAS : `H_BIAS);
parameter LEN2 = ((`F_SUPPORTED & (`LEN1 != `S_LEN)) ? `S_LEN : `H_LEN);
parameter NE2 = ((`F_SUPPORTED & (`LEN1 != `S_LEN)) ? `S_NE : `H_NE);
parameter NF2 = ((`F_SUPPORTED & (`LEN1 != `S_LEN)) ? `S_NF : `H_NF);
parameter FMT2 = ((`F_SUPPORTED & (`LEN1 != `S_LEN)) ? 2'd0 : 2'd2);
parameter BIAS2 = ((`F_SUPPORTED & (`LEN1 != `S_LEN)) ? `S_BIAS : `H_BIAS);
// largest length in IEU/FPU
parameter CVTLEN = ((`NF<`XLEN) ? (`XLEN) : (`NF));
parameter LLEN = ((`FLEN<`XLEN) ? (`XLEN) : (`FLEN));
parameter LOGCVTLEN = $unsigned($clog2(`CVTLEN+1));
parameter NORMSHIFTSZ = (((`CVTLEN+`NF+1)>(`DIVb + 1 +`NF+1) & (`CVTLEN+`NF+1)>(3*`NF+6)) ? (`CVTLEN+`NF+1) : ((`DIVb + 1 +`NF+1) > (3*`NF+6) ? (`DIVb + 1 +`NF+1) : (3*`NF+6)));
parameter LOGNORMSHIFTSZ = ($clog2(`NORMSHIFTSZ));
parameter CORRSHIFTSZ = (((`CVTLEN+`NF+1)>(`DIVb + 1 +`NF+1) & (`CVTLEN+`NF+1)>(3*`NF+6)) ? (`CVTLEN+`NF+1) : ((`DIVN+1+`NF) > (3*`NF+4) ? (`DIVN+1+`NF) : (3*`NF+4)));
// division constants
parameter DIVN = (((`NF<`XLEN) & `IDIV_ON_FPU) ? `XLEN : `NF+2); // standard length of input
parameter LOGR = ($clog2(`RADIX)); // r = log(R)
parameter RK = (`LOGR*`DIVCOPIES); // r*k used for intdiv preproc
parameter LOGRK = ($clog2(`RK)); // log2(r*k)
parameter FPDUR = ((`DIVN+1+(`LOGR*`DIVCOPIES))/(`LOGR*`DIVCOPIES)+(`RADIX/4));
parameter DURLEN = ($clog2(`FPDUR+1));
parameter DIVb = (`FPDUR*`LOGR*`DIVCOPIES-1); // canonical fdiv size (b)
parameter DIVBLEN = ($clog2(`DIVb+1)-1);
parameter DIVa = (`DIVb+1-`XLEN); // used for idiv on fpu
endpackage

83
pipelined/src/wally/wallypipelinedcore.sv
View File

@ -26,8 +26,7 @@
// and limitations under the License.
////////////////////////////////////////////////////////////////////////////////////////////////
`include "wally-config.vh"
/* verilator lint_on UNUSED */
import cvw::*; // global CORE-V-Wally parameters
module wallypipelinedcore (
input logic clk, reset,
@ -35,12 +34,12 @@ module wallypipelinedcore (
input logic MTimerInt, MExtInt, SExtInt, MSwInt,
input logic [63:0] MTIME_CLINT,
// Bus Interface
input logic [`AHBW-1:0] HRDATA,
input logic [AHBW-1:0] HRDATA,
input logic HREADY, HRESP,
output logic HCLK, HRESETn,
output logic [`PA_BITS-1:0] HADDR,
output logic [`AHBW-1:0] HWDATA,
output logic [`XLEN/8-1:0] HWSTRB,
output logic [PA_BITS-1:0] HADDR,
output logic [AHBW-1:0] HWDATA,
output logic [XLEN/8-1:0] HWSTRB,
output logic HWRITE,
output logic [2:0] HSIZE,
output logic [2:0] HBURST,
@ -58,15 +57,15 @@ module wallypipelinedcore (
logic IntDivE, W64E;
logic CSRReadM, CSRWriteM, PrivilegedM;
logic [1:0] AtomicM;
logic [`XLEN-1:0] ForwardedSrcAE, ForwardedSrcBE;
logic [`XLEN-1:0] SrcAM;
logic [XLEN-1:0] ForwardedSrcAE, ForwardedSrcBE;
logic [XLEN-1:0] SrcAM;
logic [2:0] Funct3E;
logic [31:0] InstrD;
logic [31:0] InstrM;
logic [`XLEN-1:0] PCF, PCE, PCLinkE;
logic [`XLEN-1:0] PCM;
logic [`XLEN-1:0] CSRReadValW, MDUResultW;
logic [`XLEN-1:0] UnalignedPCNextF, PCNext2F;
logic [XLEN-1:0] PCF, PCE, PCLinkE;
logic [XLEN-1:0] PCM;
logic [XLEN-1:0] CSRReadValW, MDUResultW;
logic [XLEN-1:0] UnalignedPCNextF, PCNext2F;
logic [1:0] MemRWM;
logic InstrValidM;
logic InstrMisalignedFaultM;
@ -86,9 +85,9 @@ module wallypipelinedcore (
logic [4:0] RdE, RdM, RdW;
logic FPUStallD;
logic FWriteIntE;
logic [`FLEN-1:0] FWriteDataM;
logic [`XLEN-1:0] FIntResM;
logic [`XLEN-1:0] FCvtIntResW;
logic [FLEN-1:0] FWriteDataM;
logic [XLEN-1:0] FIntResM;
logic [XLEN-1:0] FCvtIntResW;
logic FCvtIntW;
logic FDivBusyE;
logic IllegalFPUInstrM;
@ -96,23 +95,23 @@ module wallypipelinedcore (
logic FCvtIntStallD;
logic FpLoadStoreM;
logic [4:0] SetFflagsM;
logic [`XLEN-1:0] FIntDivResultW;
logic [XLEN-1:0] FIntDivResultW;
// memory management unit signals
logic ITLBWriteF;
logic ITLBMissF;
logic [`XLEN-1:0] SATP_REGW;
logic [XLEN-1:0] SATP_REGW;
logic STATUS_MXR, STATUS_SUM, STATUS_MPRV;
logic [1:0] STATUS_MPP, STATUS_FS;
logic [1:0] PrivilegeModeW;
logic [`XLEN-1:0] PTE;
logic [XLEN-1:0] PTE;
logic [1:0] PageType;
logic sfencevmaM, WFIStallM;
logic SelHPTW;
// PMA checker signals
var logic [`XLEN-1:0] PMPADDR_ARRAY_REGW [`PMP_ENTRIES-1:0];
var logic [7:0] PMPCFG_ARRAY_REGW[`PMP_ENTRIES-1:0];
var logic [XLEN-1:0] PMPADDR_ARRAY_REGW[PMP_ENTRIES-1:0];
var logic [7:0] PMPCFG_ARRAY_REGW[PMP_ENTRIES-1:0];
// IMem stalls
logic IFUStallF;
@ -120,14 +119,14 @@ module wallypipelinedcore (
// cpu lsu interface
logic [2:0] Funct3M;
logic [`XLEN-1:0] IEUAdrE;
logic [`XLEN-1:0] WriteDataM;
logic [`XLEN-1:0] IEUAdrM;
logic [`LLEN-1:0] ReadDataW;
logic [XLEN-1:0] IEUAdrE;
logic [XLEN-1:0] WriteDataM;
logic [XLEN-1:0] IEUAdrM;
logic [LLEN-1:0] ReadDataW;
logic CommittedM;
// AHB ifu interface
logic [`PA_BITS-1:0] IFUHADDR;
logic [PA_BITS-1:0] IFUHADDR;
logic [2:0] IFUHBURST;
logic [1:0] IFUHTRANS;
logic [2:0] IFUHSIZE;
@ -135,9 +134,9 @@ module wallypipelinedcore (
logic IFUHREADY;
// AHB LSU interface
logic [`PA_BITS-1:0] LSUHADDR;
logic [`XLEN-1:0] LSUHWDATA;
logic [`XLEN/8-1:0] LSUHWSTRB;
logic [PA_BITS-1:0] LSUHADDR;
logic [XLEN-1:0] LSUHWDATA;
logic [XLEN/8-1:0] LSUHWSTRB;
logic LSUHWRITE;
logic LSUHREADY;
@ -163,10 +162,6 @@ module wallypipelinedcore (
logic CommittedF;
logic JumpOrTakenBranchM;
// Bit manipulation unit
logic [`XLEN-1:0] BMUResultE; // Bit manipuation result BMU -> IEU
logic BMUE; // is this a BMU instruction
// instruction fetch unit: PC, branch prediction, instruction cache
ifu ifu(.clk, .reset,
.StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW,
@ -194,7 +189,7 @@ module wallypipelinedcore (
.InstrD, .IllegalIEUInstrFaultD, .IllegalBaseInstrFaultD,
// Execute Stage interface
.PCE, .PCLinkE, .FWriteIntE, .FCvtIntE, .IEUAdrE, .IntDivE, .W64E,
.Funct3E, .ForwardedSrcAE, .ForwardedSrcBE, .BMUE,
.Funct3E, .ForwardedSrcAE, .ForwardedSrcBE,
// Memory stage interface
.SquashSCW, // from LSU
.MemRWM, // read/write control goes to LSU
@ -204,7 +199,7 @@ module wallypipelinedcore (
.SrcAM, // to privilege and fpu
.RdE, .RdM, .FIntResM, .InvalidateICacheM, .FlushDCacheM,
// Writeback stage
.CSRReadValW, .MDUResultW, .BMUResultE, .FIntDivResultW, .RdW, .ReadDataW(ReadDataW[`XLEN-1:0]),
.CSRReadValW, .MDUResultW, .FIntDivResultW, .RdW, .ReadDataW(ReadDataW[XLEN-1:0]),
.InstrValidM, .FCvtIntResW, .FCvtIntW,
// hazards
.StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW,
@ -243,7 +238,7 @@ module wallypipelinedcore (
.PCF, .ITLBMissF, .PTE, .PageType, .ITLBWriteF, .SelHPTW,
.LSUStallM);
if(`BUS) begin : ebu
if(BUS_SUPPORTED) begin : ebu
ebu ebu(// IFU connections
.clk, .reset,
// IFU interface
@ -281,7 +276,7 @@ module wallypipelinedcore (
.FlushD, .FlushE, .FlushM, .FlushW);
// privileged unit
if (`ZICSR_SUPPORTED) begin:priv
if (ZICSR_SUPPORTED) begin:priv
privileged priv(
.clk, .reset,
.FlushD, .FlushE, .FlushM, .FlushW, .StallD, .StallE, .StallM, .StallW,
@ -314,7 +309,7 @@ module wallypipelinedcore (
end
// multiply/divide unit
if (`M_SUPPORTED) begin:mdu
if (M_SUPPORTED) begin:mdu
mdu mdu(.clk, .reset, .StallM, .StallW, .FlushE, .FlushM, .FlushW,
.ForwardedSrcAE, .ForwardedSrcBE,
.Funct3E, .Funct3M, .IntDivE, .W64E,
@ -325,12 +320,12 @@ module wallypipelinedcore (
end
// floating point unit
if (`F_SUPPORTED) begin:fpu
if (F_SUPPORTED) begin:fpu
fpu fpu(
.clk, .reset,
.FRM_REGW, // Rounding mode from CSR
.InstrD, // instruction from IFU
.ReadDataW(ReadDataW[`FLEN-1:0]),// Read data from memory
.ReadDataW(ReadDataW[FLEN-1:0]),// Read data from memory
.ForwardedSrcAE, // Integer input being processed (from IEU)
.StallE, .StallM, .StallW, // stall signals from HZU
.FlushE, .FlushM, .FlushW, // flush signals from HZU
@ -361,15 +356,5 @@ module wallypipelinedcore (
assign SetFflagsM = 0;
assign FpLoadStoreM = 0;
end
// bit manipulation unit
if (`B_SUPPORTED) begin:bmu
bmu bmu(.ForwardedSrcAE, .ForwardedSrcBE, .InstrD, .BMUE, .BMUResultE);
end else begin // no B instructions supported
assign BMUResultE = 0;
assign BMUE = 0;
end
endmodule

14
pipelined/src/wally/wallypipelinedsoc.sv
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@ -26,21 +26,21 @@
// and limitations under the License.
////////////////////////////////////////////////////////////////////////////////////////////////
`include "wally-config.vh"
import cvw::*; // global CORE-V-Wally parameters
module wallypipelinedsoc (
input logic clk,
input logic reset_ext, // external asynchronous reset pin
output logic reset, // reset synchronized to clk to prevent races on release
// AHB Interface
input logic [`AHBW-1:0] HRDATAEXT,
input logic [AHBW-1:0] HRDATAEXT,
input logic HREADYEXT, HRESPEXT,
output logic HSELEXT,
// outputs to external memory, shared with uncore memory
output logic HCLK, HRESETn,
output logic [`PA_BITS-1:0] HADDR,
output logic [`AHBW-1:0] HWDATA,
output logic [`XLEN/8-1:0] HWSTRB,
output logic [PA_BITS-1:0] HADDR,
output logic [AHBW-1:0] HWDATA,
output logic [XLEN/8-1:0] HWSTRB,
output logic HWRITE,
output logic [2:0] HSIZE,
output logic [2:0] HBURST,
@ -63,7 +63,7 @@ module wallypipelinedsoc (
);
// Uncore signals
logic [`AHBW-1:0] HRDATA; // from AHB mux in uncore
logic [AHBW-1:0] HRDATA; // from AHB mux in uncore
logic HRESP; // response from AHB
logic MTimerInt, MSwInt; // timer and software interrupts from CLINT
logic [63:0] MTIME_CLINT; // from CLINT to CSRs
@ -80,7 +80,7 @@ module wallypipelinedsoc (
);
// instantiate uncore if a bus interface exists
if (`BUS) begin : uncore
if (BUS_SUPPORTED) begin : uncore
uncore uncore(.HCLK, .HRESETn, .TIMECLK,
.HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST, .HPROT, .HTRANS, .HMASTLOCK, .HRDATAEXT,
.HREADYEXT, .HRESPEXT, .HRDATA, .HREADY, .HRESP, .HSELEXT,

2
pipelined/testbench/sdc/sd_top_tb.sv
View File

@ -32,7 +32,7 @@
module sd_top_tb();
localparam integer g_COUNT_WIDTH = 8;
localparam g_COUNT_WIDTH = 8;
logic a_RST;
logic i_SD_CMD;

66
pipelined/testbench/testbench.sv
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@ -205,8 +205,8 @@ logic [3:0] dummy;
InstrFName, InstrDName, InstrEName, InstrMName, InstrWName);
// initialize tests
localparam integer MemStartAddr = 0;
localparam integer MemEndAddr = `UNCORE_RAM_RANGE>>1+(`XLEN/32);
localparam MemStartAddr = 0;
localparam MemEndAddr = `UNCORE_RAM_RANGE>>1+(`XLEN/32);
initial
begin
@ -246,7 +246,7 @@ logic [3:0] dummy;
force dut.uncore.uncore.sdc.SDC.LimitTimers = 1;
end else begin
if (`IROM_SUPPORTED) $readmemh(memfilename, dut.core.ifu.irom.irom.rom.ROM);
else if (`BUS) $readmemh(memfilename, dut.uncore.uncore.ram.ram.memory.RAM);
else if (`BUS_SUPPORTED) $readmemh(memfilename, dut.uncore.uncore.ram.ram.memory.RAM);
if (`DTIM_SUPPORTED) $readmemh(memfilename, dut.core.lsu.dtim.dtim.ram.RAM);
end
@ -466,7 +466,7 @@ logic [3:0] dummy;
.done(DCacheFlushDone));
// initialize the branch predictor
if (`BPRED_ENABLED == 1)
if (`BPRED_SUPPORTED == 1)
begin
genvar adrindex;
@ -526,19 +526,19 @@ module riscvassertions;
assert (`F_SUPPORTED | ~`D_SUPPORTED) else $error("Can't support double fp (D) without supporting float (F)");
assert (`D_SUPPORTED | ~`Q_SUPPORTED) else $error("Can't support quad fp (Q) without supporting double (D)");
assert (`F_SUPPORTED | ~`ZFH_SUPPORTED) else $error("Can't support half-precision fp (ZFH) without supporting float (F)");
assert (`DCACHE | ~`F_SUPPORTED | `FLEN <= `XLEN) else $error("Data cache required to support FLEN > XLEN because AHB bus width is XLEN");
assert (`DCACHE_SUPPORTED | ~`F_SUPPORTED | `FLEN <= `XLEN) else $error("Data cache required to support FLEN > XLEN because AHB bus width is XLEN");
assert (`I_SUPPORTED ^ `E_SUPPORTED) else $error("Exactly one of I and E must be supported");
assert (`FLEN<=`XLEN | `DCACHE | `DTIM_SUPPORTED) else $error("Wally does not support FLEN > XLEN unleses data cache or DTIM is supported");
assert (`DCACHE_WAYSIZEINBYTES <= 4096 | (!`DCACHE) | `VIRTMEM_SUPPORTED == 0) else $error("DCACHE_WAYSIZEINBYTES cannot exceed 4 KiB when caches and vitual memory is enabled (to prevent aliasing)");
assert (`DCACHE_LINELENINBITS >= 128 | (!`DCACHE)) else $error("DCACHE_LINELENINBITS must be at least 128 when caches are enabled");
assert (`FLEN<=`XLEN | `DCACHE_SUPPORTED | `DTIM_SUPPORTED) else $error("Wally does not support FLEN > XLEN unleses data cache or DTIM is supported");
assert (`DCACHE_WAYSIZEINBYTES <= 4096 | (!`DCACHE_SUPPORTED) | `VIRTMEM_SUPPORTED == 0) else $error("DCACHE_WAYSIZEINBYTES cannot exceed 4 KiB when caches and vitual memory is enabled (to prevent aliasing)");
assert (`DCACHE_LINELENINBITS >= 128 | (!`DCACHE_SUPPORTED)) else $error("DCACHE_LINELENINBITS must be at least 128 when caches are enabled");
assert (`DCACHE_LINELENINBITS < `DCACHE_WAYSIZEINBYTES*8) else $error("DCACHE_LINELENINBITS must be smaller than way size");
assert (`ICACHE_WAYSIZEINBYTES <= 4096 | (!`ICACHE) | `VIRTMEM_SUPPORTED == 0) else $error("ICACHE_WAYSIZEINBYTES cannot exceed 4 KiB when caches and vitual memory is enabled (to prevent aliasing)");
assert (`ICACHE_LINELENINBITS >= 32 | (!`ICACHE)) else $error("ICACHE_LINELENINBITS must be at least 32 when caches are enabled");
assert (`ICACHE_WAYSIZEINBYTES <= 4096 | (!`ICACHE_SUPPORTED) | `VIRTMEM_SUPPORTED == 0) else $error("ICACHE_WAYSIZEINBYTES cannot exceed 4 KiB when caches and vitual memory is enabled (to prevent aliasing)");
assert (`ICACHE_LINELENINBITS >= 32 | (!`ICACHE_SUPPORTED)) else $error("ICACHE_LINELENINBITS must be at least 32 when caches are enabled");
assert (`ICACHE_LINELENINBITS < `ICACHE_WAYSIZEINBYTES*8) else $error("ICACHE_LINELENINBITS must be smaller than way size");
assert (2**$clog2(`DCACHE_LINELENINBITS) == `DCACHE_LINELENINBITS | (!`DCACHE)) else $error("DCACHE_LINELENINBITS must be a power of 2");
assert (2**$clog2(`DCACHE_WAYSIZEINBYTES) == `DCACHE_WAYSIZEINBYTES | (!`DCACHE)) else $error("DCACHE_WAYSIZEINBYTES must be a power of 2");
assert (2**$clog2(`ICACHE_LINELENINBITS) == `ICACHE_LINELENINBITS | (!`ICACHE)) else $error("ICACHE_LINELENINBITS must be a power of 2");
assert (2**$clog2(`ICACHE_WAYSIZEINBYTES) == `ICACHE_WAYSIZEINBYTES | (!`ICACHE)) else $error("ICACHE_WAYSIZEINBYTES must be a power of 2");
assert (2**$clog2(`DCACHE_LINELENINBITS) == `DCACHE_LINELENINBITS | (!`DCACHE_SUPPORTED)) else $error("DCACHE_LINELENINBITS must be a power of 2");
assert (2**$clog2(`DCACHE_WAYSIZEINBYTES) == `DCACHE_WAYSIZEINBYTES | (!`DCACHE_SUPPORTED)) else $error("DCACHE_WAYSIZEINBYTES must be a power of 2");
assert (2**$clog2(`ICACHE_LINELENINBITS) == `ICACHE_LINELENINBITS | (!`ICACHE_SUPPORTED)) else $error("ICACHE_LINELENINBITS must be a power of 2");
assert (2**$clog2(`ICACHE_WAYSIZEINBYTES) == `ICACHE_WAYSIZEINBYTES | (!`ICACHE_SUPPORTED)) else $error("ICACHE_WAYSIZEINBYTES must be a power of 2");
assert (2**$clog2(`ITLB_ENTRIES) == `ITLB_ENTRIES | `VIRTMEM_SUPPORTED==0) else $error("ITLB_ENTRIES must be a power of 2");
assert (2**$clog2(`DTLB_ENTRIES) == `DTLB_ENTRIES | `VIRTMEM_SUPPORTED==0) else $error("DTLB_ENTRIES must be a power of 2");
assert (`UNCORE_RAM_RANGE >= 56'h07FFFFFF) else $warning("Some regression tests will fail if UNCORE_RAM_RANGE is less than 56'h07FFFFFF");
@ -546,12 +546,12 @@ module riscvassertions;
assert (`ZICSR_SUPPORTED == 1 | (`S_SUPPORTED == 0 & `U_SUPPORTED == 0)) else $error("S and U modes not supported if ZISR not supported");
assert (`U_SUPPORTED | (`S_SUPPORTED == 0)) else $error ("S mode only supported if U also is supported");
assert (`VIRTMEM_SUPPORTED == 0 | (`DTIM_SUPPORTED == 0 & `IROM_SUPPORTED == 0)) else $error("Can't simultaneously have virtual memory and DTIM_SUPPORTED/IROM_SUPPORTED because local memories don't translate addresses");
assert (`DCACHE | `VIRTMEM_SUPPORTED ==0) else $error("Virtual memory needs dcache");
assert (`ICACHE | `VIRTMEM_SUPPORTED ==0) else $error("Virtual memory needs icache");
assert ((`DCACHE == 0 & `ICACHE == 0) | `BUS) else $error("Dcache and Icache requires DBUS.");
assert (`DCACHE_LINELENINBITS <= `XLEN*16 | (!`DCACHE)) else $error("DCACHE_LINELENINBITS must not exceed 16 words because max AHB burst size is 1");
assert (`DCACHE_SUPPORTED | `VIRTMEM_SUPPORTED ==0) else $error("Virtual memory needs dcache");
assert (`ICACHE_SUPPORTED | `VIRTMEM_SUPPORTED ==0) else $error("Virtual memory needs icache");
assert ((`DCACHE_SUPPORTED == 0 & `ICACHE_SUPPORTED == 0) | `BUS_SUPPORTED) else $error("Dcache and Icache requires DBUS_SUPPORTED.");
assert (`DCACHE_LINELENINBITS <= `XLEN*16 | (!`DCACHE_SUPPORTED)) else $error("DCACHE_LINELENINBITS must not exceed 16 words because max AHB burst size is 1");
assert (`DCACHE_LINELENINBITS % 4 == 0) else $error("DCACHE_LINELENINBITS must hold 4, 8, or 16 words");
assert (`DCACHE | `A_SUPPORTED == 0) else $error("Atomic extension (A) requires cache on Wally.");
assert (`DCACHE_SUPPORTED | `A_SUPPORTED == 0) else $error("Atomic extension (A) requires cache on Wally.");
assert (`IDIV_ON_FPU == 0 | `F_SUPPORTED) else $error("IDIV on FPU needs F_SUPPORTED");
end
@ -572,26 +572,24 @@ module DCacheFlushFSM
logic [`XLEN-1:0] ShadowRAM[`UNCORE_RAM_BASE>>(1+`XLEN/32):(`UNCORE_RAM_RANGE+`UNCORE_RAM_BASE)>>1+(`XLEN/32)];
if(`DCACHE) begin
localparam integer numlines = testbench.dut.core.lsu.bus.dcache.dcache.NUMLINES;
localparam integer numways = testbench.dut.core.lsu.bus.dcache.dcache.NUMWAYS;
localparam integer linebytelen = testbench.dut.core.lsu.bus.dcache.dcache.LINEBYTELEN;
localparam integer linelen = testbench.dut.core.lsu.bus.dcache.dcache.LINELEN;
localparam integer sramlen = testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[0].SRAMLEN;
localparam integer cachesramwords = testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[0].NUMSRAM;
//testbench.dut.core.lsu.bus.dcache.dcache.CacheWays.NUMSRAM;
localparam integer numwords = sramlen/`XLEN;
localparam integer lognumlines = $clog2(numlines);
localparam integer loglinebytelen = $clog2(linebytelen);
localparam integer lognumways = $clog2(numways);
localparam integer tagstart = lognumlines + loglinebytelen;
if(`DCACHE_SUPPORTED) begin
localparam numlines = testbench.dut.core.lsu.bus.dcache.dcache.NUMLINES;
localparam numways = testbench.dut.core.lsu.bus.dcache.dcache.NUMWAYS;
localparam linebytelen = testbench.dut.core.lsu.bus.dcache.dcache.LINEBYTELEN;
localparam linelen = testbench.dut.core.lsu.bus.dcache.dcache.LINELEN;
localparam sramlen = testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[0].SRAMLEN;
localparam cachesramwords = testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[0].NUMSRAM;
localparam numwords = sramlen/`XLEN;
localparam lognumlines = $clog2(numlines);
localparam loglinebytelen = $clog2(linebytelen);
localparam lognumways = $clog2(numways);
localparam tagstart = lognumlines + loglinebytelen;
genvar index, way, cacheWord;
logic [sramlen-1:0] CacheData [numways-1:0] [numlines-1:0] [cachesramwords-1:0];
logic [sramlen-1:0] cacheline;
logic [sramlen-1:0] cacheline;
logic [`XLEN-1:0] CacheTag [numways-1:0] [numlines-1:0] [cachesramwords-1:0];
logic CacheValid [numways-1:0] [numlines-1:0] [cachesramwords-1:0];
logic CacheDirty [numways-1:0] [numlines-1:0] [cachesramwords-1:0];

24
pipelined/testbench/testbench_imperas.sv
View File

@ -100,8 +100,8 @@ module testbench;
pathname = "../../tests/riscof/work/wally-riscv-arch-test/";
memfilename = {pathname, testName, "/ref/ref.elf.memfile"};
if (`BUS) $readmemh(memfilename, dut.uncore.uncore.ram.ram.memory.RAM);
else $error("Imperas test bench requires BUS.");
if (`BUS_SUPPORTED) $readmemh(memfilename, dut.uncore.uncore.ram.ram.memory.RAM);
else $error("Imperas test bench requires BUS_SUPPORTED.");
ProgramAddrMapFile = {pathname, testName, "/ref/ref.elf.objdump.addr"};
ProgramLabelMapFile = {pathname, testName, "/ref/ref.elf.objdump.lab"};
@ -219,7 +219,7 @@ module testbench;
.done(DCacheFlushDone));
// initialize the branch predictor
if (`BPRED_ENABLED == 1)
if (`BPRED_SUPPORTED == 1)
begin
genvar adrindex;
@ -265,14 +265,14 @@ module riscvassertions;
assert (`F_SUPPORTED | ~`D_SUPPORTED) else $error("Can't support double fp (D) without supporting float (F)");
assert (`D_SUPPORTED | ~`Q_SUPPORTED) else $error("Can't support quad fp (Q) without supporting double (D)");
assert (`F_SUPPORTED | ~`ZFH_SUPPORTED) else $error("Can't support half-precision fp (ZFH) without supporting float (F)");
assert (`DCACHE | ~`F_SUPPORTED | `FLEN <= `XLEN) else $error("Data cache required to support FLEN > XLEN because AHB bus width is XLEN");
assert (`DCACHE_SUPPORTED | ~`F_SUPPORTED | `FLEN <= `XLEN) else $error("Data cache required to support FLEN > XLEN because AHB bus width is XLEN");
assert (`I_SUPPORTED ^ `E_SUPPORTED) else $error("Exactly one of I and E must be supported");
assert (`FLEN<=`XLEN | `DCACHE | `DTIM_SUPPORTED) else $error("Wally does not support FLEN > XLEN unleses data cache or DTIM is supported");
assert (`DCACHE_WAYSIZEINBYTES <= 4096 | (!`DCACHE) | `VIRTMEM_SUPPORTED == 0) else $error("DCACHE_WAYSIZEINBYTES cannot exceed 4 KiB when caches and vitual memory is enabled (to prevent aliasing)");
assert (`DCACHE_LINELENINBITS >= 128 | (!`DCACHE)) else $error("DCACHE_LINELENINBITS must be at least 128 when caches are enabled");
assert (`DCACHE_WAYSIZEINBYTES <= 4096 | (!`DCACHE_SUPPORTED) | `VIRTMEM_SUPPORTED == 0) else $error("DCACHE_WAYSIZEINBYTES cannot exceed 4 KiB when caches and vitual memory is enabled (to prevent aliasing)");
assert (`DCACHE_LINELENINBITS >= 128 | (!`DCACH_SUPPORTED)) else $error("DCACHE_LINELENINBITS must be at least 128 when caches are enabled");
assert (`DCACHE_LINELENINBITS < `DCACHE_WAYSIZEINBYTES*8) else $error("DCACHE_LINELENINBITS must be smaller than way size");
assert (`ICACHE_WAYSIZEINBYTES <= 4096 | (!`ICACHE) | `VIRTMEM_SUPPORTED == 0) else $error("ICACHE_WAYSIZEINBYTES cannot exceed 4 KiB when caches and vitual memory is enabled (to prevent aliasing)");
assert (`ICACHE_LINELENINBITS >= 32 | (!`ICACHE)) else $error("ICACHE_LINELENINBITS must be at least 32 when caches are enabled");
assert (`ICACHE_WAYSIZEINBYTES <= 4096 | (!`ICACHE_SUPPORTED) | `VIRTMEM_SUPPORTED == 0) else $error("ICACHE_WAYSIZEINBYTES cannot exceed 4 KiB when caches and vitual memory is enabled (to prevent aliasing)");
assert (`ICACHE_LINELENINBITS >= 32 | (!`ICACHE_SUPPORTED)) else $error("ICACHE_LINELENINBITS must be at least 32 when caches are enabled");
assert (`ICACHE_LINELENINBITS < `ICACHE_WAYSIZEINBYTES*8) else $error("ICACHE_LINELENINBITS must be smaller than way size");
assert (2**$clog2(`DCACHE_LINELENINBITS) == `DCACHE_LINELENINBITS | (!`DCACHE)) else $error("DCACHE_LINELENINBITS must be a power of 2");
assert (2**$clog2(`DCACHE_WAYSIZEINBYTES) == `DCACHE_WAYSIZEINBYTES | (!`DCACHE)) else $error("DCACHE_WAYSIZEINBYTES must be a power of 2");
@ -285,12 +285,12 @@ module riscvassertions;
assert (`ZICSR_SUPPORTED == 1 | (`S_SUPPORTED == 0 & `U_SUPPORTED == 0)) else $error("S and U modes not supported if ZISR not supported");
assert (`U_SUPPORTED | (`S_SUPPORTED == 0)) else $error ("S mode only supported if U also is supported");
assert (`VIRTMEM_SUPPORTED == 0 | (`DTIM_SUPPORTED == 0 & `IROM_SUPPORTED == 0)) else $error("Can't simultaneously have virtual memory and DTIM_SUPPORTED/IROM_SUPPORTED because local memories don't translate addresses");
assert (`DCACHE | `VIRTMEM_SUPPORTED ==0) else $error("Virtual memory needs dcache");
assert (`ICACHE | `VIRTMEM_SUPPORTED ==0) else $error("Virtual memory needs icache");
assert ((`DCACHE == 0 & `ICACHE == 0) | `BUS) else $error("Dcache and Icache requires DBUS.");
assert (`DCACHE_SUPPORTED | `VIRTMEM_SUPPORTED ==0) else $error("Virtual memory needs dcache");
assert (`ICACHE_SUPPORTED | `VIRTMEM_SUPPORTED ==0) else $error("Virtual memory needs icache");
assert ((`DCACHE_SUPPORTED == 0 & `ICACHE_SUPPORTED == 0) | `BUS_SUPPORTED) else $error("Dcache and Icache requires DBUS.");
assert (`DCACHE_LINELENINBITS <= `XLEN*16 | (!`DCACHE)) else $error("DCACHE_LINELENINBITS must not exceed 16 words because max AHB burst size is 1");
assert (`DCACHE_LINELENINBITS % 4 == 0) else $error("DCACHE_LINELENINBITS must hold 4, 8, or 16 words");
assert (`DCACHE | `A_SUPPORTED == 0) else $error("Atomic extension (A) requires cache on Wally.");
assert (`DCACHE_SUPPORTED | `A_SUPPORTED == 0) else $error("Atomic extension (A) requires cache on Wally.");
assert (`IDIV_ON_FPU == 0 | `F_SUPPORTED) else $error("IDIV on FPU needs F_SUPPORTED");
end

72
synthDC/Makefile
View File

@ -8,6 +8,7 @@ NAME := synth
export DESIGN ?= wallypipelinedcore
export FREQ ?= 3000
export CONFIG ?= rv32e
export MOD ?= orig
# title to add a note in the synth's directory name
TITLE =
# tsmc28, sky130, and sky90 presently supported
@ -22,13 +23,15 @@ export DRIVE ?= FLOP
time := $(shell date +%F-%H-%M)
hash := $(shell git rev-parse --short HEAD)
export OUTPUTDIR := runs/$(DESIGN)_$(CONFIG)_$(TECH)nm_$(FREQ)_MHz_$(time)_$(TITLE)_$(hash)
export OUTPUTDIR := runs/$(DESIGN)_$(CONFIG)_$(MOD)_$(TECH)nm_$(FREQ)_MHz_$(time)_$(TITLE)_$(hash)
export SAIFPOWER ?= 0
CONFIGDIR ?= ${WALLY}/pipelined/config
configAsList := $(subst _, ,$(CONFIG))
BASECONFIG := $(word 1, $(configAsList))
OLDCONFIGDIR ?= ${WALLY}/pipelined/config
CONFIGDIR ?= $(OUTPUTDIR)/hdl/config
CONFIGFILES ?= $(shell find $(CONFIGDIR) -name rv*_*)
CONFIGFILESTRIM = $(notdir $(CONFIGFILES))
# FREQS = 25 50 100 150 200 250 300 350 400
# k = 3 6
print:
@ -42,8 +45,8 @@ default:
@echo "Use wallySynth.py to run a concurrent sweep "
DIRS32 = rv32e rv32gc rv32ic
DIRS64 = rv64ic rv64gc
DIRS32 = rv32e rv32gc rv32ic rv32i
DIRS64 = rv64i rv64gc
DIRS = $(DIRS32) $(DIRS64)
# bpred:
@ -51,73 +54,72 @@ DIRS = $(DIRS32) $(DIRS64)
# @$(foreach kval, $(k), cp -r $(CONFIGDIR)/rv64gc $(CONFIGDIR)/rv64gc_bpred_$(kval);)
# @$(foreach kval, $(k), sed -i 's/BPRED_SIZE.*/BPRED_SIZE $(kval)/g' $(CONFIGDIR)/rv64gc_bpred_$(kval)/wally-config.vh;)
# @$(foreach kval, $(k), make synth DESIGN=wallypipelinedcore CONFIG=rv64gc_bpred_$(kval) TECH=sky90 FREQ=500 MAXCORES=4 --jobs;)
copy:
# remove old config files
rm -rf $(CONFIGDIR)/*_*
@$(foreach dir, $(DIRS), rm -rf $(CONFIGDIR)/$(dir)_orig;)
@$(foreach dir, $(DIRS), cp -r $(CONFIGDIR)/$(dir) $(CONFIGDIR)/$(dir)_orig;)
@$(foreach dir, $(DIRS), sed -i 's/WAYSIZEINBYTES.*/WAYSIZEINBYTES 512/g' $(CONFIGDIR)/$(dir)_orig/wally-config.vh;)
@$(foreach dir, $(DIRS), sed -i 's/NUMWAYS.*/NUMWAYS 1/g' $(CONFIGDIR)/$(dir)_orig/wally-config.vh;)
@$(foreach dir, $(DIRS), sed -i 's/BPRED_SIZE.*/BPRED_SIZE 4/g' $(CONFIGDIR)/$(dir)_orig/wally-config.vh;)
configs: $(BASECONFIG)
$(BASECONFIG):
@echo $(BASECONFIG)
cp -r $(OLDCONFIGDIR)/$(BASECONFIG) $(CONFIGDIR)/$(BASECONFIG)_orig
sed -i 's/WAYSIZEINBYTES.*/WAYSIZEINBYTES 512/g' $(CONFIGDIR)/$(BASECONFIG)_orig/wally-config.vh
sed -i 's/NUMWAYS.*/NUMWAYS 1/g' $(CONFIGDIR)/$(BASECONFIG)_orig/wally-config.vh
sed -i 's/BPRED_SIZE.*/BPRED_SIZE 4/g' $(CONFIGDIR)/$(BASECONFIG)_orig/wally-config.vh
@$(foreach dir, $(DIRS32), sed -i "s/RAM_RANGE.*/RAM_RANGE 34\'h01FF/g" $(CONFIGDIR)/$(dir)_orig/wally-config.vh ;)
@$(foreach dir, $(DIRS64), sed -i "s/RAM_RANGE.*/RAM_RANGE 56\'h01FF/g" $(CONFIGDIR)/$(dir)_orig/wally-config.vh ;)
configs: $(DIRS)
$(DIRS):
ifneq ($(filter $ $(BASECONFIG), $(DIRS32)),)
sed -i "s/RAM_RANGE.*/RAM_RANGE 34\'h01FF/g" $(CONFIGDIR)/$(BASECONFIG)_orig/wally-config.vh
else ifneq ($(filter $ $(BASECONFIG), $(DIRS64)),)
sed -i "s/RAM_RANGE.*/RAM_RANGE 56\'h01FF/g" $(CONFIGDIR)/$(BASECONFIG)_orig/wally-config.vh
else
$(info $(BASECONFIG) does not exist in $(DIRS32) or $(DIRS64))
@echo "Config not in list, RAM_RANGE will be unmodified"
endif
# turn off FPU
rm -rf $(CONFIGDIR)/$@_FPUoff
cp -r $(CONFIGDIR)/$@_orig $(CONFIGDIR)/$@_FPUoff
sed -i 's/1 *<< *3/0 << 3/' $(CONFIGDIR)/$@_FPUoff/wally-config.vh
sed -i 's/1 *<< *5/0 << 5/' $(CONFIGDIR)/$@_FPUoff/wally-config.vh
# PMP 16
rm -rf $(CONFIGDIR)/$@_PMP16
cp -r $(CONFIGDIR)/$@_FPUoff $(CONFIGDIR)/$@_PMP16
sed -i 's/PMP_ENTRIES \(64\|16\|0\)/PMP_ENTRIES 16/' $(CONFIGDIR)/$@_PMP16/wally-config.vh
# PMP 0
rm -rf $(CONFIGDIR)/$@_PMP0
cp -r $(CONFIGDIR)/$@_FPUoff $(CONFIGDIR)/$@_PMP0
sed -i 's/PMP_ENTRIES \(64\|16\|0\)/PMP_ENTRIES 0/' $(CONFIGDIR)/$@_PMP0/wally-config.vh
# no muldiv
rm -rf $(CONFIGDIR)/$@_noMulDiv
cp -r $(CONFIGDIR)/$@_PMP0 $(CONFIGDIR)/$@_noMulDiv
sed -i 's/1 *<< *12/0 << 12/' $(CONFIGDIR)/$@_noMulDiv/wally-config.vh
# no priv
rm -rf $(CONFIGDIR)/$@_noPriv
cp -r $(CONFIGDIR)/$@_noMulDiv $(CONFIGDIR)/$@_noPriv
sed -i 's/ZICSR_SUPPORTED *1/ZICSR_SUPPORTED 0/' $(CONFIGDIR)/$@_noPriv/wally-config.vh
ifeq ($(SAIFPOWER), 1)
cp -f ../pipelined/regression/power.saif .
endif
freqs:
@$(foreach freq, $(FREQS), make synth DESIGN=wallypipelinedcore CONFIG=rv32e FREQ=$(freq) MAXCORES=1;)
synth:
mkdirecs:
@echo "DC Synthesis"
@mkdir -p $(OUTPUTDIR)
@mkdir -p $(OUTPUTDIR)/hdl
@mkdir -p $(OUTPUTDIR)/hdl/config
@mkdir -p $(OUTPUTDIR)/reports
@mkdir -p $(OUTPUTDIR)/mapped
@mkdir -p $(OUTPUTDIR)/unmapped
ifeq ($(SAIFPOWER), 1)
cp -f ../pipelined/regression/power.saif .
endif
synth: mkdirecs configs rundc clean
rundc:
dc_shell-xg-t -64bit -f scripts/$(NAME).tcl | tee $(OUTPUTDIR)/$(NAME).out
# rm -rf $(OUTPUTDIR)/hdl
clean:
rm -rf $(OUTPUTDIR)/hdl
rm -rf $(OUTPUTDIR)/WORK
rm -rf $(OUTPUTDIR)/alib-52
clean:
rm -f default.svf
rm -f command.log
rm -f filenames*.log
rm -f power.saif
rm -f Synopsys_stack_trace_*.txt
rm -f crte_*.txt
fresh: clean copy configs
@echo "synth directory cleaned and fresh config files written"
rm -f crte_*.txt

54
synthDC/extractSummary.py
View File

@ -28,16 +28,16 @@ def synthsintocsv():
file = open("Summary.csv", "w")
writer = csv.writer(file)
writer.writerow(['Width', 'Config', 'Special', 'Tech', 'Target Freq', 'Delay', 'Area'])
writer.writerow(['Width', 'Config', 'Mod', 'Tech', 'Target Freq', 'Delay', 'Area'])
for oneSynth in allSynths:
descrip = specReg.findall(oneSynth)
width = descrip[2][:4]
config = descrip[2][4:]
if descrip[3][-2:] == 'nm':
special = ''
mod = ''
else:
special = descrip[3]
mod = descrip[3]
descrip = descrip[1:]
tech = descrip[3][:-2]
freq = descrip[4]
@ -57,12 +57,12 @@ def synthsintocsv():
else:
delay = 1000/int(freq) - metrics[0]
area = metrics[1]
writer.writerow([width, config, special, tech, freq, delay, area])
writer.writerow([width, config, mod, tech, freq, delay, area])
file.close()
def synthsfromcsv(filename):
Synth = namedtuple("Synth", "width config special tech freq delay area")
Synth = namedtuple("Synth", "width config mod tech freq delay area")
with open(filename, newline='') as csvfile:
csvreader = csv.reader(csvfile)
global allSynths
@ -81,14 +81,9 @@ def freqPlot(tech, width, config):
''' plots delay, area for syntheses with specified tech, module, width
'''
current_directory = os.getcwd()
final_directory = os.path.join(current_directory, 'plots/wally')
if not os.path.exists(final_directory):
os.makedirs(final_directory)
freqsL, delaysL, areasL = ([[], []] for i in range(3))
for oneSynth in allSynths:
if (width == oneSynth.width) & (config == oneSynth.config) & (tech == oneSynth.tech) & ('' == oneSynth.special):
if (width == oneSynth.width) & (config == oneSynth.config) & (tech == oneSynth.tech) & ('orig' == oneSynth.mod):
ind = (1000/oneSynth.delay < oneSynth.freq) # when delay is within target clock period
freqsL[ind] += [oneSynth.freq]
delaysL[ind] += [oneSynth.delay]
@ -130,7 +125,7 @@ def freqPlot(tech, width, config):
ax2.yaxis.set_major_formatter(ticker.StrMethodFormatter('{x:,.0f}'))
addFO4axis(fig, ax1, tech)
plt.savefig('./plots/wally/freqSweep_' + tech + '_' + width + config + '.png')
plt.savefig(final_directory + '/freqSweep_' + tech + '_' + width + config + '.png')
def areaDelay(tech, delays, areas, labels, fig, ax, norm=False):
@ -168,7 +163,7 @@ def plotFeatures(tech, width, config):
if (oneSynth.config == config) & (width == oneSynth.width):
delays += [oneSynth.delay]
areas += [oneSynth.area]
labels += [oneSynth.special]
labels += [oneSynth.mod]
fig, (ax) = plt.subplots(1, 1)
@ -176,28 +171,28 @@ def plotFeatures(tech, width, config):
titlestr = tech+'_'+width+config
plt.title(titlestr)
plt.savefig('./plots/wally/features_'+titlestr+'.png')
plt.savefig(final_directory + '/features_'+titlestr+'.png')
def plotConfigs(tech, special=''):
def plotConfigs(tech, mod=''):
delays, areas, labels = ([] for i in range(3))
freq = techdict[tech].targfreq
for oneSynth in allSynths:
if (tech == oneSynth.tech) & (freq == oneSynth.freq) & (oneSynth.special == special):
delays += [oneSynth.delay]
areas += [oneSynth.area]
labels += [oneSynth.width + oneSynth.config]
if (tech == oneSynth.tech) & (freq == oneSynth.freq) & (oneSynth.mod == mod):
delays += [oneSynth.delay]
areas += [oneSynth.area]
labels += [oneSynth.width + oneSynth.config]
fig, (ax) = plt.subplots(1, 1)
fig = areaDelay(tech, delays, areas, labels, fig, ax)
titleStr = tech+'_'+special
titleStr = tech+'_'+mod
plt.title(titleStr)
plt.savefig('./plots/wally/configs_' + titleStr + '.png')
plt.savefig(final_directory + '/configs_' + titleStr + '.png')
def normAreaDelay(special=''):
def normAreaDelay(mod=''):
fig, (ax) = plt.subplots(1, 1)
fullLeg = []
for tech in list(techdict.keys()):
@ -205,7 +200,7 @@ def normAreaDelay(special=''):
spec = techdict[tech]
freq = spec.targfreq
for oneSynth in allSynths:
if (tech == oneSynth.tech) & (freq == oneSynth.freq) & (oneSynth.special == special):
if (tech == oneSynth.tech) & (freq == oneSynth.freq) & (oneSynth.mod == mod):
delays += [oneSynth.delay]
areas += [oneSynth.area]
labels += [oneSynth.width + oneSynth.config]
@ -216,7 +211,7 @@ def normAreaDelay(special=''):
ax.set_xlabel('Cycle Time (FO4)')
ax.set_ylabel('Area (add32)')
ax.legend(handles = fullLeg, loc='upper left')
plt.savefig('./plots/wally/normAreaDelay.png')
plt.savefig(final_directory + '/normAreaDelay.png')
def addFO4axis(fig, ax, tech):
@ -254,12 +249,17 @@ if __name__ == '__main__':
techdict['sky90'] = TechSpec('green', 'o', args.skyfreq, 43.2e-3, 1440.600027, 714.057, 0.658023)
techdict['tsmc28'] = TechSpec('blue', 's', args.tsmcfreq, 12.2e-3, 209.286002, 1060.0, .081533)
current_directory = os.getcwd()
final_directory = os.path.join(current_directory, 'wallyplots')
if not os.path.exists(final_directory):
os.makedirs(final_directory)
synthsintocsv()
synthsfromcsv('Summary.csv')
freqPlot('tsmc28', 'rv32', 'e')
freqPlot('sky90', 'rv32', 'e')
plotFeatures('sky90', 'rv64', 'gc')
plotFeatures('tsmc28', 'rv64', 'gc')
plotConfigs('sky90', special='orig')
plotConfigs('tsmc28', special='orig')
normAreaDelay(special='orig')
plotConfigs('sky90', mod='orig')
plotConfigs('tsmc28', mod='orig')
normAreaDelay(mod='orig')

1
synthDC/scripts/synth.tcl
View File

@ -30,6 +30,7 @@ eval file copy -force ${cfg} {$outputDir/hdl/}
#eval file copy -force ${cfg} $outputDir
eval file copy -force [glob ${hdl_src}/../config/shared/*.vh] {$outputDir/hdl/}
eval file copy -force [glob ${hdl_src}/*/*.sv] {$outputDir/hdl/}
eval file copy -force [glob ${hdl_src}/*/*/*.sv] {$outputDir/hdl/}
eval file copy -force [glob ${hdl_src}/*/flop/*.sv] {$outputDir/hdl/}
# Only for FMA class project; comment out when done

31
synthDC/wallySynth.py
View File

@ -5,20 +5,14 @@ import subprocess
from multiprocessing import Pool
import argparse
def runSynth(config, tech, freq, maxopt):
def runSynth(config, mod, tech, freq, maxopt):
global pool
command = "make synth DESIGN=wallypipelinedcore CONFIG={} TECH={} DRIVE=FLOP FREQ={} MAXOPT={} MAXCORES=1".format(config, tech, freq, maxopt)
command = "make synth DESIGN=wallypipelinedcore CONFIG={} MOD={} TECH={} DRIVE=FLOP FREQ={} MAXOPT={} MAXCORES=1".format(config, mod, tech, freq, maxopt)
pool.map(mask, [command])
def mask(command):
subprocess.Popen(command, shell=True)
def freshStart():
out = subprocess.check_output(['bash','-c', 'make fresh'])
for x in out.decode("utf-8").split('\n')[:-1]:
print(x)
return
if __name__ == '__main__':
@ -41,24 +35,21 @@ if __name__ == '__main__':
args = parser.parse_args()
freq = args.targetfreq if args.targetfreq else 3000
tech = args.tech if args.tech else 'sky90'
defaultfreq = 3000 if tech == 'sky90' else 10000
freq = args.targetfreq if args.targetfreq else defaultfreq
maxopt = int(args.maxopt)
mod = 'orig' # until memory integrated
if args.freqsweep:
sc = args.freqsweep
config = args.version if args.version else 'rv32e'
freshStart()
for freq in [round(sc+sc*x/100) for x in freqVaryPct]: # rv32e freq sweep
runSynth(config, tech, freq, maxopt)
runSynth(config, mod, tech, freq, maxopt)
if args.configsweep:
freshStart()
for config in ['rv32gc', 'rv32ic', 'rv64gc', 'rv64ic', 'rv32e']: # configs
config = config + '_orig' # until memory integrated
runSynth(config, tech, freq, maxopt)
for config in ['rv32i', 'rv64gc', 'rv64i', 'rv32gc', 'rv32ic', 'rv32e']: #configs
runSynth(config, mod, tech, freq, maxopt)
if args.featuresweep:
freshStart()
v = args.version if args.version else 'rv64gc'
for mod in ['FPUoff', 'noMulDiv', 'noPriv', 'PMP0', 'PMP16']: # rv64gc path variations
config = v + '_' + mod
runSynth(config, tech, freq, maxopt)
config = args.version if args.version else 'rv64gc'
for mod in ['FPUoff', 'noMulDiv', 'noPriv', 'PMP0', 'PMP16']: # rv64gc path variations 'orig',
runSynth(config, mod, tech, freq, maxopt)

2
tests/riscof/Makefile
View File

@ -16,7 +16,7 @@ root:
mkdir -p $(work)
mkdir -p $(arch_workdir)
mkdir -p $(wally_workdir)
sed 's,{0},$(current_dir),g;s,{1},32imc,g' config.ini > config32.ini
sed 's,{0},$(current_dir),g;s,{1},32gc,g' config.ini > config32.ini
sed 's,{0},$(current_dir),g;s,{1},64gc,g' config.ini > config64.ini
sed 's,{0},$(current_dir),g;s,{1},32e,g' config.ini > config32e.ini

4
tests/riscof/spike/spike_rv32e_isa.yaml
View File

@ -1,11 +1,11 @@
hart_ids: [0]
hart0:
ISA: RV32EMFCZicsr_Zifencei
ISA: RV32EMCZicsr_Zifencei
physical_addr_sz: 32
User_Spec_Version: '2.3'
supported_xlen: [32]
misa:
reset-val: 0x40001034
reset-val: 0x40001014
rv32:
accessible: true
mxl:

0
tests/riscof/spike/spike_rv32imc_isa.yaml → tests/riscof/spike/spike_rv32gc_isa.yaml
View File

8
tests/testgen/testgen.py
View File

@ -76,11 +76,6 @@ def writeVector(a, b, storecmd, xlen):
lines = lines + storecmd + " x" + str(reg3) + ", " + str(wordsize*testnum) + "(x6)\n"
# lines = lines + "RVTEST_IO_ASSERT_GPR_EQ(x7, " + str(reg3) +", "+formatstr.format(expected)+")\n"
f.write(lines)
if (xlen == 32):
line = formatrefstr.format(expected)+"\n"
else:
line = formatrefstr.format(expected % 2**32)+"\n" + formatrefstr.format(expected >> 32) + "\n"
r.write(line)
testnum = testnum+1
##################################
@ -114,12 +109,10 @@ for xlen in xlens:
pathname = "../wally-riscv-arch-test/riscv-test-suite/rv" + str(xlen) + "i_m/I/"
basename = "WALLY-" + test
fname = pathname + "src/" + basename + ".S"
refname = pathname + "references/" + basename + ".reference_output"
testnum = 0
# print custom header part
f = open(fname, "w")
r = open(refname, "w")
line = "///////////////////////////////////////////\n"
f.write(line)
lines="// "+fname+ "\n// " + author + "\n"
@ -154,7 +147,6 @@ for xlen in xlens:
# lines = lines + "\nRV_COMPLIANCE_DATA_END\n"
f.write(lines)
f.close()
r.close()

580
tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/references/cadd-01.reference_output
View File

@ -1,580 +0,0 @@
bfffffff
00004000
bfffdffe
e000003f
56666665
f7fffffa
fbff4afc
ffffffff
00000000
ef7ffffe
ffc0ffff
1fdfffff
fff00002
fff74afc
003bffff
fffe001f
ffff0005
3332b333
3fffbfff
fbffdffe
fffeeffe
0001f7ff
66666265
dffffdfe
ffffff07
ffffff3e
7fffffbe
66666646
55555545
fffffff9
ffff7ffa
0ffffffd
66666665
dfffffff
5e666665
fdff4afc
ff0fffff
bf7fffff
00bfffff
55355555
002fffff
ffffffff
007bffff
bffdffff
003fbfff
fffff03f
1ffff7ff
ffff7bfe
ffffddfe
ffffff03
333332b1
0000001f
efffffee
01fffff7
55555552
1ffffffe
80000004
3ffffffa
0ffffff8
07fffffa
03fffffb
55755556
00040002
00020020
0000fdff
fe007fff
00002fff
ffff9fff
ffff5afc
fc0007ff
00001400
aaaaacaa
00040100
fc00007f
0000000f
00000110
0000000a
00010002
00000005
07fffff6
03dfffff
00fffffc
00800000
66866666
55655556
00080200
aaab2aab
00004100
00008800
01000400
00040200
0000b585
0000b514
ffffff80
00016a0a
00000002
66671b6c
3333e839
0000b50b
aaab5fb0
55560a5b
0000b509
00016a08
0000b505
66671b6a
3333e837
55560a59
0000b507
00016a09
00000001
66671b6b
3333e838
0000b50a
aaab5faf
55560a5a
0000b508
00000002
fffe95fa
6665b164
33327e31
ffff4b03
aaa9f5a8
5554a053
ffff4b01
00000000
ffff4afd
6665b162
33327e2f
5554a051
ffff4aff
00000001
fffe95f9
6665b163
33327e30
ffff4b02
aaa9f5a7
5554a052
ffff4b00
66671b6c
6665b164
ccccccce
9999999b
6666666d
11111112
bbbbbbbd
6666666b
66671b6a
66666667
cccccccc
99999999
bbbbbbbb
66666669
66671b6b
6665b163
cccccccd
9999999a
6666666c
11111111
bbbbbbbc
6666666a
3333e839
33327e31
9999999b
66666668
3333333a
dddddddf
8888888a
33333338
3333e837
33333334
99999999
66666666
88888888
33333336
3333e838
33327e30
9999999a
66666667
33333339
ddddddde
88888889
33333337
0000b50b
ffff4b03
6666666d
3333333a
0000000c
aaaaaab1
5555555c
0000000a
0000b509
00000006
6666666b
33333338
5555555a
00000008
0000b50a
ffff4b02
6666666c
33333339
0000000b
aaaaaab0
5555555b
00000009
aaab5fb0
aaa9f5a8
11111112
dddddddf
aaaaaab1
55555556
00000001
aaaaaaaf
aaab5fae
aaaaaaab
11111110
dddddddd
ffffffff
aaaaaaad
aaab5faf
aaa9f5a7
11111111
ddddddde
aaaaaab0
55555555
00000000
aaaaaaae
55560a5b
5554a053
bbbbbbbd
8888888a
5555555c
00000001
aaaaaaac
5555555a
55560a59
55555556
bbbbbbbb
88888888
aaaaaaaa
55555558
55560a5a
5554a052
bbbbbbbc
88888889
5555555b
00000000
aaaaaaab
55555559
0000b509
ffff4b01
6666666b
33333338
0000000a
aaaaaaaf
5555555a
00000008
0000b507
00000004
66666669
33333336
55555558
00000006
0000b508
ffff4b00
6666666a
33333337
00000009
aaaaaaae
55555559
00000007
00016a08
00000000
66671b6a
3333e837
0000b509
aaab5fae
55560a59
0000b507
00016a06
0000b503
66671b68
3333e835
55560a57
0000b505
00016a07
ffffffff
66671b69
3333e836
0000b508
aaab5fad
55560a58
0000b506
0000b505
ffff4afd
66666667
33333334
00000006
aaaaaaab
55555556
00000004
0000b503
00000000
66666665
33333332
55555554
00000002
0000b504
ffff4afc
66666666
33333333
00000005
aaaaaaaa
55555555
00000003
66671b6a
6665b162
cccccccc
99999999
6666666b
11111110
bbbbbbbb
66666669
66671b68
66666665
33333333
99999998
66666665
88888887
33333335
3333e837
33327e2f
99999999
66666666
33333338
dddddddd
88888888
33333336
0000b50a
ffff4b02
6666666c
33333339
0000000b
aaaaaab0
5555555b
00000009
0000b508
00000005
6666666a
33333337
55555559
00000007
0000b509
ffff4b01
6666666b
33333338
0000000a
aaaaaaaf
5555555a
00000008
aaab5faf
aaa9f5a7
11111111
ddddddde
aaaaaab0
55555555
00000000
aaaaaaae
aaab5fad
aaaaaaaa
1111110f
dddddddc
fffffffe
aaaaaaac
aaab5fae
aaa9f5a6
11111110
dddddddd
aaaaaaaf
55555554
ffffffff
aaaaaaad
55560a5a
5554a052
bbbbbbbc
88888889
5555555b
00000000
aaaaaaab
55555559
55560a58
55555555
bbbbbbba
88888887
aaaaaaa9
55555557
55560a59
5554a051
bbbbbbbb
88888888
5555555a
ffffffff
aaaaaaaa
55555558
0000b508
ffff4b00
6666666a
33333337
00000009
aaaaaaae
55555559
00000007
0000b506
00000003
66666668
33333335
55555557
00000005
0000b507
ffff4aff
66666669
33333336
00000008
aaaaaaad
55555558
00000006
ccccccca
99999997
bbbbbbb9
66666667
66671b69
6665b161
cccccccb
99999998
6666666a
1111110f
bbbbbbba
66666668
3333e837
33327e2f
99999999
66666666
33333338
dddddddd
88888888
33333336
3333e835
33333332
99999997
66666664
88888886
33333334
3333e836
33327e2e
99999998
66666665
33333337
dddddddc
88888887
33333335
55560a59
5554a051
bbbbbbbb
88888888
5555555a
ffffffff
aaaaaaaa
55555558
55560a57
55555554
bbbbbbb9
88888886
aaaaaaa8
55555556
55560a58
5554a050
bbbbbbba
88888887
55555559
fffffffe
aaaaaaa9
55555557
0000b507
ffff4aff
66666669
33333336
00000008
aaaaaaad
55555558
00000006
0000b505
00000002
66666667
33333334
55555556
00000004
0000b506
ffff4afe
66666668
33333335
00000007
aaaaaaac
55555557
00000005
00016a09
00000001
66671b6b
3333e838
0000b50a
aaab5faf
55560a5a
0000b508
00016a07
0000b504
66671b69
3333e836
55560a58
0000b506
00016a08
00000000
66671b6a
3333e837
0000b509
aaab5fae
55560a59
0000b507
00000001
fffe95f9
6665b163
33327e30
ffff4b02
aaa9f5a7
5554a052
ffff4b00
ffffffff
ffff4afc
6665b161
33327e2e
5554a050
ffff4afe
00000000
fffe95f8
6665b162
33327e2f
ffff4b01
aaa9f5a6
5554a051
ffff4aff
66671b6b
6665b163
cccccccd
9999999a
6666666c
11111111
bbbbbbbc
6666666a
66671b69
66666666
cccccccb
99999998
bbbbbbba
66666668
66671b6a
6665b162
cccccccc
99999999
6666666b
11111110
bbbbbbbb
66666669
3333e838
33327e30
9999999a
66666667
33333339
ddddddde
88888889
33333337
3333e836
80001fff
feff7ffe

375
tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/references/caddi-01.reference_output
View File

@ -1,375 +0,0 @@
007fffe0
80000003
bffffffe
e0000007
f0000003
f8000004
fc000003
fdfffffa
ff00000f
ff7ffffa
ffbfffdf
ffdffffd
ffeffffd
fff80004
fffc0004
fffe0003
fffefffa
ffff7ff7
ffffc005
ffffe002
ffffeffd
fffff7df
fffffc03
fffffdee
fffffefe
ffffff82
ffffffba
ffffffc9
ffffffeb
ffffffe7
ffffffeb
00000001
00000005
0000001c
effffff6
0007fffd
80000009
3fffffea
20000010
10000000
08000010
04000005
02000006
01000008
0040000f
00200009
00100009
0004000f
0001ffea
0000fff0
00008006
00004005
00002007
00000ff9
000007f6
000003fe
000001ef
00000101
00000084
00000046
00000024
00000013
0000000c
00000004
00000001
00000005
00000001
0000b50b
0000b501
0000b504
0000b50c
0000b509
0000b510
0000b505
0000b50a
0000b507
0000b50e
0000b500
0000b503
0000b508
0000b50f
ffff4b03
ffff4af9
ffff4afc
ffff4b04
ffff4b01
ffff4b08
ffff4afd
ffff4b02
ffff4aff
ffff4b06
ffff4af8
ffff4afb
ffff4b00
ffff4b07
6666666d
66666663
66666666
6666666e
6666666b
66666672
66666667
6666666c
66666669
66666670
66666662
66666665
6666666a
66666671
3333333a
33333330
33333333
3333333b
33333338
3333333f
33333334
33333339
33333336
3333333d
3333332f
33333332
33333337
3333333e
0000000c
00000002
00000005
0000000d
0000000a
00000011
00000006
0000000b
00000008
0000000f
00000001
00000004
00000009
00000010
aaaaaab1
aaaaaaa7
aaaaaaaa
aaaaaab2
aaaaaaaf
aaaaaab6
aaaaaaab
aaaaaab0
aaaaaaad
aaaaaab4
aaaaaaa6
aaaaaaa9
aaaaaaae
aaaaaab5
5555555c
55555552
55555555
5555555d
5555555a
55555561
55555556
5555555b
55555558
5555555f
55555551
55555554
55555559
55555560
0000000a
00000000
00000003
0000000b
00000008
0000000f
00000009
00000006
0000000d
ffffffff
00000002
00000007
0000000e
0000b509
0000b4ff
0000b502
0000b50a
0000b507
0000b50e
0000b503
0000b508
0000b505
0000b50c
0000b4fe
0000b501
0000b506
0000b50d
00000006
fffffffc
ffffffff
00000007
00000004
0000000b
00000000
00000005
00000002
00000009
fffffffb
fffffffe
00000003
0000000a
6666666b
66666661
66666664
6666666c
66666669
66666670
66666665
6666666a
66666667
6666666e
66666660
66666663
66666668
6666666f
33333338
3333332e
33333331
33333339
33333336
3333333d
33333332
33333337
33333334
3333333b
3333332d
33333330
33333335
3333333c
5555555a
55555550
55555553
5555555b
55555558
5555555f
55555554
55555559
55555556
5555555d
5555554f
55555552
55555557
5555555e
00000008
fffffffe
00000009
00000006
0000000d
00000002
00000007
00000004
0000000b
fffffffd
00000000
00000005
0000000c
0000b50a
0000b500
0000b503
0000b50b
0000b508
0000b50f
0000b504
0000b509
0000b506
0000b50d
0000b4ff
0000b502
0000b507
0000b50e
ffff4b02
ffff4af8
ffff4afb
ffff4b03
ffff4b00
ffff4b07
ffff4afc
ffff4b01
ffff4afe
ffff4b05
ffff4af7
ffff4afa
ffff4aff
ffff4b06
6666666c
66666662
66666665
6666666d
6666666a
66666671
66666666
6666666b
66666668
6666666f
66666661
66666664
66666669
66666670
33333339
3333332f
33333332
3333333a
33333337
3333333e
33333333
33333338
33333335
3333333c
0000000d
aaaaaaa3
5555555e
0000001b
3333332e
33333331
33333336
3333333d
0000000b
00000001
00000004
0000000c
00000009
00000010
00000005
0000000a
00000007
0000000e
00000000
00000003
00000008
0000000f
aaaaaab0
aaaaaaa6
aaaaaaa9
aaaaaab1
aaaaaaae
aaaaaab5
aaaaaaaa
aaaaaaaf
aaaaaaac
aaaaaab3
aaaaaaa5
aaaaaaa8
aaaaaaad
aaaaaab4
5555555b
55555551
55555554
5555555c
55555559
55555560
55555555
5555555a
55555557
55555550
55555553
55555558
5555555f
00000009
ffffffff
00000002
0000000a
00000007
0000000e
00000003
00000008
00000005
0000000c
fffffffe
00000001
00000006

72
tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/references/caddi16sp-01.reference_output
View File

@ -1,72 +0,0 @@
003ffe00
8000007f
c000005f
dfffff9f
effffe9f
f7ffffaf
fbffff6f
fe0000ef
feffff7f
ff7fff8f
ffc0003f
ffdffe9f
fff0000f
fff8000f
fffbfeff
fffe014f
fffeffaf
ffff803f
ffffc04f
ffffdfbf
fffff07f
fffff87f
fffffbef
ffffff4f
fffffedf
ffffff5f
0000004f
ffffffef
fffffe8f
ffffff97
fffffefb
ffffff6d
0000006e
004001f0
fffffeeb
ffbfffcf
7fffff60
40000100
1ffffff0
10000030
07ffff60
000000c0
00000210
00000200
00000078
fffffef4
ffffffb2
00000051
00000029
aaaaaada
555555b5
ffffff00
00000080
03fffe00
01fffe00
00ffffc0
00800010
00200020
00100090
00080050
0003fea0
0001ff60
00010150
000081f0
00004040
00002080
000011f0
00000900
000005f0
00000350
000002f0
000000b0

19
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@ -1,19 +0,0 @@
000003fc
000001fc
000002fc
0000037c
000003bc
000003dc
000003ec
000003f4
000003f8
00000200
00000100
00000080
00000004
000002a8
00000154
00000040
00000020
00000010
00000008

586
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View File

@ -1,586 +0,0 @@
80000000
0000b503
bfff4afc
00000003
00000200
55555555
00001000
fdff7fff
fefffff9
ff7ffffa
40000000
00000006
00000020
20000000
00000020
fffdffdf
66666665
00000000
ffffbff8
00000003
fffff7fd
00000003
00200000
55555456
ffffff7c
ffff4abd
20000000
55555545
aaaaaaa3
80000000
dffffffd
33333334
00000800
15555555
2fffffff
f7feffff
00000009
ddffffff
fefffffa
c0000000
00008000
ffdf7fff
00200000
00000100
00000000
fffdfffc
00000006
00020000
40000000
55554554
ffff42fd
55555156
fffffd7f
fffffefd
00000004
00000200
00000006
00100000
aaaaaaaa
00000002
80000000
00000000
00000000
08000000
00000000
00000000
00000000
00000000
00400000
00080000
00040000
00000000
00000000
00002000
00001000
00000400
00000080
00000040
00000020
00000010
00000008
00000000
00000001
10000000
00000000
04000000
01000000
00000000
00100000
00000000
00040000
00020000
00010000
00000000
00000000
00002000
00000000
00000400
00000100
00000080
00000000
00000004
00000000
00000000
0000b505
00000005
00002405
00003104
00000004
0000a001
00001504
00000004
0000b501
00000000
00002405
00003100
00001504
00000000
0000b504
00000004
00002404
00003101
00000005
0000a000
00001505
00000001
00000005
ffff4afd
66664265
33330234
00000004
aaaa0aa9
55554054
00000004
00000001
00000000
66664265
33330230
55554054
00000000
00000004
ffff4afc
66664264
33330231
00000005
aaaa0aa8
55554055
00000001
00002405
66664265
66666667
22222224
00000006
22222223
44444446
00000004
00002403
00000000
66666665
22222222
44444444
00000002
00002404
66664264
66666666
22222223
00000005
22222222
44444445
00000003
00003104
33330234
22222224
33333334
00000004
22222220
11111114
00000004
00003100
00000000
22222224
33333330
11111114
00000000
00003104
33330234
22222224
33333330
00000004
22222220
11111114
00000000
00000004
00000004
00000006
00000004
00000006
00000002
00000006
00000004
00000002
00000000
00000004
00000002
00000004
00000002
00000004
00000004
00000006
00000002
00000004
00000002
00000004
00000002
0000a001
aaaa0aa9
22222223
22222220
00000002
aaaaaaab
00000002
00000000
0000a003
00000000
22222221
22222222
00000000
00000002
0000a000
aaaa0aa8
22222222
22222223
00000001
aaaaaaaa
00000001
00000003
00001504
55554054
44444446
11111114
00000006
00000002
55555556
00000004
00001502
00000000
44444444
11111112
55555554
00000002
00001504
55554054
44444446
11111112
00000004
00000002
55555554
00000002
00000004
00000004
00000004
00000004
00000004
00000000
00000004
00000000
00000000
00000004
00000000
00000004
00000000
00000004
00000004
00000004
00000000
00000004
00000000
00000004
00000000
0000b501
00000001
00002403
00003100
00000002
0000a003
00001502
00000000
0000b503
00000000
00002401
00003102
00001500
00000002
0000b500
00000000
00002402
00003103
00000001
0000a002
00001501
00000003
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00002405
66664265
66666665
22222224
00000004
22222221
44444444
00000004
00002401
00000000
22222221
33333332
11111110
00000002
00003100
33330230
22222222
33333333
00000001
22222222
11111111
00000003
00000005
00000005
00000005
00000004
00000004
00000001
00000004
00000004
00000001
00000000
00000005
00000000
00000004
00000000
00000004
00000004
00000004
00000001
00000005
00000000
00000005
00000001
0000a000
aaaa0aa8
22222222
22222220
00000002
aaaaaaaa
00000002
00000000
0000a002
00000000
22222220
22222222
00000000
00000002
0000a000
aaaa0aa8
22222222
22222222
00000000
aaaaaaaa
00000000
00000002
00001505
55554055
44444445
11111114
00000004
00000001
55555554
00000004
00001501
00000000
44444445
11111110
55555554
00000000
00001504
55554054
44444444
11111111
00000005
00000000
55555555
00000001
00000001
00000001
00000003
00000000
00000002
00000003
00000002
00000000
00000003
00000000
00000001
00000002
00000000
00000002
00000000
00000000
00000002
00000003
00000001
00000002
00000001
00000003
00000000
66666665
22222220
44444444
00002404
66664264
66666664
22222221
00000005
22222220
44444445
00000001
00003100
33330230
22222222
33333330
00000002
22222222
11111112
00000000
00003102
00000000
22222220
33333332
11111110
00000002
00003100
33330230
22222222
33333332
00000000
22222222
11111110
00000002
00001504
55554054
44444444
11111114
00000004
00000000
55555554
00000004
00001500
00000000
44444444
11111110
55555554
00000000
00001504
55554054
44444444
11111110
00000004
00000000
55555554
00000000
00000000
00000000
00000002
00000000
00000002
00000002
00000002
00000000
00000002
00000000
00000000
00000002
00000000
00000002
00000000
00000000
00000002
00000002
00000000
00000002
00000000
00000002
0000b504
00000004
00002404
00003104
00000004
0000a000
00001504
00000004
0000b500
00000000
00002404
00003100
00001504
00000000
0000b504
00000004
00002404
00003100
00000004
0000a000
00001504
00000000
00000004
ffff4afc
66664264
33330234
00000004
aaaa0aa8
55554054
00000004
00000000
00000000
66664264
33330230
55554054
00000000
00000004
ffff4afc
66664264
33330230
00000004
aaaa0aa8
55554054
00000000
00002404
66664264
66666666
22222224
00000006
22222222
44444446
00000004
00002402
00000000
66666664
22222222
44444444
00000002
00002404
66664264
66666666
22222222
00000004
22222222
44444444
00000002
00003101
33330231
22222223
33333330
00000002
22222223
11111112
00000000
00003103

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@ -1,374 +0,0 @@
00000200
00000004
00000000
00000007
00000003
00000006
00000009
00000004
00000000
00000005
ffbffff8
ffdffffd
00000004
00000002
fffbfff8
00000007
00000006
00000005
00000004
00000003
ffffeffa
00000006
fffffbfb
fffffdea
00000006
ffffff6a
ffffffbe
ffffffd0
00000004
00000000
00000002
00000000
00000006
0000001f
00000800
00000005
00000000
00000000
00000000
10000000
00000000
00000000
02000000
01000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00008000
00000000
00000000
00000000
00000000
00000000
00000080
00000000
00000000
00000000
00000008
00000000
00000000
00000000
00000004
0000b504
0000b505
00000005
00000004
00000001
00000000
00000005
00000000
00000001
0000b501
0000b504
00000001
00000000
00000004
ffff4afc
ffff4afd
00000005
00000004
00000009
00000000
00000005
00000000
00000009
ffff4af9
ffff4afc
00000001
00000008
00000006
66666664
66666667
00000007
00000004
00000003
00000000
00000005
00000002
00000001
66666663
66666666
00000003
00000002
00000004
33333334
33333334
00000004
00000004
00000000
00000000
00000004
00000000
00000000
33333330
33333334
00000000
00000000
00000006
00000004
00000006
00000006
00000004
00000002
00000000
00000004
00000002
00000000
00000002
00000006
00000002
00000002
00000002
aaaaaaa8
aaaaaaab
00000003
00000000
0000000b
00000000
00000001
00000002
00000009
aaaaaaab
aaaaaaaa
00000003
0000000a
00000006
55555554
55555556
00000006
00000004
00000002
00000000
00000004
00000002
00000000
55555552
55555556
00000002
00000002
00000004
00000004
00000004
00000004
00000004
00000000
00000004
00000000
00000000
00000000
00000004
00000000
00000000
00000002
0000b500
0000b503
00000003
00000000
00000003
00000000
00000001
00000002
00000001
0000b503
0000b502
00000003
00000002
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000004
66666664
66666665
00000005
00000004
00000001
00000000
00000005
00000000
00000001
66666661
66666664
00000001
00000000
00000002
33333330
33333332
00000002
00000000
00000002
00000000
00000000
00000002
00000000
33333332
33333332
00000002
00000002
00000004
55555554
55555554
00000004
00000004
00000000
00000000
00000004
00000000
00000000
55555550
55555554
00000000
00000000
00000002
00000000
00000002
00000002
00000000
00000002
00000000
00000000
00000002
00000000
00000002
00000002
00000002
00000002
00000004
0000b504
0000b504
00000004
00000004
00000000
00000000
00000004
00000000
00000000
0000b500
0000b504
00000000
00000000
00000004
ffff4afc
ffff4afc
00000004
00000004
00000008
00000000
00000004
00000000
00000008
ffff4af8
ffff4afc
00000000
00000008
00000006
66666664
66666666
00000006
00000004
00000002
00000000
00000004
00000002
00000000
66666662
66666666
00000002
00000002
00000002
33333330
33333333
00000003
00000000
00000003
00000000
00000001
00000002
00000001
00000002
00000000
00000004
00000000
33333333
33333332
00000003
00000002
00000004
00000004
00000005
00000005
00000004
00000001
00000000
00000005
00000000
00000001
00000001
00000004
00000001
00000000
00000002
aaaaaaa8
aaaaaaaa
00000002
00000000
0000000a
00000000
00000002
00000008
aaaaaaaa
aaaaaaaa
00000002
0000000a
00000004
55555554
55555555
00000005
00000001
00000000
00000005
00000000
00000001
55555551
55555554
00000001
00000000
00000002
00000000
00000003
00000003
00000000
00000003
00000000
00000001
00000002
00000001
00000003
00000002
00000003

84
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@ -1,84 +0,0 @@
ff76df58
ff76df5a
ff76df5c
ff76df5e
ff76df60
ff76df62
ff76df64
ff76df66
ff76df68
ff76df6a
ff76df6c
ff76df6e
ff76df70
ff76df72
ff76df74
ff76df76
ff76df78
ff76df7a
ff76df7c
ff76df7e
ff76df80
ff76df82
ff76df84
ff76df86
ff76df88
ff76df8a
ff76df8c
ff76df8e
ff76df90
ff76df92
ff76df94
ff76df96
ff76df98
ff76df9a
ff76df9c
ff76df9e
ff76dfa0
ff76dfa2
ff76dfa4
ff76dfa6
ff76dfa8
ff76dfaa
ff76dfac
ff76dfae
ff76dfb0
ff76dfb2
ff76dfb4
ff76dfb6
ff76dfb8
ff76dfba
ff76dfbc
ff76dfbe
ff76dfc0
ff76dfc2
ff76dfc4
ff76dfc6
ff76dfc8
ff76dfca
ff76dfcc
ff76dfce
ff76dfd0
ff76dfd2
ff76dfd4
ff76dfd6
ff76dfd8
ff76dfda
ff76dfdc
ff76dfde
ff76dfe0
ff76dfe2
ff76dfe5
ff76dfe7
ff76dfe9
ff76dfeb
ff76dfed
ff76dfef
ff76dff1
ff76dff3
ff76dff5
ff76dff7
ff76dff9
ff76dffb
ff76dffd
ff76dfff

84
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@ -1,84 +0,0 @@
ff76df57
ff76df5a
ff76df5d
ff76df5e
ff76df61
ff76df62
ff76df63
ff76df66
ff76df69
ff76df6c
ff76df6d
ff76df70
ff76df73
ff76df76
ff76df79
ff76df7c
ff76df7d
ff76df80
ff76df81
ff76df82
ff76df85
ff76df88
ff76df89
ff76df8a
ff76df8d
ff76df90
ff76df93
ff76df96
ff76df97
ff76df98
ff76df9b
ff76df9c
ff76df9d
ff76dfa0
ff76dfa1
ff76dfa4
ff76dfa5
ff76dfa8
ff76dfa9
ff76dfac
ff76dfaf
ff76dfb2
ff76dfb3
ff76dfb4
ff76dfb5
ff76dfb6
ff76dfb7
ff76dfba
ff76dfbd
ff76dfbe
ff76dfc1
ff76dfc2
ff76dfc5
ff76dfc6
ff76dfc9
ff76dfcc
ff76dfcd
ff76dfce
ff76dfcf
ff76dfd2
ff76dfd5
ff76dfd6
ff76dfd7
ff76dfda
ff76dfdb
ff76dfdc
ff76dfdf
ff76dfe2
ff76dfe3
ff76dfe6
ff76dfe8
ff76dfeb
ff76dfec
ff76dfef
ff76dff0
ff76dff3
ff76dff4
ff76dff7
ff76dff8
ff76dff9
ff76dffa
ff76dffb
ff76dffe
ff76e001

17
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@ -1,17 +0,0 @@
ff76df57
ff76df58
ff76df59
ff76df5a
ff76df5b
ff76df5c
ff76df5d
ff76df5e
ff76df61
ff76df64
ff76df67
ff76df68
ff76df6b
ff76df6e
ff76df71
ff76df74
ff76df77

18
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@ -1,18 +0,0 @@
00000015
00000409
00000209
00000109
00000089
00000049
00000029
00000019
00000011
0000000d
0000000d
0000000d
0000055d
0000000d
0000000d
0000000d
0000000d
0000000d

15
tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/references/cjalr-01.reference_output
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@ -1,15 +0,0 @@
00000009
0000000f
00000009
0000000f
00000009
0000000f
00000009
0000000f
00000009
0000000f
00000009
0000000f
0000000f
00000009
0000000f

15
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@ -1,15 +0,0 @@
00000013
00000013
00000013
00000013
00000013
00000013
00000013
00000013
00000013
00000013
00000013
00000013
00000011
00000013
00000011

17
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@ -1,17 +0,0 @@
ffffffe0
0000001f
ffffffef
fffffff7
fffffffb
fffffffd
fffffffe
00000010
00000000
00000008
00000004
00000000
00000001
ffffffea
00000015
00000000
00000002

15
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View File

@ -1,15 +0,0 @@
00004000
0001f000
fffef000
ffff7000
ffffb000
ffffd000
00000000
fffe0000
0000c000
00010000
00008000
00002000
00001000
fffea000
00015000

13
tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/references/clw-01.reference_output
View File

@ -1,13 +0,0 @@
babecafe
babecafe
babecafe
babecafe
babecafe
babecafe
babecafe
babecafe
babecafe
babecafe
babecafe
babecafe
babecafe

15
tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/references/clwsp-01.reference_output
View File

@ -1,15 +0,0 @@
babecafe
babecafe
babecafe
babecafe
babecafe
babecafe
babecafe
babecafe
babecafe
babecafe
babecafe
babecafe
babecafe
babecafe
babecafe

85
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View File

@ -1,85 +0,0 @@
80000000
7fffffff
bfffffff
dfffffff
efffffff
f7ffffff
fbffffff
fdffffff
feffffff
ff7fffff
ffbfffff
ffdfffff
ffefffff
fff7ffff
00000000
fffdffff
fffeffff
ffff7fff
ffffbfff
ffffdfff
ffffefff
fffff7ff
fffffbff
fffffdff
fffffeff
ffffff7f
ffffffbf
ffffffdf
ffffffef
fffffff7
fffffffb
fffffffd
fffffffe
40000000
20000000
10000000
08000000
04000000
02000000
01000000
00800000
00400000
00200000
00100000
00080000
00040000
00020000
00010000
00008000
00004000
00002000
00001000
00000800
00000400
00000200
00000100
00000080
00000040
00000001
0000b505
ffff4afd
66666667
33333334
00000006
aaaaaaab
55555556
00000004
0000b503
00000000
66666665
33333332
55555554
00000002
0000b504
ffff4afc
66666666
33333333
00000005
aaaaaaaa
55555555
00000020
00000010
00000008
00000003
fffbffff

14
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View File

@ -1,14 +0,0 @@
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000

582
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View File

@ -1,582 +0,0 @@
80000000
33333334
bfffffff
dfffffff
ffffffff
f7ffffff
ffffffff
fdffffff
ffffffff
ffffffff
ffbfffff
ffffffff
ffffffff
fff7ffff
fffbffff
fffdffff
ffffffff
ffff7fff
ffffbfff
ffffdfff
ffffffff
ffffffff
ffffffff
ffffffff
fffffeff
ffffff7f
ffffffbf
ffffffff
ffffffff
fffffff7
fffffffb
fffffffd
fffffffe
7fffffff
dfffffff
ffffffff
f7ffffff
fbffffff
fdffffff
feffffff
ffffffff
ffefffff
fffdffff
fffeffff
ffff7fff
ffffbfff
ffffdfff
ffffefff
fffff7ff
ffffffff
fffffdff
ffffffff
ffffffff
ffffffbf
ffffffff
ffffffff
ffffffff
ffffffff
8000b503
40000003
20000000
55555554
feffffff
fffff7ff
c1000000
10800000
fdffffff
55755554
bfffffff
fffffff9
00042000
33333332
00012000
0000c000
00002200
04001000
fffffffb
00000200
fbffffff
04000010
ffffffbf
40000000
ffff4afc
02000010
01000004
ffffffff
ffffdfff
00300000
00080003
00040006
fffeffff
aaabaaab
00001001
00100800
00020400
ffffbfff
00000085
0000b505
0000b505
fffffffd
6666f767
3333b735
0000b507
aaaabfaf
5555f557
0000b505
0000b507
0000b505
6666f765
3333b737
5555f555
0000b507
0000b505
fffffffd
6666f767
3333b737
0000b505
aaaabfaf
5555f555
0000b507
fffffffd
ffff4afd
ffff6eff
ffff7bfd
ffff4aff
ffffeaff
ffff5fff
ffff4afd
ffffffff
ffff4afd
ffff6efd
ffff7bff
ffff5ffd
ffff4aff
fffffffd
ffff4afd
ffff6eff
ffff7bff
ffff4afd
ffffeaff
ffff5ffd
ffff4aff
6666f767
ffff6eff
66666667
77777777
66666667
eeeeeeef
77777777
66666667
6666f767
66666667
66666667
77777777
77777777
66666667
6666f767
ffff6eff
66666667
77777777
66666667
eeeeeeef
77777777
66666667
3333b735
ffff7bfd
77777777
33333334
33333336
bbbbbbbf
77777776
33333334
3333b737
33333334
77777775
33333336
77777774
33333336
3333b734
ffff7bfc
77777776
33333337
33333335
bbbbbbbe
77777775
33333337
0000b507
ffff4aff
66666667
33333336
00000006
aaaaaaaf
55555556
00000006
0000b507
00000006
66666667
33333336
55555556
00000006
0000b506
ffff4afe
66666666
33333337
00000007
aaaaaaae
55555557
00000007
aaaabfaf
ffffeaff
eeeeeeef
bbbbbbbf
aaaaaaaf
aaaaaaab
ffffffff
aaaaaaaf
aaaabfab
aaaaaaab
eeeeeeef
bbbbbbbb
ffffffff
aaaaaaab
aaaabfaf
ffffeaff
eeeeeeef
bbbbbbbb
aaaaaaaf
aaaaaaab
ffffffff
aaaaaaab
5555f557
ffff5fff
77777777
77777776
55555556
ffffffff
55555556
55555556
5555f557
55555556
77777777
77777776
55555556
55555556
5555f556
ffff5ffe
77777776
77777777
55555557
fffffffe
55555557
55555557
0000b505
ffff4afd
66666667
33333334
00000006
aaaaaaaf
55555556
00000004
0000b507
00000004
66666665
33333336
55555554
00000006
0000b504
ffff4afc
66666666
33333337
00000005
aaaaaaae
55555555
00000007
0000b507
ffffffff
6666f767
3333b737
0000b507
aaaabfab
5555f557
0000b507
0000b503
0000b503
6666f767
3333b733
5555f557
0000b503
0000b507
ffffffff
6666f767
3333b733
0000b507
aaaabfab
5555f557
0000b503
0000b505
ffff4afd
66666667
33333334
00000006
aaaaaaab
55555556
00000004
0000b503
00000000
66666665
33333332
55555554
00000002
0000b504
ffff4afc
66666666
33333333
00000005
aaaaaaaa
55555555
00000003
6666f765
ffff6efd
66666667
77777775
66666667
eeeeeeef
77777777
66666665
6666f767
66666665
33333333
77777777
33333333
77777777
33333333
3333b737
ffff7bff
77777777
33333333
33333337
bbbbbbbb
77777777
33333333
0000b505
ffff4afd
66666667
33333335
00000007
aaaaaaaf
55555557
00000005
0000b507
00000005
66666665
33333337
55555555
00000007
0000b505
ffff4afd
66666667
33333337
00000005
aaaaaaaf
55555555
00000007
aaaabfaf
ffffeaff
eeeeeeef
bbbbbbbe
aaaaaaae
aaaaaaab
fffffffe
aaaaaaae
aaaabfab
aaaaaaaa
eeeeeeef
bbbbbbba
fffffffe
aaaaaaaa
aaaabfae
ffffeafe
eeeeeeee
bbbbbbbb
aaaaaaaf
aaaaaaaa
ffffffff
aaaaaaab
5555f555
ffff5ffd
77777777
77777775
55555557
ffffffff
55555557
55555555
5555f557
55555555
77777775
77777777
55555555
55555557
5555f555
ffff5ffd
77777777
77777777
55555555
ffffffff
55555555
55555557
0000b507
ffff4aff
66666667
33333337
00000007
aaaaaaab
55555557
00000007
0000b503
00000003
66666667
33333333
55555557
00000003
0000b507
ffff4aff
66666667
33333333
00000007
aaaaaaab
55555557
00000003
66666665
77777777
77777775
66666667
6666f765
ffff6efd
66666667
77777777
66666665
eeeeeeef
77777775
66666667
3333b737
ffff7bff
77777777
33333336
33333336
bbbbbbbb
77777776
33333336
3333b733
33333332
77777777
33333332
77777776
33333332
3333b736
ffff7bfe
77777776
33333333
33333337
bbbbbbba
77777777
33333333
5555f555
ffff5ffd
77777777
77777774
55555556
ffffffff
55555556
55555554
5555f557
55555554
77777775
77777776
55555554
55555556
5555f554
ffff5ffc
77777776
77777777
55555555
fffffffe
55555555
55555557
0000b507
ffff4aff
66666667
33333336
00000006
aaaaaaab
55555556
00000006
0000b503
00000002
66666667
33333332
55555556
00000002
0000b506
ffff4afe
66666666
33333333
00000007
aaaaaaaa
55555557
00000003
0000b505
fffffffd
6666f767
3333b734
0000b506
aaaabfaf
5555f556
0000b504
0000b507
0000b504
6666f765
3333b736
5555f554
0000b506
0000b504
fffffffc
6666f766
3333b737
0000b505
aaaabfae
5555f555
0000b507
fffffffd
ffff4afd
ffff6eff
ffff7bfc
ffff4afe
ffffeaff
ffff5ffe
ffff4afc
ffffffff
ffff4afc
ffff6efd
ffff7bfe
ffff5ffc
ffff4afe
fffffffc
ffff4afc
ffff6efe
ffff7bff
ffff4afd
ffffeafe
ffff5ffd
ffff4aff
6666f767
ffff6eff
66666667
77777776
66666666
eeeeeeef
77777776
66666666
6666f767
66666666
66666667
77777776
77777776
66666666
6666f766
ffff6efe
66666666
77777777
66666667
eeeeeeee
77777777
66666667
3333b737
ffff7bff
77777777
33333337
33333337
bbbbbbbb
77777777
33333337
3333b733

86
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@ -1,86 +0,0 @@
e0000000
fffff800
fffff000
ffffff80
7ffffff8
80000000
fff80000
fffffc00
dfffffe0
80000000
fff80000
fffe0000
dffffe00
ffe00000
f8000000
fff7fffc
80000000
f7ffe000
e0000000
f8000000
fbff8000
80000000
ffffbfe0
80000000
c0000000
fffffdf8
ef800000
ffffffde
e0000000
fd800000
e8000000
80000000
00000000
00000000
00000000
00000000
00000000
10000000
40000000
20000000
20000000
00000000
10000000
00000000
00000000
08000000
00000000
08000000
00010000
00000000
00004000
00200000
10000000
00000000
00400000
04000000
00002000
00008000
00000000
00100000
00400000
00800000
10000000
00080000
40000000
fff7fff0
5a828000
fd2bf400
c0000000
33333340
00000030
55800000
55555600
18000000
18000000
55555550
55555550
00000000
cccccca0
33320000
aa000000
002d4100
fd2bf000
99980000
66666666
00000050

85
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@ -1,85 +0,0 @@
fffeaaaa
003fffff
fdffffff
fdffffff
ffffff7f
fffffeff
ffffbfff
ffffffff
fffff7ff
ffefffff
ffffefff
fffffeff
ffffff7f
ffffbfff
ffffbfff
ffffffff
ffffffff
ffffdfff
ffffff7f
ffffffff
ffffffbf
ffffffff
ffffff7f
ffffffff
fffffffd
ffffffff
ffffffff
ffffffff
ffffffff
ffffffff
ffffffff
ffffffff
ffffffff
00000000
ffffe000
00002000
00000004
00000080
00000200
00000020
00200000
00000000
00000000
00000200
00000100
00000002
00000400
00000000
00002000
00000100
00000400
00000000
00000100
00000000
00000002
00000000
00000000
00000000
00000010
00000000
00000000
00000000
00000000
00000000
00000000
ffffffff
2aaaaaaa
00000005
fffffa57
00000333
00000066
00000000
00000000
00000000
feaaaaaa
00002aaa
00000002
03333333
00333333
00555555
00000000
ffffff4a
00033333
00000066
00000002

87
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@ -1,87 +0,0 @@
0003ffff
00ffffff
00017fff
001bffff
000effff
0f7fffff
1f7fffff
00007eff
03fbffff
0001feff
000007fd
1ffbffff
3ffbffff
0000fff7
03ffefff
0000fffd
007fff7f
007fffbf
000ffffb
0003ffff
07ffff7f
000007ff
00000007
000fffff
000fffff
01fffffe
00000007
0001ffff
000fffff
01ffffff
00000003
001fffff
00000000
0000001f
00400000
00800000
00800000
00080000
00000000
00000200
00000010
00000100
00000000
00000400
00000200
00000000
00000000
00000000
00000000
00000100
00000000
00000800
00000000
00000000
00000010
00000000
00000000
00000080
00000001
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
000007ff
00333333
00006666
00000000
05555555
0000aaaa
00002d40
00000000
00000000
2aaaaaaa
000aaaaa
00000000
00000000
00019999
00cccccc
0aaaaaaa
00000000
07fffa57
0ccccccc
00000000

581
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@ -1,581 +0,0 @@
d5555556
00000000
c0000000
1ffffff7
0fff4afd
6e666666
03fffffa
f2000000
00fff800
33b33333
00380000
001ffffd
000fffc0
0007ff80
0003fff9
02020001
0000fffd
40008000
ffff8afe
fffc2000
00001005
ffffc800
ffe00400
01000201
00000201
0000007f
00000081
0000001e
ffff8010
ffffffc8
00000025
ffffe002
fffffc01
bfffffbf
e0000005
78000000
fc000020
fe000007
ff000010
ff7ff7ff
bfbfffff
ffefffff
fffeb503
ffff0100
7ffff000
fbfffdff
000fffe0
000007f0
fffffff2
00000001
5fffffff
dffffffd
f000b504
f8004000
fe000020
fefffff7
01800000
00000000
ffe00020
66566666
fff6ffff
fffc0009
fffe0000
ffff0009
ffff8200
aaaa6aaa
ffffdff7
ffffefff
aaaaa6aa
00000200
ffffdeff
fffffb7f
ffff7fdf
fffffff0
5555554d
ffff4af8
fefffffd
0fffffff
3fffffe0
1ffffffe
07fe0000
04000011
f8800000
00200000
000ffffc
f0080000
00040001
00020201
e0010000
00008008
10002001
10001001
000007fb
00000088
ffff4b0d
00000003
00000000
9999999b
00000000
00016a08
999a4e9e
cccd81d1
0000b4ff
55560a5a
aaab5faf
0000b501
00000002
0000b505
999a4ea0
cccd81d3
aaab5fb1
0000b503
00000001
00016a09
999a4e9f
cccd81d2
0000b500
55560a5b
aaab5fb0
0000b502
fffe95f8
00000000
9998e496
cccc17c9
ffff4af7
5554a052
aaa9f5a7
ffff4af9
fffe95fa
ffff4afd
9998e498
cccc17cb
aaa9f5a9
ffff4afb
fffe95f9
00000001
9998e497
cccc17ca
ffff4af8
5554a053
aaa9f5a8
ffff4afa
6665b162
66671b6a
00000000
33333333
66666661
bbbbbbbc
11111111
66666663
6665b164
66666667
00000002
33333335
11111113
66666665
6665b163
66671b6b
00000001
33333334
66666662
bbbbbbbd
11111112
66666664
33327e2f
3333e837
cccccccd
00000000
3333332e
88888889
ddddddde
33333330
33327e31
33333334
cccccccf
00000002
dddddde0
33333332
33327e30
3333e838
ccccccce
00000001
3333332f
8888888a
dddddddf
33333331
ffff4b01
0000b509
9999999f
ccccccd2
00000000
5555555b
aaaaaab0
00000002
ffff4b03
00000006
999999a1
ccccccd4
aaaaaab2
00000004
ffff4b02
0000b50a
999999a0
ccccccd3
00000001
5555555c
aaaaaab1
00000003
aaa9f5a6
aaab5fae
44444444
77777777
aaaaaaa5
00000000
55555555
aaaaaaa7
aaa9f5a8
aaaaaaab
44444446
77777779
55555557
aaaaaaa9
aaa9f5a7
aaab5faf
44444445
77777778
aaaaaaa6
00000001
55555556
aaaaaaa8
5554a051
55560a59
eeeeeeef
22222222
55555550
aaaaaaab
00000000
55555552
5554a053
55555556
eeeeeef1
22222224
00000002
55555554
5554a052
55560a5a
eeeeeef0
22222223
55555551
aaaaaaac
00000001
55555553
ffff4aff
0000b507
9999999d
ccccccd0
fffffffe
55555559
aaaaaaae
00000000
ffff4b01
00000004
9999999f
ccccccd2
aaaaaab0
00000002
ffff4b00
0000b508
9999999e
ccccccd1
ffffffff
5555555a
aaaaaaaf
00000001
fffffffe
00016a06
999a4e9c
cccd81cf
0000b4fd
55560a58
aaab5fad
0000b4ff
00000000
0000b503
999a4e9e
cccd81d1
aaab5faf
0000b501
ffffffff
00016a07
999a4e9d
cccd81d0
0000b4fe
55560a59
aaab5fae
0000b500
ffff4afb
0000b503
99999999
cccccccc
fffffffa
55555555
aaaaaaaa
fffffffc
ffff4afd
00000000
9999999b
ccccccce
aaaaaaac
fffffffe
ffff4afc
0000b504
9999999a
cccccccd
fffffffb
55555556
aaaaaaab
fffffffd
6665b160
66671b68
fffffffe
33333331
6666665f
bbbbbbba
1111110f
33333333
ccccccce
00000001
dddddddf
33333331
33327e2f
3333e837
cccccccd
00000000
3333332e
88888889
ddddddde
33333330
ffff4b00
0000b508
9999999e
ccccccd1
ffffffff
5555555a
aaaaaaaf
00000001
ffff4b02
00000005
999999a0
ccccccd3
aaaaaab1
00000003
ffff4b01
0000b509
9999999f
ccccccd2
00000000
5555555b
aaaaaab0
00000002
aaa9f5a5
aaab5fad
44444443
77777776
aaaaaaa4
ffffffff
55555554
aaaaaaa6
aaa9f5a7
aaaaaaaa
44444445
77777778
55555556
aaaaaaa8
aaa9f5a6
aaab5fae
44444444
77777777
aaaaaaa5
00000000
55555555
aaaaaaa7
5554a050
55560a58
eeeeeeee
22222221
5555554f
aaaaaaaa
ffffffff
55555551
5554a052
55555555
eeeeeef0
22222223
00000001
55555553
5554a051
55560a59
eeeeeeef
22222222
55555550
aaaaaaab
00000000
55555552
ffff4afe
0000b506
9999999c
cccccccf
fffffffd
55555558
aaaaaaad
ffffffff
ffff4b00
00000003
9999999e
ccccccd1
aaaaaaaf
00000001
ffff4aff
0000b507
9999999d
ccccccd0
fffffffe
55555559
aaaaaaae
00000000
66666661
6665b162
66666665
00000000
33333333
11111111
66666663
6665b161
66671b69
ffffffff
33333332
66666660
bbbbbbbb
11111110
66666662
33327e2d
3333e835
cccccccb
fffffffe
3333332c
88888887
dddddddc
3333332e
33327e2f
33333332
cccccccd
00000000
ddddddde
33333330
33327e2e
3333e836
cccccccc
ffffffff
3333332d
88888888
dddddddd
3333332f
5554a04f
55560a57
eeeeeeed
22222220
5555554e
aaaaaaa9
fffffffe
55555550
5554a051
55555554
eeeeeeef
22222222
00000000
55555552
5554a050
55560a58
eeeeeeee
22222221
5555554f
aaaaaaaa
ffffffff
55555551
ffff4afd
0000b505
9999999b
ccccccce
fffffffc
55555557
aaaaaaac
fffffffe
ffff4aff
00000002
9999999d
ccccccd0
aaaaaaae
ffff4afe
0000b506
9999999c
cccccccf
fffffffd
55555558
aaaaaaad
ffffffff
ffffffff
00016a07
999a4e9d
cccd81d0
0000b4fe
55560a59
aaab5fae
0000b500
00000001
0000b504
999a4e9f
cccd81d2
aaab5fb0
0000b502
00000000
00016a08
999a4e9e
cccd81d1
0000b4ff
55560a5a
aaab5faf
0000b501
fffe95f7
ffffffff
9998e495
cccc17c8
ffff4af6
5554a051
aaa9f5a6
fffe95f9
ffff4afc
9998e497
cccc17ca
aaa9f5a8
ffff4afa
fffe95f8
00000000
9998e496
cccc17c9
ffff4af7
5554a052
aaa9f5a7
ffff4af9
6665b161
66671b69
ffffffff
33333332
66666660
bbbbbbbb
11111110
66666662
6665b163
66666666
00000001
33333334
11111112
66666664
6665b162
66671b6a
00000000
33333333
66666661
bbbbbbbc
11111111
66666663
33327e2e
3333e836
cccccccc
ffffffff
3333332d
88888888
dddddddd
3333332f
33327e30
7fffff00

68
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@ -1,68 +0,0 @@
ffffbfff
7fffffff
bfffffff
dfffffff
efffffff
f7ffffff
fbffffff
fdffffff
feffffff
ff7fffff
ffbfffff
ffdfffff
ffefffff
fff7ffff
fffbffff
fffdffff
fffeffff
ffff7fff
ffffdfff
ffffefff
fffff7ff
fffffbff
fffffdff
fffffeff
ffffff7f
ffffffbf
ffffffdf
ffffffef
fffffff7
fffffffb
fffffffd
fffffffe
00008000
80000000
40000000
20000000
10000000
08000000
00000020
00000010
00000008
00000004
00000002
00000001
ffefffff
00080000
aaaaaaaa
55555555
00000000
04000000
02000000
01000000
00800000
00400000
00200000
00100000
00040000
00020000
00010000
00004000
00002000
00001000
00000800
00000400
00000200
00000100
00000080
00000040

70
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@ -1,70 +0,0 @@
00000003
7fffffff
bfffffff
dfffffff
8000220c
f7ffffff
fbffffff
fdffffff
feffffff
ff7fffff
ffbfffff
ffdfffff
ffefffff
fff7ffff
fffbffff
fffdffff
fffeffff
ffff7fff
ffffbfff
ffffdfff
ffffefff
fffff7ff
fffffbff
fffffdff
fffffeff
ffffff7f
ffffffbf
ffffffdf
ffffffef
fffffff7
fffffffb
fffffffd
fffffffe
ffff7fff
80000000
40000000
20000000
10000000
08000000
04000000
00000040
00000020
00000010
00000008
00000004
00000002
00000001
aaaaaaaa
55555555
00000000
02000000
01000000
00800000
00400000
00200000
00100000
00080000
00040000
00020000
00010000
00008000
00004000
00002000
00001000
00000800
00000400
00000200
00000100
00000080
efffffff

580
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@ -1,580 +0,0 @@
7fff7fff
00000000
ffffffff
dfffffdf
1000b503
08002000
0c000000
02000800
feefffff
aa2aaaab
00440000
ffdffeff
00100006
fff7fff9
f7fbffff
00020002
fffefff6
00005000
ffffdffa
efffefff
10000800
fffffbff
ffbffdff
00000300
00000089
ffffffba
fff7ffdf
ffff4aec
04000008
00000000
ffdffffd
fffdfffe
7fffffff
bffdffff
9fffffff
fdfffff8
81000000
00880000
ffbffffb
ffd7ffff
00100800
40080000
02020000
fffefffb
00008006
ffff0afa
ffbffbff
fffff6ff
fbffff7f
80000040
00000420
80000010
99999992
fffffff7
d5555556
20200000
10000004
3b333334
ffffffff
54555555
33b33334
ffdbffff
ff6fffff
aaaeaaaa
ff7effff
04008000
04004000
55557555
ffefefff
00010400
08000200
00080100
ffffff7d
00000140
aaaaaa8b
3fffffef
ffbffff7
fffffff4
fffffffc
a0000000
57555555
32333332
fe7fffff
40040000
6666e666
ffff9fff
0000a000
ffff5afc
fffff3ff
00000408
ffeffdff
0000b584
dfffffef
fefffff7
00000004
fffdfffe
00000000
fffffff8
6666d362
33338631
0000b503
aaaa1fae
5555e053
0000b501
00000006
0000b505
6666d360
33338637
5555e051
0000b507
00000001
fffffff9
6666d363
33338636
0000b500
aaaa1faf
5555e050
0000b506
fffffff8
00000000
99992c9a
cccc79c9
ffff4afb
5555e056
aaaa1fab
ffff4af9
fffffffe
ffff4afd
99992c98
cccc79cf
aaaa1fa9
ffff4aff
fffffff9
00000001
99992c9b
cccc79ce
ffff4af8
5555e057
aaaa1fa8
ffff4afe
6666d362
99992c9a
00000000
55555553
66666661
cccccccc
33333331
66666663
6666d364
66666667
00000002
55555555
33333333
66666665
6666d363
99992c9b
00000001
55555554
66666662
cccccccd
33333332
66666664
33338631
cccc79c9
55555553
00000000
33333332
9999999f
66666662
33333330
33338637
33333334
55555551
00000006
66666660
33333336
33338630
cccc79c8
55555552
00000007
33333331
9999999e
66666661
33333337
0000b503
ffff4afb
66666661
33333332
00000000
aaaaaaad
55555550
00000002
0000b505
00000006
66666663
33333334
55555552
00000004
0000b502
ffff4afa
66666660
33333335
00000003
aaaaaaac
55555553
00000005
aaaa1fae
5555e056
cccccccc
9999999f
aaaaaaad
00000000
fffffffd
aaaaaaaf
aaaa1fa8
aaaaaaab
ccccccce
99999999
ffffffff
aaaaaaa9
aaaa1faf
5555e057
cccccccd
99999998
aaaaaaae
00000001
fffffffe
aaaaaaa8
5555e053
aaaa1fab
33333331
66666662
55555550
fffffffd
00000000
55555552
5555e055
55555556
33333333
66666664
00000002
55555554
5555e052
aaaa1faa
33333330
66666665
55555553
fffffffc
00000003
55555555
0000b501
ffff4af9
66666663
33333330
00000002
aaaaaaaf
55555552
00000000
0000b507
00000004
66666661
33333336
55555550
00000006
0000b500
ffff4af8
66666662
33333337
00000001
aaaaaaae
55555551
00000007
00000006
fffffffe
6666d364
33338637
0000b505
aaaa1fa8
5555e055
0000b507
00000000
0000b503
6666d366
33338631
5555e057
0000b501
00000007
ffffffff
6666d365
33338630
0000b506
aaaa1fa9
5555e056
0000b500
0000b505
ffff4afd
66666667
33333334
00000006
aaaaaaab
55555556
00000004
0000b503
00000000
66666665
33333332
55555554
00000002
0000b504
ffff4afc
66666666
33333333
00000005
aaaaaaaa
55555555
00000003
6666d360
99992c98
00000002
55555551
66666663
ccccccce
33333333
66666661
33333333
55555556
00000001
66666667
33333331
33338637
cccc79cf
55555555
00000000
33333336
99999999
66666666
33333330
0000b500
ffff4af8
66666662
33333331
00000003
aaaaaaae
55555553
00000001
0000b506
00000005
66666660
33333337
55555551
00000007
0000b501
ffff4af9
66666663
33333336
00000000
aaaaaaaf
55555550
00000006
aaaa1faf
5555e057
cccccccd
9999999e
aaaaaaac
00000001
fffffffc
aaaaaaae
aaaa1fa9
aaaaaaaa
cccccccf
99999998
fffffffe
aaaaaaa8
aaaa1fae
5555e056
cccccccc
99999999
aaaaaaaf
00000000
ffffffff
aaaaaaa9
5555e050
aaaa1fa8
33333332
66666661
55555553
fffffffe
00000003
55555551
5555e056
55555555
33333330
66666667
00000001
55555557
5555e051
aaaa1fa9
33333333
66666666
55555550
ffffffff
00000000
55555556
0000b506
ffff4afe
66666664
33333337
00000005
aaaaaaa8
55555555
00000007
0000b500
00000003
66666666
33333331
55555557
00000001
0000b507
ffff4aff
66666665
33333330
00000006
aaaaaaa9
55555556
00000000
6666d366
66666665
00000000
55555557
33333331
66666667
6666d361
99992c99
00000003
55555556
66666660
cccccccf
33333330
66666666
33338637
cccc79cf
55555555
00000006
33333334
99999999
66666664
33333336
33338631
33333332
55555557
00000000
66666666
33333330
33338636
cccc79ce
55555554
00000001
33333337
99999998
66666667
33333331
5555e051
aaaa1fa9
33333333
66666660
55555552
ffffffff
00000002
55555550
5555e057
55555554
33333331
66666666
00000000
55555556
5555e050
aaaa1fa8
33333332
66666667
55555551
fffffffe
00000001
55555557
0000b507
ffff4aff
66666665
33333336
aaaaaaa9
55555554
00000006
0000b501
00000002
66666667
33333330
55555556
00000000
0000b506
ffff4afe
66666664
33333331
00000007
aaaaaaa8
55555557
00000001
00000001
fffffff9
6666d363
33338630
0000b502
aaaa1faf
5555e052
0000b500
00000007
0000b504
6666d361
33338636
5555e050
0000b506
00000000
fffffff8
6666d362
33338637
0000b501
aaaa1fae
5555e051
0000b507
fffffff9
00000001
99992c9b
cccc79c8
ffff4afa
5555e057
aaaa1faa
ffff4af8
ffffffff
ffff4afc
99992c99
cccc79ce
aaaa1fa8
ffff4afe
fffffff8
00000000
99992c9a
cccc79cf
ffff4af9
5555e056
aaaa1fa9
ffff4aff
6666d363
99992c9b
00000001
55555552
66666660
cccccccd
33333330
66666662
6666d365
66666666
00000003
55555554
33333332
66666664
6666d362
99992c9a
00000000
55555555
66666663
cccccccc
33333333
66666665
33338636
cccc79ce
55555554
00000007
33333335
99999998
66666665
33333337
33338630
7fffffbf

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00000000
00000000
00000001
00000001
ffffffff
00000000
00000000
00000000
00000000
00000000
00000000
fffffd56
00000000
00000000
00000000
00000001
00000000
fffffe01
00000000
00000000
00000000
00000000
00000000
00001ff0
ffccffcd
0000003f
ff03f040
00f83e0f
fffc3c3d
0038e38e
00019999
000aaaab
fc000000
ffffffc1
00007fff
fffe0000
02aaaaab
00000001
0000003f
ffff8000
00000000
00000000
00000000
00000000
00000007
000000e3
00000092
00000000
00000081
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000333
00000000
00000000
00000000
0000aaaa
00000000
00000000
00033333
00000000
00000008
00000004
00000002
00000000
08000000
00000002
40000000
ffffffff
00000000
00000100
00000000
fffff002
00000000
fffffe01
00000000
00000040
00002aaa
00000000
fffffff1
00000000
00000000
00000020
00000000
00000001
ffffffff
00000000
00000000
00001e2b
00000000
00000000
00002d41
00000001
ffffffff
00000000
00000000
00000000
00005a82
00000001
ffffffff
00000000
00000000
00002434
00000000
00000000
00003c57
00000000
00000001
00000000
00000000
ffffe1d5
00000000
00000000
ffffd2c0
ffffffff
ffffffff
00000000
00000000
00000000
ffffa57f
00000000
00000000
00000000
00000000
ffffdbcd
00000000
00000000
ffffc3aa
000090d0
ffff6f2e
00000001
00000001
11111111
ffffffff
00000001
19999999
000090d2
ffffffff
00000001
00000002
00000001
33333333
000090d1
ffff6f2f
00000001
00000002
147ae147
ffffffff
00000001
22222222
00004868
ffffb797
00000000
00000001
08888888
00000000
00000000
0ccccccd
00004869
ffffffff
00000000
00000001
00000000
1999999a
00004868
ffffb798
00000000
00000001
0a3d70a4
00000000
00000000
11111111
00000000
00000000
00000000
00000000
00000001
00000000
00000000
00000001
00000000
ffffffff
00000000
00000000
00000000
00000003
00000000
00000000
00000000
00000000
00000001
00000000
00000000
00000002
ffff8753
000078af
00000000
ffffffff
f1c71c72
00000001
00000000
eaaaaaab
ffff8751
ffffffff
00000000
ffffffff
ffffffff
d5555556
ffff8752
000078ae
00000000
ffffffff
eeeeeeef
00000000
ffffffff
e38e38e4
000078ad
ffff8751
00000000
00000001
0e38e38e
ffffffff
00000001
15555555
000078af
ffffffff
00000000
00000001
00000001
2aaaaaab
000078ae
ffff8752
00000000
00000001
11111111
ffffffff
00000001
1c71c71c
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000001
00000000
ffffffff
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000001
00000000
ffffffff
00000000
00000000
00001e2b
00000000
00000000
00002d40
00000001
ffffffff
00000000
00000000
00000000
00005a81
00000000
00000000
00000000
00000000
00002433
00000000
00000000
00003c56
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
ffffffff
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
000090d0
ffff6f2e
00000000
00000001
11111110
ffffffff
00000001
19999999
000090d2
ffffffff
00000000
00000001
00000000
19999999
00004868
ffffb798
00000000
00000001
0a3d70a3
00000000
00000000
11111111
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000001
00000000
ffffffff
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000001
00000000
00000000
00000001
ffff8753
000078af
00000000
ffffffff
f1c71c72
00000001
ffffffff
eaaaaaab
ffff8751
ffffffff
00000000
ffffffff
ffffffff
d5555555
ffff8752
000078ae
00000000
ffffffff
eeeeeeef
00000001
ffffffff
e38e38e4
000078ad
ffff8751
00000000
00000001
0e38e38e
ffffffff
00000000
15555555
000078af
ffffffff
00000000
00000001
00000001
2aaaaaaa
000078ae
ffff8752
00000000
00000001
11111111
00000000
00000001
1c71c71c
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
ffffffff
00000000
00000000
00000000
00000001
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000001
ffffffff
00000001
00000002
00000001
33333332
000090d1
ffff6f2f
00000000
00000001
147ae147
ffffffff
00000001
22222221
00004868
ffffb797
00000000
00000000
08888888
00000000
00000000
0ccccccc
00004869
ffffffff
00000000
00000001
00000000
19999999
00004868
ffffb798
00000000
00000000
0a3d70a3
00000000
00000000
11111110
000078ad
ffff8751
00000000
00000001
0e38e38e
00000000
00000000
15555555
000078af
ffffffff
00000000
00000001
00000001
2aaaaaaa
000078ae
ffff8752
00000000
00000001
11111110
00000000
00000000
1c71c71c
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
ffffffff
00000000
00000000
00000000
00000001
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
ffffffff
00000000
00000000
00001e2b
00000000
00000000
00002d41
00000001
ffffffff
00000000
00000000
00000000
00005a82
00000001
ffffffff
00000000
00000000
00002434
00000000
00000000
00003c56
00000000
00000001
00000000
00000000
ffffe1d5
00000000
00000000
ffffd2bf
ffffffff
ffffffff
00000000
00000000
00000000
ffffa57e
ffffffff
00000001
00000000
00000000
ffffdbcc
00000000
00000000
ffffc3aa
000090d0
ffff6f2e
00000000
00000001
11111111
ffffffff
00000001
19999999
000090d2
ffffffff
00000001
00000002
00000001
33333333
000090d1
ffff6f2f
00000001
00000002
147ae147
ffffffff
00000001
22222222
00004868
ffffb797
00000000
00000000
08888888
00000000
00000000
0ccccccc
00004869
00000000
00000000
00000000

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00000000
00000000
00000001
00000001
00000000
ffffffff
00000000
00000000
00000000
00000001
00000000
00000001
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000001
3fffffff
00000000
0001536c
00000000
00000007
00000001
00000002
0000003f
00000001
2aa7ffff
33326666
0f0effff
00000000
1ffff7ff
00000001
00000000
249248db
00000002
24924922
00000001
3ffffffe
00000002
00000001
00000000
00000000
0000007f
00000055
00000008
00000000
00000000
00000000
00000aaa
00000000
00001999
0000ffff
0001ffff
00002000
00000000
000fffff
00000040
00000080
00000800
00efffff
0000016a
00000000
01000000
0fffefff
7fffffdf
00080000
0ba2e8ba
00040000
00001000
00000000
00800000
00000000
00000000
00000000
00000000
00000666
000000f0
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000001
00010000
00000001
00000000
00000000
00002aaa
00000000
00000000
00004000
00000001
ffffffff
00000001
00000000
00000000
00000000
00000000
00008000
00000001
00000001
00000000
00000000
00003333
00000000
00000000
00005555
00000000
00000001
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
ffffffff
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
0000b505
00000001
00000000
00000000
00001e2b
00000000
00000000
00002d41
00000000
ffffffff
00000001
00000000
00000000
00000000
00000000
00005a82
00000000
00000001
00000000
00000000
00002434
00000000
00000000
00003c57
00006666
66666667
000090d0
00000001
00000001
11111111
00000000
00000001
19999999
00006667
ffffffff
000090d2
00000001
00000002
00000000
00000001
33333333
00006666
000090d1
00000001
00000002
147ae147
00000000
00000001
22222222
00003333
33333334
00004868
00000000
00000001
08888888
00000000
00000000
0ccccccd
00003333
ffffffff
00004869
00000000
00000001
00000000
00000000
1999999a
00003333
00004868
00000000
00000001
0a3d70a4
00000000
00000000
11111111
00000000
00000006
00000000
00000000
00000000
00000001
00000000
00000000
00000001
00000000
ffffffff
00000000
00000000
00000000
00000000
00000000
00000003
00000000
00000000
00000000
00000000
00000001
00000000
00000000
00000002
0000aaaa
aaaaaaab
0000f15b
00000001
00000003
1c71c71c
00000001
00000001
2aaaaaaa
0000aaac
ffffffff
0000f15e
00000001
00000003
00000001
00000002
55555555
0000aaab
0000f15d
00000001
00000003
22222222
00000001
00000002
38e38e39
00005555
55555556
000078ad
00000000
00000001
0e38e38e
00000000
00000001
15555555
00005556
ffffffff
000078af
00000000
00000001
00000000
00000001
2aaaaaab
00005555
000078ae
00000000
00000001
11111111
00000000
00000001
1c71c71c
00000000
00000004
00000000
00000000
00000000
00000000
00000000
00000000
00000001
00000000
ffffffff
00000000
00000000
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000001
00000000
0000fffe
00000001
00000000
00000000
00002aaa
00000000
00000000
00003fff
00000001
ffffffff
00000001
00000000
00000000
00000000
00000000
00007fff
00000000
00000001
00000000
00000000
00003332
00000000
00000000
00005554
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
ffffffff
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
0000b503
00000000
00000000
00000000
00001e2b
00000000
00000000
00002d40
00000000
ffffffff
00000001
00000000
00000000
00000000
00000000
00005a81
00000000
00000000
00000000
00000000
00002433
00000000
00000000
00003c56
00006666
66666665
000090d0
00000000
00000001
11111110
00000000
00000001
19999999
00006667
ffffffff
000090d2
00000001
00000002
00000000
00000001
33333332
00006666
000090d1
00000000
00000001
147ae147
00000000
00000001
22222221
00003333
33333332
00004868
00000000
00000000
08888888
00000000
00000000
0ccccccc
00003333
ffffffff
00004869
00000000
00000001
00000000
00000000
19999999
00003333
00004868
00000000
00000000
0a3d70a3
00000000
00000000
11111110
0000aaaa
aaaaaaa9
0000f15b
00000001
00000003
1c71c71c
00000000
00000001
2aaaaaaa
0000aaac
ffffffff
0000f15e
00000001
00000003
00000001
00000002
55555554
0000aaab
0000f15d
00000001
00000003
15555555
00005556
ffffffff
000078af
00000000
00000001
00000000
00000001
2aaaaaaa
00005555
000078ae
00000000
00000001
11111110
00000000
00000000
1c71c71c
00000000
00000002
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
ffffffff
00000000
00000000
00000000
00000000
00000000
00000001
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
0000ffff
00000001
00000000
00000000
00002aaa
00000000
00000000
00003fff
00000001
ffffffff
00000001
00000000
00000000
00000000
00000000
00007fff
00000001
00000001
00000000
00000000
00003333
00000000
00000000
00005555
00000000
0000b504
00000000
00000000
00000000
00001e2b
00000000
00000000
00002d41
00000000
ffffffff
00000001
00000000
00000000
00000000
00000000
00005a82
00000000
00000001
00000000
00000000
00002434
00000000
00000000
00003c56
00006666
66666666
000090d0
00000000
00000001
11111111
00000000
00000001
19999999
00006667
ffffffff
000090d2
00000001
00000002
00000000
00000001
33333333
00006666
000090d1
00000001
00000002
147ae147
00000000
00000001
22222222
00003333
33333333
00004868
00000000
00000000
08888888
00000000
00000000
0ccccccc
00003333
ffffffff
38e38e38
00004869
00000000
00000001
00000000
00000000
19999999
00003333
00004868
00000000
00000001
0a3d70a3
00000000
00000000
11111111
00000000
00000005
00000000
00000000
00000000
00000000
00000000
00000000
00000001
00000000
ffffffff
00000000
00000000
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000000
00000001
00000000
00000000
00000001
0000aaaa
aaaaaaaa
0000f15b
00000001
00000003
1c71c71c
00000000
00000001
2aaaaaaa
0000aaac
ffffffff
0000f15e
00000001
00000003
00000001
00000002
55555555
0000aaab
0000f15d
00000001
00000003
22222222
00000001
00000002
38e38e38
00005555
55555555
000078ad
00000000
00000001
0e38e38e
00000000
00000000
15555555
00005556
ffffffff
000078af
00000000
00000001
00000000
00000001
2aaaaaaa
00005555
000078ae
00000000
00000001
11111111
00000000
00000001
1c71c71c
00000000
00000003
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
ffffffff
00000000
00000000
00000000
00000000
00000000
00000001
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000001
22222221
00000000
00000001
00005555
55555554
000078ad
00000000
00000001
0e38e38e
00000000
00000000
00000001
00000001
00000000
00000001

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00000002
2aaaaaab
00000000
00000040
10000101
00000000
04080001
edfffff7
00000000
00000000
00000000
666ccccd
00000000
01080001
0001999a
feffff80
aaab5556
00108001
fffbfff0
08002001
02001001
ffffc7f9
f0000000
cccccb99
00000404
ffbf8000
04100041
e0000000
aaaaaaa5
80000009
ffffffe2
00000033
00000000
fffc0000
5ffffffb
4aaaaaaa
ffff0000
c0800001
ffcccccc
00220001
00044001
000a0001
10011001
fffe0000
80000000
00202001
00001001
00000aac
fffffccc
fffffbfe
fffdfc00
ffd209fc
000000a5
ffffffb8
fffffff1
00000018
fffffff0
00000000
00000000
f0000000
00000000
00000000
ec000000
ff000000
99800000
01800000
00000000
00000000
fff80000
02000000
00000000
00020000
fffff000
fa57e000
00000a00
fffff600
00020000
00000000
000000c0
00000040
04000000
fffffffb
80000000
00000000
fc000000
06000000
ff800000
ffc00000
00000000
00140000
6a080000
00100000
08000000
00100000
00000000
fffff200
55555540
0000000c
ffffffdf
80001219
800157f1
6666d303
3333c404
00043e1e
00003c57
000078ae
0002d414
7ffea80f
00000000
666568f9
333259fa
ffff0ea4
00016a0a
7fff5d14
8000a2ec
66661dfe
33330eff
00038919
ffff8752
ffffc3a9
00021f0f
800157f1
7ffd3e09
6665f9cb
3332a264
fffbc1ee
555518ff
aaaa31fe
fffd2bf4
8002c1f7
00000000
666763d1
33340c6a
aaab9c04
fffe95fa
80020cf4
7ffdf30c
6666aece
33335767
fffc76f1
5555ce02
aaaae701
fffde0f7
6666d303
6665f9cb
d70a3d71
1eb851ec
6666666a
cccccccd
9999999a
9999999c
999a0635
00000000
0a3d70a3
51eb851e
cccccccc
ccccccce
00006c9c
ffff9364
70a3d70a
b851eb85
00000003
66666666
33333333
33333335
3333c404
3332a264
1eb851ec
28f5c290
33333338
bbbbbbbc
77777778
ccccccd0
cccd5d9c
00000000
b851eb84
c28f5c28
11111110
66666668
000090d0
ffff6f30
eb851eb8
f5c28f5c
00000004
88888888
44444444
9999999c
00043e1e
fffbc1ee
6666666a
33333338
00000024
00000004
00000018
00043e12
00000000
6666665e
3333332c
fffffff8
0000000c
00043e18
fffbc1e8
66666664
33333332
0000001e
fffffffc
fffffffe
00000012
00003c57
555518ff
cccccccd
bbbbbbbc
00000002
38e38e39
71c71c72
aaaaaaac
aaaae701
00000000
77777777
66666666
1c71c71c
55555556
555591ac
aaaa6e54
22222222
11111111
55555557
8e38e38e
c71c71c7
00000001
000078ae
aaaa31fe
9999999a
77777778
00000004
71c71c72
e38e38e4
55555558
5555ce02
00000000
eeeeeeee
cccccccc
38e38e38
aaaaaaac
aaab2358
5554dca8
44444444
22222222
aaaaaaae
1c71c71c
8e38e38e
00000002
0002d414
fffd2bf4
9999999c
ccccccd0
00000018
aaaaaaac
55555558
00000010
0002d40c
00000000
99999994
ccccccc8
55555550
00000008
0002d410
fffd2bf0
99999998
cccccccc
00000014
aaaaaaa8
55555554
0000000c
7ffea80f
8002c1f7
999a0635
cccd5d9c
00043e12
aaaae701
5555ce02
0002d40c
7ffd3e09
00000000
99989c2f
cccbf396
555463fc
00016a06
7ffdf30c
80020cf4
99995132
cccca899
0003890f
aaaa31fe
555518ff
00021f09
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
666568f9
666763d1
0a3d70a3
b851eb84
6666665e
77777777
eeeeeeee
99999994
00000000
51eb851f
8f5c28f6
bbbbbbbc
66666666
ffffdbcc
00002434
851eb852
c28f5c29
ffffffff
ddddddde
eeeeeeef
99999999
00038919
fffc76f1
00000003
00000004
0000001e
55555557
aaaaaaae
00000014
0003890f
00000000
fffffff9
fffffffa
aaaaaaa4
0000000a
00038914
fffc76ec
fffffffe
ffffffff
00000019
55555552
aaaaaaa9
0000000f
ffff8752
5555ce02
66666666
88888888
fffffffc
8e38e38e
1c71c71c
aaaaaaa8
aaaa31fe
00000000
11111112
33333334
c71c71c8
55555554
5554dca8
aaab2358
bbbbbbbc
ddddddde
55555552
e38e38e4
71c71c72
fffffffe
ffffc3a9
aaaae701
33333333
44444444
fffffffe
c71c71c7
8e38e38e
55555554
555518ff
00000000
88888889
9999999a
e38e38e4
aaaaaaaa
aaaa6e54
555591ac
ddddddde
eeeeeeef
aaaaaaa9
71c71c72
38e38e39
ffffffff
00021f0f
fffde0f7
33333335
9999999c
00000012
00000001
00000002
0000000c
00021f09
00000000
3333332f
99999996
fffffffc
00000006
00021f0c
fffde0f4
33333332
99999999
0000000f
fffffffe
ffffffff
00000009
99989c2f
00000000
3d70a3d9
eb851eba
22222224
ccccccca
ffff0294
0000fd6c
a3d70a3e
51eb851f
fffffff9
11111112
88888889
3333332f
333259fa
33340c6a
51eb851e
c28f5c28
3333332c
66666666
cccccccc
ccccccc8
cccbf396
00000000
eb851eba
5c28f5c4
66666668
66666664
ffff26c8
0000d938
1eb851ec
8f5c28f6
fffffffa
33333334
9999999a
99999996
ffff0ea4
aaab9c04
cccccccc
11111110
fffffff8
1c71c71c
38e38e38
55555550
555463fc
00000000
22222224
66666668
8e38e390
aaaaaaa8
aaa9b950
555646b0
77777778
bbbbbbbc
aaaaaaa4
c71c71c8
e38e38e4
fffffffc
00016a0a
fffe95fa
ccccccce
66666668
55555556
aaaaaaac
00000008
00016a06
00000000
ccccccca
66666664
aaaaaaa8
00000004
00016a08
fffe95f8
cccccccc
66666666
0000000a
55555554
aaaaaaaa
00000006
7fff5d14
80020cf4
00006c9c
000090d0
00043e18
555591ac
aaab2358
0002d410
7ffdf30c
00000000
ffff0294
ffff26c8
aaa9b950
00016a08
7ffea810
800157f0
ffffb798
ffffdbcc
00038914
5554dca8
aaaa6e54
00021f0c
8000a2ec
7ffdf30c
ffff9364
ffff6f30
fffbc1e8
aaaa6e54
5554dca8
fffd2bf0
80020cf4
00000000
0000fd6c
0000d938
555646b0
fffe95f8
800157f0
7ffea810
00004868
00002434
fffc76ec
aaab2358
555591ac
fffde0f4
66661dfe
6666aece
70a3d70a
eb851eb8
66666664
22222222
44444444
99999998
99995132
00000000
a3d70a3e
1eb851ec
77777778
cccccccc
ffffb798
00004868
0a3d70a4
851eb852
fffffffe
bbbbbbbc
ddddddde
33333332
33330eff
33335767
b851eb85
f5c28f5c
33333332
11111111
22222222
cccccccc
cccca899
f8000000
fffffff8
fb7ffff7
f7ffffe0

591
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@ -1,591 +0,0 @@
ffffffff
00005a81
3fffffff
00001000
fccccccc
fffffa57
00000000
00080000
00000000
ffdfffff
ffefffff
00040000
fffccccc
00000002
fffffbff
00000000
ffffdfff
fffff333
fffff999
ffffffff
00000000
ffffffff
ffffffff
ffffffff
fffffff7
00000000
ffffffff
ffffffff
ffffffff
00000000
00000000
00000000
000016a0
fffff4af
000002d4
ff555555
00002000
ffe66666
00000000
ffffffff
00000000
fffeaaaa
00000020
ffffaaaa
00000000
fffffd55
ffffffff
00000002
00000000
ffffffd5
00000015
00000000
ffffffff
ffffffff
ffffffff
00000000
00000000
20000000
00000001
00000080
ffbfffff
fff7ffff
00cccccc
00200000
00555555
00000000
00000016
00000000
0003ffff
00000000
ffffffff
00000000
00000fff
00000002
ffffffff
fffffe00
00000040
00000000
00000000
ffffffff
0000000c
ffffffff
ffffffff
ffffffff
00000000
00005a81
00000000
00000001
ffffffff
ffaaaaaa
ffd55555
00080000
00000000
00000000
00000000
00000100
ffffefff
ffffffbf
fffffaaa
0000001f
00000019
fffffff8
00000000
00000000
ffffffff
00004868
00002434
00000000
ffffc3a9
00003c57
00000000
00000000
00000000
00004868
00002434
00003c56
00000000
00000000
ffffffff
00004868
00002434
00000000
ffffc3a8
00003c56
00000000
ffffffff
00000000
ffffb798
ffffdbcc
ffffffff
00003c56
ffffc3a9
ffffffff
ffffffff
00000000
ffffb798
ffffdbcc
ffffc3a9
ffffffff
ffffffff
00000000
ffffb798
ffffdbcc
ffffffff
00003c56
ffffc3a9
ffffffff
00004868
ffffb798
28f5c28f
147ae148
00000002
dddddddd
22222222
00000001
00004867
00000000
28f5c28f
147ae147
22222221
00000000
00004868
ffffb797
28f5c28f
147ae147
00000002
dddddddd
22222222
00000001
00002434
ffffdbcc
147ae148
0a3d70a4
00000001
eeeeeeee
11111111
00000000
00002433
00000000
147ae147
0a3d70a3
11111111
00000000
00002434
ffffdbcb
147ae147
0a3d70a3
00000001
eeeeeeee
11111111
00000000
00000000
ffffffff
00000002
00000001
00000000
fffffffe
00000002
00000000
00000000
00000000
00000002
00000001
00000001
00000000
00000000
ffffffff
00000002
00000001
00000000
fffffffd
00000001
00000000
ffffc3a9
00003c56
dddddddd
eeeeeeee
fffffffe
1c71c71c
e38e38e3
fffffffe
ffffc3a9
00000000
ddddddde
eeeeeeef
e38e38e4
ffffffff
ffffc3a9
00003c56
ddddddde
eeeeeeef
fffffffe
1c71c71c
e38e38e3
ffffffff
00003c57
ffffc3a9
22222222
11111111
00000002
e38e38e3
1c71c71c
00000001
00003c56
00000000
22222221
11111110
1c71c71c
00000000
00003c56
ffffc3a9
22222222
11111111
00000001
e38e38e3
1c71c71c
00000001
00000000
ffffffff
00000001
00000000
00000000
fffffffe
00000001
00000000
00000000
00000000
00000001
00000000
00000001
00000000
00000000
ffffffff
00000001
00000000
00000000
fffffffe
00000001
00000000
00000000
ffffffff
00004867
00002433
00000000
ffffc3a9
00003c56
00000000
00000000
00000000
00004867
00002433
00003c56
00000000
00000000
ffffffff
00004867
00002433
00000000
ffffc3a9
00003c56
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00004868
ffffb798
28f5c28f
147ae147
00000002
ddddddde
22222221
00000001
00004867
00000000
00000000
147ae147
0a3d70a3
11111110
00000000
00002433
ffffdbcc
147ae147
0a3d70a3
00000000
eeeeeeee
11111110
00000000
00000000
ffffffff
00000002
00000001
00000000
fffffffe
00000001
00000000
00000000
00000000
00000001
00000000
00000001
00000000
00000000
ffffffff
00000001
00000000
00000000
fffffffe
00000001
00000000
ffffc3a8
00003c56
dddddddd
eeeeeeee
fffffffd
1c71c71c
e38e38e3
fffffffe
ffffc3a9
00000000
ddddddde
eeeeeeef
e38e38e3
ffffffff
ffffc3a9
00003c56
dddddddd
eeeeeeee
fffffffe
1c71c71c
e38e38e3
fffffffe
00003c56
ffffc3a9
22222222
11111111
00000001
e38e38e3
1c71c71c
00000001
00003c56
00000000
22222221
11111110
1c71c71b
00000000
00003c56
ffffc3a9
22222221
11111110
00000001
e38e38e3
1c71c71c
00000000
00000000
ffffffff
00000001
00000000
00000000
ffffffff
00000001
00000000
00000000
00000000
00000001
00000000
00000000
00000000
00000000
ffffffff
00000001
00000000
00000000
fffffffe
00000000
00000000
28f5c28e
147ae146
22222221
00000000
00004867
ffffb798
28f5c28e
147ae147
00000001
ddddddde
22222221
00000001
00002434
ffffdbcc
147ae147
0a3d70a3
00000001
eeeeeeef
11111110
00000000
00002433
00000000
147ae146
0a3d70a3
11111110
00000000
00002433
ffffdbcc
147ae147
0a3d70a3
00000000
eeeeeeef
11111110
00000000
00003c56
ffffc3a9
22222221
11111111
00000001
e38e38e4
1c71c71c
00000001
00003c56
00000000
22222221
11111110
1c71c71b
00000000
00003c56
ffffc3a9
22222221
11111110
00000001
e38e38e3
1c71c71b
00000000
00000000
ffffffff
00000000
00000000
00000000
ffffffff
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
ffffffff
00000000
00000000
00000000
ffffffff
00000000
00000000
00000000
ffffffff
00004868
00002434
00000000
ffffc3a9
00003c56
00000000
00000000
00000000
00004867
00002433
00003c56
00000000
00000000
ffffffff
00004867
00002433
00000000
ffffc3a9
00003c56
00000000
ffffffff
00000000
ffffb797
ffffdbcb
ffffffff
00003c56
ffffc3a9
ffffffff
ffffffff
00000000
ffffb798
ffffdbcc
ffffc3a9
ffffffff
ffffffff
00000000
ffffb798
ffffdbcc
ffffffff
00003c56
ffffc3a9
ffffffff
00004868
ffffb798
28f5c28f
147ae147
00000002
ddddddde
22222222
00000001
00004867
00000000
28f5c28e
147ae147
22222221
00000000
00004867
ffffb798
28f5c28f
147ae147
00000001
dddddddd
22222221
00000001
00002434
ffffdbcc
147ae147
0a3d70a3
00000001
eeeeeeef
11111111
00000000
00002433
00080000
00000020
ffffffff
ffff9999

654
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@ -1,654 +0,0 @@
0000aaaa
d5555555
00000100
00000000
fffffff0
00000000
fffffc0f
00000001
fffffffe
0007fbff
000001ff
554aaaaa
55500000
fffffbff
c000ffff
00000000
fffffffb
0000b503
00000002
fffffff9
0000b504
aaaaad55
fffffffe
fffeffff
03fffffb
66666632
00000002
66666658
00000005
efffffff
ffff4afd
00000003
f7ffffff
7ff7fffe
fffffffe
ffffffff
ffffffff
ff000001
ff800003
ffffffc0
ffe1ffff
fffffffe
fffffeff
fffff7ff
ffffffff
ffffffff
ffffffff
ffffdfff
ffffffff
fffff7ff
fffffdff
fffffeff
ffffffff
ffffffbf
ffffffdf
fffffffd
fffffffd
00000040
00000400
08000000
ffff7fff
ffffffbf
01555555
00000000
fffffffe
000ccccc
00000000
0002aaaa
00015555
00000800
fffffdff
00000000
00000000
00000000
ffffffff
ffffffff
00000019
00000000
fffffffd
00000000
00000000
00000000
ffffff80
00000001
00040000
00000000
00000001
002aaaaa
003ffdff
001fffef
00000040
0001ffff
00000000
00002aaa
00000000
00000000
00000000
00000000
00000000
00000000
00000007
00000000
00000000
00000000
00000000
00004868
00002434
00000000
000078ae
00003c57
00000000
00000000
00000000
00000000
00004868
00002434
000078ad
00003c56
00000000
00000000
00000000
00004868
00002434
00000000
000078ad
00003c56
00000000
ffffffff
ffffffff
ffffffff
ffffb798
ffffdbcc
ffffffff
ffff8753
ffffc3a9
ffffffff
ffffffff
00000000
ffffffff
ffffb798
ffffdbcc
ffff8753
ffffc3a9
ffffffff
ffffffff
ffffffff
ffffb798
ffffdbcc
ffffffff
ffff8753
ffffc3a9
ffffffff
00006666
00000000
00004868
28f5c28f
147ae148
00000002
44444444
22222222
00000001
00006665
00000000
00004867
28f5c28f
147ae147
44444443
22222221
00000000
00006666
00004868
28f5c28f
147ae147
00000002
44444444
22222222
00000001
00003333
00000000
00002434
147ae148
0a3d70a4
00000001
22222222
11111111
00000000
00003332
00000000
00002433
147ae147
0a3d70a3
22222222
11111111
00000000
00003333
00002434
147ae147
0a3d70a3
00000001
22222222
11111111
00000000
00000000
00000000
00000000
00000002
00000001
00000000
00000004
00000002
00000000
00000000
00000000
00000000
00000002
00000001
00000003
00000001
00000000
00000000
00000000
00000002
00000001
00000000
00000003
00000001
00000000
ffffaaaa
ffffffff
ffffc3a9
dddddddd
eeeeeeee
fffffffe
c71c71c7
e38e38e3
fffffffe
ffffaaab
00000000
ffffc3a9
ddddddde
eeeeeeef
c71c71c7
e38e38e4
ffffffff
ffffaaab
ffffc3a9
ddddddde
eeeeeeef
fffffffe
c71c71c7
e38e38e3
ffffffff
00005555
00000000
00003c57
22222222
11111111
00000002
38e38e39
1c71c71c
00000001
00005554
00000000
00003c56
22222221
11111110
38e38e38
1c71c71c
00000000
00005555
00003c56
22222222
11111111
00000001
38e38e39
1c71c71c
00000001
00000000
00000000
00000000
00000001
00000000
00000000
00000002
00000001
00000000
00000000
00000000
00000000
00000001
00000000
00000002
00000001
00000000
00000000
00000000
00000001
00000000
00000000
00000002
00000001
00000000
00000000
00000000
00000000
00004867
00002433
00000000
000078ac
00003c56
00000000
00000000
00000000
00000000
00004867
00002433
000078ac
00003c56
00000000
00000000
00000000
00004867
00002433
00000000
000078ac
00003c56
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00006666
00000000
00004868
28f5c28f
147ae147
00000002
44444443
22222221
00000001
00006665
00000000
00004867
28f5c28e
147ae146
44444442
22222221
00000000
00006665
00004867
28f5c28e
147ae147
00000001
44444443
22222221
00000001
00003333
00000000
00002434
147ae147
0a3d70a3
00000001
22222221
11111110
00003332
00000000
00002433
147ae146
0a3d70a3
22222221
11111110
00000000
00003332
00002433
147ae147
0a3d70a3
ffffffff
ffffffff
00000000
ffffffff
ffffb798
ffffdbcc
ffff8752
ffffc3a9
ffffffff
ffffffff
ffffffff
ffffb798
ffffdbcc
ffffffff
ffff8752
ffffc3a9
ffffffff
00006666
00000000
00004868
28f5c28f
147ae147
00000002
44444444
22222222
00000001
00006665
00000000
00004867
28f5c28e
147ae147
44444443
22222221
00000000
00006665
00004867
28f5c28f
147ae147
00000001
44444443
22222221
00000001
00003333
00000000
00002434
147ae147
0a3d70a3
00000001
22222222
11111111
00000000
00003332
00000000
00002433
147ae147
0a3d70a3
22222221
11111110
00000000
00003332
00002433
147ae147
0a3d70a3
00000000
22222221
11111110
00000000
00000000
00000000
00000000
00000002
00000001
00000000
00000003
00000001
00000000
00000000
00000000
00000000
00000001
00000000
00000003
00000001
00000000
00000000
00000000
00000001
00000000
00000000
00000003
00000001
00000000
ffffaaaa
ffffffff
ffffc3a8
dddddddd
eeeeeeee
fffffffd
c71c71c6
e38e38e3
fffffffe
ffffaaab
00000000
ffffc3a9
ddddddde
eeeeeeef
c71c71c7
e38e38e3
ffffffff
ffffaaaa
ffffc3a9
dddddddd
eeeeeeee
fffffffe
c71c71c6
e38e38e3
fffffffe
00005555
00000000
00003c56
22222222
11111111
00000001
38e38e38
1c71c71c
00000001
00005554
00000000
00000000
00003c56
22222221
11111110
38e38e38
1c71c71b
00000000
00005554
00003c56
22222221
11111110
00000001
38e38e38
1c71c71c
00000000
00000000
00000000
00000000
00000001
00000000
00000000
00000002
00000001
00000000
00000000
00000000
00000000
00000001
00000000
00000001
00000000
00000000
00000000
00000000
00000001
00000000
00000000
00000001
00000000
00000000
00000000
22222221
11111110
00000000
00005555
00000000
00003c56
fffffffe
22222221
11111111
00000001
38e38e38
1c71c71c
00000001
00005554
00000000
00003c56
22222221
11111110
38e38e37
1c71c71b
00000000
00005554
00003c56
22222221
11111110
00000001
38e38e37
1c71c71b
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000001
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000001
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000001
00000000
00000000
00000000
00000000
00000000
00004868
00002434
00000000
000078ad
00003c56
00000000
00000000
00000000
00000000
00004867
00002433
000078ad
00003c56
00000000
00000000
00000000
00004867
00002433
00000000
000078ad
00003c56
ffffffff
ffffffff
ffffffff
ffffb797
ffffdbcb
ffffffff
ffff8752
ffffc3a9
000bffff
59999997
00000004

724
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@ -1,724 +0,0 @@
00000000
00003fff
fff0003e
00000000
077fffff
0000001e
fbffffbf
00000000
0000fefe
ff7fffde
33266665
0000003f
fbf03ffe
0000b4fd
00007ffd
3332cccc
00000010
0000fffd
003fffef
00000012
ff7ff006
00000004
ffffdbfe
ffff7dfe
0000007f
fffff77e
fffffdbe
fffffede
00000012
0003ffff
0000b504
ffffffdc
0000001f
7ffdfffe
b3fffffe
dffff1fe
77fffffe
00000000
0000fdfe
feff00fe
ffbffffa
ffdf800e
00ffefff
00000007
000fffdf
1fffdfff
00000000
ffffedfe
666664cc
ff7fff7e
7ffffff6
ffffffb6
0000003f
000000ff
effffffd
00100000
15555555
00000080
07efffff
03bfffff
01ffffff
0000005a
003fffff
000aaaaa
00000200
00000200
00000200
00002000
00004000
00003f7f
00000666
00000555
000007fd
00000000
000000aa
0000007f
00000000
00000000
00000000
00000001
00000000
00000003
00080000
00000000
01feffff
00000000
00000000
00003ff7
00000000
00000000
00000000
000001ff
00000000
0000000f
00000000
00000000
00000000
00000000
00000001
00000000
00000000
00006666
00003333
00000000
0000aaaa
00005555
00000000
00000000
00000000
00000000
00006666
00003333
0000aaaa
00005555
00000000
00000000
00000000
00006666
00003333
00000000
0000aaaa
00005555
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00004868
00002434
00000000
000078ae
00003c57
00000000
00000000
00000000
00000000
00004868
00002434
000078ad
00003c56
00000000
00000000
00000000
00004868
00002434
00000000
000078ad
00003c56
00000000
00006666
00000000
00004868
28f5c28f
147ae148
00000002
44444444
22222222
00000001
00006665
00000000
00004867
28f5c28f
147ae147
44444443
22222221
00000000
00006666
00004868
28f5c28f
147ae147
00000002
44444444
22222222
00000001
00003333
00002434
147ae148
0a3d70a4
00000001
22222222
11111111
00000000
00003332
00000000
00002433
147ae147
0a3d70a3
22222222
11111111
00000000
00003333
00002434
147ae147
0a3d70a3
00000001
22222222
11111111
00000000
00000000
00000000
00000000
00000002
00000001
00000000
00000004
00000002
00000000
00000000
00000000
00000000
00000002
00000001
00000003
00000001
00000000
00000000
00000000
00000002
00000001
00000000
00000003
00000001
00000000
0000aaaa
00000000
000078ae
44444444
22222222
00000004
71c71c72
38e38e39
00000002
0000aaa9
00000000
000078ac
44444443
22222221
71c71c70
38e38e38
00000001
0000aaaa
000078ad
44444444
22222222
00000003
71c71c71
38e38e38
00000002
00005555
00000000
00003c57
22222222
11111111
00000002
38e38e39
1c71c71c
00000001
00005554
00000000
00003c56
22222221
11111110
38e38e38
1c71c71c
00000000
00005555
00003c56
22222222
11111111
00000001
38e38e39
1c71c71c
00000001
00000000
00000000
00000000
00000001
00000000
00000000
00000002
00000001
00000000
00000000
00000000
00000001
00000000
00000002
00000001
00000000
00000000
00000000
00000001
00000000
00000000
00000002
00000001
00000000
00000000
00000000
00000000
00006665
00003332
00000000
0000aaa9
00005554
00000000
00000000
00000000
00000000
00006665
00003332
0000aaa9
00005554
00000000
00000000
00000000
00006665
00003332
00000000
0000aaa9
00005554
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00004867
00002433
00000000
000078ac
00003c56
00000000
00000000
00000000
00000000
00004867
00002433
000078ac
00003c56
00000000
00000000
00000000
00004867
00002433
00000000
000078ac
00003c56
00000000
00006666
00000000
00004868
28f5c28f
147ae147
00000002
44444443
22222221
00000001
00006665
00000000
00004867
28f5c28e
147ae146
44444442
22222221
00000000
00006665
00004867
28f5c28e
147ae147
00000001
44444443
22222221
00000001
00003333
00000000
00002434
147ae147
0a3d70a3
00000001
22222221
11111110
00000000
00003332
00000000
00002433
147ae146
0a3d70a3
22222221
11111110
00000000
00003332
00002433
147ae147
0a3d70a3
00000000
22222221
11111110
00000000
0000aaaa
00000000
000078ad
44444443
22222222
00000003
71c71c70
38e38e38
00000002
0000aaa9
00000000
000078ac
44444442
22222221
71c71c6f
38e38e37
00000001
0000aaa9
000078ad
44444443
22222221
00000001
00005554
00000000
00003c56
22222221
11111110
38e38e37
1c71c71b
00000000
00005554
00003c56
22222221
11111110
00000001
38e38e37
1c71c71b
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000001
00000000
00000000
00000000
00000000
00000000
00000000
00000001
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000001
00000000
00000000
00000000
00000000
00000000
00006666
00003333
00000000
0000aaaa
00005555
00000000
00000000
00000000
00000000
00006665
00003332
0000aaa9
00005554
00000000
00000000
00000000
00006665
00003332
00000000
0000aaa9
00005554
00000000
00000000
00000000
00000000
00004868
00002434
00000000
000078ad
00003c56
00000000
00000000
00000000
00000000
00004867
00002433
000078ad
00003c56
00000000
00000000
00000000
00004867
00002433
00000000
000078ad
00003c56
00000000
00006666
00000000
00004868
28f5c28f
147ae147
00000002
44444444
22222222
00000001
00006665
00000000
00004867
28f5c28e
147ae147
44444443
22222221
00000000
00006665
00004867
28f5c28f
147ae147
00000001
44444443
22222221
00000001
00003333
00000000
00002434
147ae147
0a3d70a3
00000001
22222222
11111111
00000000
00003332
00000000
00002433
00005555
147ae147
0a3d70a3
22222221
22222221
11111110
00000000
00003332
00002433
147ae147
0a3d70a3
00000000
22222221
11111110
00000000
00000000
00000000
00000000
00000002
00000001
00000000
00000003
00000001
00000000
00000000
00000000
00000000
00000001
00000000
00000003
00000001
00000000
00000000
00000000
00000001
00000000
00000000
00000003
00000001
00000000
0000aaaa
00000000
000078ad
44444444
22222222
00000003
71c71c71
38e38e39
00000002
0000aaa9
00000000
000078ac
44444443
22222221
71c71c70
38e38e37
00000001
0000aaa9
000078ad
44444443
22222221
00000003
71c71c70
38e38e38
00000001
00005555
00000000
00003c56
22222222
11111111
00000001
38e38e38
1c71c71c
00000001
00005554
00000000
00003c56
22222221
11111110
38e38e38
1c71c71b
00000000
00005554
00003c56
22222221
11111110
00000001
38e38e38
1c71c71c
00000000
00000000
00000000
00000000
00000001
00000000
00000000
00000002
00000001
00000000
00000000
00000000
00000000
00000001
00000000
00000001
00000000
00000000
00000000
00000000
00000001
00000000
00000000
00000001
00000000
00000000
00000003
71c71c70
00001fff
38e38e38
00000001
00000000
00003c56
11111111
00000001
38e38e38
1c71c71c
bff9fffe
0006ffff
54aaaaa9

586
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@ -1,586 +0,0 @@
0000b503
00000800
00000000
00000000
fffffeff
ff7fffff
03333326
04000000
00000400
ffffffef
00000002
fff003ff
00000000
00032668
00000004
00000000
ffffbffe
00000005
00000000
fffffb07
00000000
000003fe
00000060
fffffffd
fffffffb
00000020
ffffffee
00000008
00000008
fffffffc
ffffffff
00000000
ffff3ffe
ffffffff
ffffffdf
fdffffff
feffffff
ffbfffff
ffdfffff
ffefffff
ffff8913
ffff7fff
fffffffb
ffffffff
ffffffff
fffff7ff
fffffbff
fffffdff
ffffffbf
ffffffdf
fffffff7
fffffffb
fffffffd
fffffffe
00000100
eaaaaaaa
ffffffdf
ffff4afc
00000010
0000b505
ffff4afc
00266667
ffeaaaaa
00000020
00000007
00000002
00006667
00000004
00000000
00000000
00000000
00000000
ffffffff
ffffffff
fffffff9
00000008
00000000
00000005
00000000
00000000
00000000
00000000
000000c1
20000000
00000000
00000000
01000000
00800000
00000000
00200000
00080000
00000000
00000001
00000010
00000200
00000000
00000001
00000001
00000000
00000002
0000b505
0000b505
00000003
0000b505
0000b505
00000001
00000002
0000b505
0000b505
0000b505
0000b505
00000001
00000001
00000001
0000b505
0000b505
00000001
0000b505
0000b505
00000000
ffff4afd
00000000
ffff4afd
ffff4afd
ffffffff
ffff4afd
ffff4afd
fffffffd
00000000
ffff4afd
ffff4afd
ffff4afd
ffff4afd
ffffffff
ffff4afd
ffff4afd
ffff4afd
ffff4afd
fffffffc
ffff4afd
ffff4afd
ffffffff
00008257
000039f1
00000000
33333333
00000001
11111112
11111111
00000003
000039f1
66666667
00000002
00000003
11111113
00000001
00005e23
00005e23
00000001
00000001
00000004
11111111
11111112
00000001
0000412c
00001cf9
33333334
00000000
00000004
33333334
33333334
00000000
00001cf9
33333334
33333334
00000002
33333334
00000000
00008994
00008994
33333334
00000001
00000000
33333334
33333334
00000001
00000006
00000006
00000006
00000006
00000000
00000006
00000006
00000002
00000006
00000006
00000006
00000006
00000006
00000000
00000006
00000006
00000006
00000006
00000001
00000006
00000006
00000000
ffff570c
ffffcfb8
aaaaaaab
dddddddf
ffffffff
00000000
aaaaaaab
ffffffff
ffffcfb8
aaaaaaab
aaaaaaab
dddddddd
ffffffff
ffffffff
ffff9363
ffff9363
aaaaaaab
ddddddde
00000000
aaaaaaab
00000000
ffffffff
0000a8f5
00003049
55555556
22222222
00000002
00000001
00000000
00000002
00003049
55555556
55555556
22222224
00000002
00000000
00006c9e
00006c9e
55555556
22222223
00000001
00000000
00000001
00000002
00000004
00000004
00000004
00000004
00000004
00000004
00000004
00000000
00000004
00000004
00000004
00000004
00000004
00000000
00000004
00000004
00000004
00000004
00000004
00000004
00000004
00000001
0000b503
00000000
0000b503
0000b503
00000001
0000b503
0000b503
00000003
00000000
0000b503
0000b503
0000b503
0000b503
00000001
0000b503
0000b503
0000b503
0000b503
00000004
0000b503
0000b503
00000001
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00008255
000039ef
66666665
33333331
00000005
11111110
1111110f
00000001
000039ef
33333333
33333333
00000001
33333333
00000001
00008993
00008993
33333333
00000000
00000004
33333333
33333333
00000000
00000005
00000005
00000005
00000005
00000005
00000005
00000005
00000001
00000005
00000005
00000005
00000005
00000005
00000001
00000005
00000005
00000005
00000005
00000000
00000005
00000005
00000002
ffff570b
ffffcfb7
aaaaaaaa
ddddddde
fffffffe
ffffffff
00000000
fffffffe
ffffcfb7
aaaaaaaa
aaaaaaaa
dddddddc
fffffffe
00000000
ffff9362
ffff9362
aaaaaaaa
dddddddd
ffffffff
00000000
ffffffff
fffffffe
0000a8f4
00003048
55555555
22222221
00000001
00000000
55555555
00000001
00003048
55555555
55555555
22222223
00000001
00000001
00006c9d
00006c9d
55555555
22222222
00000000
55555555
00000000
00000001
00000003
00000003
00000003
00000003
00000003
00000003
00000003
00000003
00000003
00000003
00000003
00000003
00000003
00000001
00000003
00000003
00000003
00000003
00000003
00000003
00000003
00000000
66666665
00000000
00000001
11111111
00000001
00005e21
00005e21
66666665
33333332
00000002
1111110f
11111110
00000002
0000412a
00001cf7
33333332
33333332
00000002
33333332
33333332
00000002
00001cf7
33333332
33333332
00000000
33333332
00000000
00008992
00008992
33333332
33333332
00000003
33333332
33333332
00000002
0000a8f3
00003047
55555554
22222220
00000000
55555554
55555554
00000000
00003047
55555554
55555554
22222222
00000000
00000000
00006c9c
00006c9c
55555554
22222221
00000004
55555554
55555554
00000000
00000002
00000002
00000002
00000002
00000002
00000002
00000002
00000002
00000002
00000002
00000002
00000002
00000002
00000000
00000002
00000002
00000002
00000002
00000002
00000002
00000002
00000002
0000b504
00000001
0000b504
0000b504
00000002
0000b504
0000b504
00000000
00000001
0000b504
0000b504
0000b504
0000b504
00000000
00000000
00000000
0000b504
0000b504
00000000
0000b504
0000b504
00000002
ffff4afc
ffffffff
ffff4afc
ffff4afc
fffffffe
ffff4afc
ffff4afc
00000000
ffffffff
ffff4afc
ffff4afc
ffff4afc
ffff4afc
00000000
00000000
00000000
ffff4afc
ffff4afc
00000000
ffff4afc
ffff4afc
fffffffe
00008256
000039f0
66666666
33333332
00000000
11111111
11111110
00000002
000039f0
66666666
00000001
00000002
11111112
00000000
00005e22
00005e22
00000000
00000000
00000003
11111110
11111111
00000000
0000412b
00001cf8
33333333
33333333
00000003
33333333
33333333
00000003
00001cf8
fbffffff
fffdffff
01ffffff
fffffff9

725
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00000020
33333332
00000000
00000000
0ffc0000
00020000
00000000
00000000
00000003
007fffe0
00000010
fffffffb
ff7fffff
0000b503
fbffffff
ffdfffff
00000000
00004000
0000000c
00000000
00000ff8
20000000
00010000
000000c0
00000400
00000001
33333332
ffffffbf
00000000
ffff7fff
00000001
00000400
001fffff
000001ff
0000a9bb
f7ffffff
fdffffff
32333335
00000005
0000000d
fff7ffff
fffdffff
001fe000
00000009
01fff800
00000003
fffffdff
0000000f
00000f7f
ffffffef
00001ffe
55555554
00000020
1fff7fff
0000000b
00000002
00400000
01333332
00000005
00000010
003ff7ff
00000000
00000080
00000100
0001ffff
0000ff7f
00007ff7
00000000
00001fdf
00000004
000003ff
00000067
00000000
00000008
00000004
00000003
00000000
00000000
80000000
40000000
10000000
00002160
00000000
01000000
00000000
00200000
00080000
00040000
00004000
00002000
00001000
00000800
00000002
00000040
00000000
00000000
00004afb
00010000
00010000
00000004
00010000
00010000
00000000
00000002
00010000
00004afd
00010000
00010000
00010000
00010000
00000000
00000001
00004afc
00010000
00010000
00000001
00010000
00010000
00000001
00000001
00000000
00000001
00000001
00000001
00000001
00000001
00000001
00000001
00000001
00000001
00000001
00000001
00000001
00000001
00000001
00000001
00000001
00000001
00000001
00000001
00000001
00000001
00000001
00000001
0000b505
00000000
00000000
0000b505
0000b505
00000003
0000b505
0000b505
00000001
0000b505
0000b505
00000002
0000b505
0000b505
0000b505
0000b505
00000001
0000b505
00000001
0000b505
0000b505
00000001
0000b505
0000b505
00000000
00006667
00000000
00008257
00000000
33333333
00000001
66666667
11111111
00000003
00003335
66666667
000039f1
00000002
00000003
66666667
11111113
00000001
0000cccd
00005e23
00000001
00000001
00000004
66666667
11111112
00000001
00003334
00000000
0000412c
33333334
00000000
00000004
33333334
33333334
00000000
0000999a
33333334
00001cf9
33333334
00000002
33333334
33333334
00000000
00006667
00008994
33333334
00000001
00000000
33333334
33333334
00000001
00000006
00000000
00000006
00000006
00000006
00000000
00000006
00000006
00000002
00000006
00000006
00000006
00000006
00000006
00000006
00000006
00000000
00000006
00000006
00000006
00000006
00000001
00000006
00000006
00000000
0000aaab
00000000
00009ce4
44444444
1111110f
00000003
00000000
55555555
00000003
00000003
aaaaaaab
00006091
44444446
11111115
00000002
00000003
00000001
00005556
00002437
44444445
11111112
00000001
00000001
00000001
00000000
00005556
00000000
0000a8f5
55555556
22222222
00000002
55555556
00000000
00000002
00000002
55555556
00003049
55555556
22222224
55555556
00000002
00000000
0000aaab
00006c9e
55555556
22222223
00000001
55555556
00000001
00000002
00000004
00000000
00000004
00000004
00000004
00000004
00000004
00000004
00000000
00000004
00000004
00000004
00000004
00000004
00000004
00000004
00000000
00000004
00000004
00000004
00000004
00000004
00000004
00000004
00000001
0000fffe
00000000
00004af9
0000fffe
0000fffe
00000002
0000fffe
0000fffe
00000002
00000000
0000fffe
00004afb
0000fffe
0000fffe
0000fffe
0000fffe
00000000
0000fffe
00004afa
0000fffe
0000fffe
00000004
0000fffe
0000fffe
00000002
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
0000b503
00000000
0000b503
0000b503
0000b503
00000001
0000b503
0000b503
00000003
0000b503
0000b503
00000000
0000b503
0000b503
0000b503
0000b503
00000001
0000b503
0000b503
0000b503
0000b503
00000004
0000b503
0000b503
00000001
00006665
00000000
00008255
66666665
33333331
00000005
66666665
1111110f
00000001
00003333
66666665
000039ef
00000000
00000001
66666665
11111111
00000001
0000cccb
00005e21
66666665
33333332
00000002
66666665
11111110
00000002
00003332
00000000
0000412a
33333332
33333332
00000002
33333332
33333332
00000002
00009998
33333332
00001cf7
33333332
00000000
33333332
33333332
00000000
00006665
00008992
33333332
33333332
00000003
33333332
33333332
00000002
0000aaa9
00000000
00009ce2
44444442
1111110d
00000001
aaaaaaa9
55555553
00000001
00000001
aaaaaaa9
0000608f
44444444
11111113
00000000
00000001
00000001
00005554
00002435
44444443
11111110
00000004
00000000
00000000
55555554
00003047
55555554
22222222
55555554
00000000
00000000
0000aaa9
00006c9c
55555554
22222221
00000004
55555554
55555554
00000000
00000002
00000000
00000002
00000002
00000002
00000002
00000002
00000002
00000002
00000002
00000002
00000002
00000002
00000002
00000002
00000002
00000000
00000002
00000002
00000002
00000002
00000002
00000002
00000002
00000002
0000ffff
00000000
00004afa
0000ffff
0000ffff
00000003
0000ffff
0000ffff
00000003
00000001
0000ffff
00004afc
0000ffff
0000ffff
0000ffff
0000ffff
00000001
00000000
00004afb
0000ffff
0000ffff
00000000
0000ffff
0000ffff
00000000
0000b504
00000000
0000b504
0000b504
0000b504
00000002
0000b504
0000b504
00000000
0000b504
0000b504
00000001
0000b504
0000b504
0000b504
0000b504
00000000
0000b504
00000000
0000b504
0000b504
00000000
0000b504
0000b504
00000002
00006666
00000000
00008256
66666666
33333332
00000000
66666666
11111110
00000002
00003334
66666666
000039f0
00000001
00000002
66666666
11111112
00000000
0000cccc
00005e22
00000000
00000000
00000003
66666666
11111111
00000000
00003333
00000000
0000412b
33333333
33333333
00000003
33333333
33333333
00000003
00009999
33333333
00000001
00001cf8
33333333
00000001
33333333
33333333
00000001
00006666
00008993
33333333
00000000
00000004
33333333
33333333
00000000
00000005
00000000
00000005
00000005
00000005
00000005
00000005
00000005
00000001
00000005
00000005
00000005
00000005
00000005
00000005
00000005
00000001
00000005
00000005
00000005
00000005
00000000
00000005
00000005
00000002
0000aaaa
00000000
00009ce3
44444443
1111110e
00000002
aaaaaaaa
55555554
00000002
00000002
aaaaaaaa
00006090
44444445
11111114
00000001
00000002
00000000
00005555
00002436
44444444
11111111
00000000
00000000
00000000
00000002
00005555
00000000
0000a8f4
55555555
22222221
00000001
55555555
55555555
00000001
00000001
55555555
00003048
55555555
22222223
55555555
00000001
00000001
0000aaaa
00006c9d
55555555
22222222
00000000
55555555
00000000
00000001
00000003
00000000
00000003
00000003
00000003
00000003
00000003
00000003
00000003
00000003
00000003
00000003
00000003
00000003
00000003
00000003
00000001
00000003
00000003
00000003
00000003
00000003
00000003
00000003
00000000
aaaaaaa9
00000010
55555554
00005554
00000000
0000a8f3
55555554
22222220
00000000
55555554
55555554
00008000
0000000c
55555555
dfffffff
001ffffc

3
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@ -1,3 +0,0 @@
00000000
40000000

584
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@ -1,584 +0,0 @@
ffffb7fe
7ffbfffe
bfbffffe
00000040
00000000
f6fffffe
fc000006
31333332
ff0007ff
ff7fffee
ffbffffa
fddffffe
ffedfffe
ffd7fffe
fffc007f
fdfdfffe
aaa9aaa9
3332b331
ffffe002
fffff008
fff7f7fe
fffffbff
fffff5fe
55555454
ffffff7c
ffdfffbe
ffffff5e
fffffff8
ffffbff6
07fffffb
ffdffffc
ffffbffd
8001ffff
26666664
dfff7ffe
f000001f
f7ffff7e
fc0fffff
ff7ffffb
ffefffff
fffeeffe
00077fff
ffffdfff
0003efff
fffffcff
ffffddfe
ffffeefe
ffffffae
ffffffe6
fdfffff6
fffffff8
80000006
60000000
e0000000
baaaaaaa
08000001
59555554
02000040
01000003
007ffffa
00400010
000fffff
00010000
ffff7fff
ffff8afd
55557555
00011000
00000800
00080400
000001fd
fffffe7f
00000042
ffe0000f
fffffff7
fffffffb
ffffffc1
40000000
80000006
40000005
0fff4afc
04000006
01fffff7
00fffff9
007ffffe
003ffdff
001ffff8
c00fffff
0003ff7f
c001ffff
01008000
c0004000
00042000
aaaabaaa
f80003ff
00000201
ffff00ff
fff80007
00016a0a
00000002
66671b6c
3333e839
0000b50b
aaab5fb0
55560a5b
0000b509
00016a08
0000b505
66671b6a
3333e837
55560a59
0000b507
00016a09
00000001
66671b6b
3333e838
0000b50a
aaab5faf
55560a5a
0000b508
00000002
fffe95fa
6665b164
33327e31
ffff4b03
aaa9f5a8
5554a053
ffff4b01
00000000
ffff4afd
6665b162
33327e2f
5554a051
ffff4aff
00000001
fffe95f9
6665b163
33327e30
ffff4b02
aaa9f5a7
5554a052
ffff4b00
66671b6c
6665b164
ccccccce
9999999b
6666666d
11111112
bbbbbbbd
6666666b
66671b6a
66666667
cccccccc
99999999
bbbbbbbb
66666669
66671b6b
6665b163
cccccccd
9999999a
6666666c
11111111
bbbbbbbc
6666666a
3333e839
33327e31
9999999b
66666668
3333333a
dddddddf
8888888a
33333338
3333e837
33333334
99999999
66666666
88888888
33333336
3333e838
33327e30
9999999a
66666667
33333339
ddddddde
88888889
33333337
0000b50b
ffff4b03
6666666d
3333333a
0000000c
aaaaaab1
5555555c
0000000a
0000b509
00000006
6666666b
33333338
5555555a
00000008
0000b50a
ffff4b02
6666666c
33333339
0000000b
aaaaaab0
5555555b
00000009
aaab5fb0
aaa9f5a8
11111112
dddddddf
aaaaaab1
55555556
00000001
aaaaaaaf
aaab5fae
aaaaaaab
11111110
dddddddd
ffffffff
aaaaaaad
aaab5faf
aaa9f5a7
11111111
ddddddde
aaaaaab0
55555555
00000000
aaaaaaae
55560a5b
5554a053
bbbbbbbd
8888888a
5555555c
00000001
aaaaaaac
5555555a
55560a59
55555556
bbbbbbbb
88888888
aaaaaaaa
55555558
55560a5a
5554a052
bbbbbbbc
88888889
5555555b
00000000
aaaaaaab
55555559
0000b509
ffff4b01
6666666b
33333338
0000000a
aaaaaaaf
5555555a
00000008
0000b507
00000004
66666669
33333336
55555558
00000006
0000b508
ffff4b00
6666666a
33333337
00000009
aaaaaaae
55555559
00000007
00016a08
00000000
66671b6a
3333e837
0000b509
aaab5fae
55560a59
0000b507
00016a06
0000b503
66671b68
3333e835
55560a57
0000b505
00016a07
ffffffff
66671b69
3333e836
0000b508
aaab5fad
55560a58
0000b506
0000b505
ffff4afd
66666667
33333334
00000006
aaaaaaab
55555556
00000004
0000b503
00000000
66666665
33333332
55555554
00000002
0000b504
ffff4afc
66666666
33333333
00000005
aaaaaaaa
55555555
00000003
66671b6a
6665b162
cccccccc
99999999
6666666b
11111110
bbbbbbbb
66666669
66671b68
33333333
99999998
66666665
88888887
33333335
3333e837
33327e2f
99999999
66666666
33333338
dddddddd
88888888
33333336
0000b50a
ffff4b02
6666666c
33333339
0000000b
aaaaaab0
5555555b
00000009
0000b508
00000005
6666666a
33333337
55555559
00000007
0000b509
ffff4b01
6666666b
33333338
0000000a
aaaaaaaf
5555555a
00000008
aaab5faf
aaa9f5a7
11111111
ddddddde
aaaaaab0
55555555
00000000
aaaaaaae
aaab5fad
aaaaaaaa
1111110f
dddddddc
fffffffe
aaaaaaac
aaab5fae
aaa9f5a6
11111110
dddddddd
aaaaaaaf
55555554
ffffffff
aaaaaaad
55560a5a
5554a052
bbbbbbbc
88888889
5555555b
00000000
aaaaaaab
55555559
55560a58
55555555
bbbbbbba
88888887
aaaaaaa9
55555557
55560a59
5554a051
bbbbbbbb
88888888
5555555a
ffffffff
aaaaaaaa
55555558
0000b508
ffff4b00
6666666a
33333337
00000009
aaaaaaae
55555559
00000007
0000b506
00000003
66666668
33333335
55555557
00000005
0000b507
ffff4aff
66666669
33333336
00000008
aaaaaaad
55555558
00000006
66666665
ccccccca
99999997
bbbbbbb9
66666667
66671b69
6665b161
cccccccb
99999998
6666666a
1111110f
bbbbbbba
66666668
3333e837
33327e2f
99999999
66666666
33333338
dddddddd
88888888
33333336
3333e835
33333332
99999997
66666664
88888886
33333334
3333e836
33327e2e
99999998
66666665
33333337
dddddddc
88888887
33333335
55560a59
5554a051
bbbbbbbb
88888888
5555555a
ffffffff
aaaaaaaa
55555558
55560a57
55555554
bbbbbbb9
88888886
aaaaaaa8
55555556
55560a58
5554a050
bbbbbbba
88888887
55555559
fffffffe
aaaaaaa9
55555557
0000b507
ffff4aff
66666669
33333336
00000008
aaaaaaad
55555558
00000006
0000b505
00000002
66666667
33333334
55555556
00000004
0000b506
ffff4afe
66666668
33333335
00000007
aaaaaaac
55555557
00000005
00016a09
00000001
66671b6b
3333e838
0000b50a
aaab5faf
55560a5a
0000b508
00016a07
0000b504
66671b69
3333e836
55560a58
0000b506
00016a08
00000000
66671b6a
3333e837
0000b509
aaab5fae
55560a59
0000b507
00000001
fffe95f9
6665b163
33327e30
ffff4b02
aaa9f5a7
5554a052
ffff4b00
ffffffff
ffff4afc
6665b161
33327e2e
5554a050
ffff4afe
00000000
fffe95f8
6665b162
33327e2f
ffff4b01
aaa9f5a6
5554a051
ffff4aff
66671b6b
6665b163
cccccccd
9999999a
6666666c
11111111
bbbbbbbc
6666666a
66671b69
66666666
cccccccb
99999998
bbbbbbba
66666668
66671b6a
6665b162
cccccccc
99999999
6666666b
11111110
bbbbbbbb
66666669
3333e838
33327e30
9999999a
66666667
33333339
ddddddde
88888889
33333337
3333e836
e000001f
f0000003
00000000

564
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-addi-01.reference_output
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@ -1,564 +0,0 @@
1ffff800
80000666
00000000
e0000555
efffffee
f7fffffb
fbffffff
00000000
ff000003
ff80003f
ffbffffa
ffe00554
ffefffee
fff7fff5
fffbfdfe
fffe0002
ffff0004
ffff8005
ffffbff7
ffffdff9
ffffefde
fffff9ff
fffffbf9
fffffdde
ffffff01
ffffffac
ffffffeb
ffffffe1
fffffff5
fffffff2
00000027
ffffffd1
fffffff4
0000bd02
ffffffff
ffffeefe
07ffff7f
ffffffc3
ffffffb6
00000003
fffffff9
80000556
3ffffc00
10000000
03fffff6
0200002e
01000667
007fffbf
003ffeff
00200555
00100000
00080005
000403ff
00020000
00010200
00007ff9
00004333
00002555
00000aaa
00000e65
000001bf
000004ff
000006e6
00000373
0000081f
00000210
00000008
ffffffff
00000101
000003bf
00000080
00000020
00008010
00000000
55555556
0000b533
0000b4d9
0000bb6c
0000b839
0000b50b
0000afb0
0000ba5b
0000b509
0000b531
0000b505
0000bb6a
0000b837
0000ba59
0000b507
0000b532
0000b4d8
0000bb6b
0000b838
0000b50a
0000afaf
0000ba5a
0000b508
ffff4b2b
ffff4ad1
ffff5164
ffff4e31
ffff4b03
ffff45a8
ffff5053
ffff4b01
ffff4b29
ffff4afd
ffff5162
ffff4e2f
ffff5051
ffff4aff
ffff4b2a
ffff4ad0
ffff5163
ffff4e30
ffff4b02
ffff45a7
ffff5052
ffff4b00
66666695
6666663b
66666cce
6666699b
6666666d
66666112
66666bbd
6666666b
66666693
66666667
66666ccc
66666999
66666bbb
66666669
66666694
6666663a
66666ccd
6666699a
6666666c
66666111
66666bbc
6666666a
33333362
33333308
3333399b
33333668
3333333a
33332ddf
3333388a
33333338
33333360
33333334
33333999
33333666
33333888
33333336
33333361
33333307
3333399a
33333667
33333339
33332dde
33333889
33333337
00000034
ffffffda
0000066d
0000033a
0000000c
fffffab1
0000055c
0000000a
00000032
00000006
0000066b
00000338
0000055a
00000008
00000033
ffffffd9
0000066c
00000339
0000000b
fffffab0
0000055b
00000009
aaaaaad9
aaaaaa7f
aaaab112
aaaaaddf
aaaaaab1
aaaaa556
aaaab001
aaaaaaaf
aaaaaad7
aaaaaaab
aaaab110
aaaaaddd
aaaaafff
aaaaaaad
aaaaaad8
aaaaaa7e
aaaab111
aaaaadde
aaaaaab0
aaaaa555
aaaab000
aaaaaaae
55555584
5555552a
55555bbd
5555588a
5555555c
55555001
55555aac
5555555a
55555582
55555556
55555bbb
55555888
55555aaa
55555558
55555583
55555529
55555bbc
55555889
5555555b
55555000
55555aab
55555559
00000032
ffffffd8
0000066b
00000338
0000000a
fffffaaf
0000055a
00000008
00000030
00000004
00000669
00000336
00000558
00000006
00000031
ffffffd7
0000066a
00000337
00000009
fffffaae
00000559
00000007
0000b531
0000b4d7
0000bb6a
0000b837
0000b509
0000afae
0000ba59
0000b507
0000b52f
0000b503
0000bb68
0000b835
0000ba57
0000b505
0000b530
0000b4d6
0000bb69
0000b836
0000b508
0000afad
0000ba58
0000b506
0000002e
ffffffd4
00000667
00000334
00000006
fffffaab
00000556
00000004
0000002c
00000000
00000665
00000332
00000554
00000002
0000002d
ffffffd3
00000666
00000333
00000005
fffffaaa
00000555
00000003
66666693
66666639
66666ccc
66666999
6666666b
66666110
66666bbb
66666669
66666691
66666665
aaaaa555
aaaab000
aaaaaaae
aaaaaad6
aaaaaaaa
aaaab10f
aaaaaddc
aaaaaffe
aaaaaaac
aaaaaad7
aaaaaa7d
aaaab110
aaaaaddd
aaaaaaaf
aaaaa554
aaaaafff
aaaaaaad
55555583
55555529
55555bbc
55555889
5555555b
55555000
55555aab
55555559
55555581
55555555
55555bba
55555887
55555aa9
55555557
55555582
55555528
55555bbb
55555888
5555555a
55554fff
55555aaa
55555558
00000031
ffffffd7
0000066a
00000337
00000009
fffffaae
00000559
00000007
0000002f
00000003
00000668
00000335
00000557
00000005
00000030
ffffffd6
00000669
00000336
00000008
fffffaad
00000558
00000006
66666cca
66666997
66666bb9
66666667
66666692
66666638
66666ccb
66666998
6666666a
6666610f
66666bba
66666668
33333360
33333306
33333999
33333666
33333338
33332ddd
33333888
33333336
3333335e
33333332
33333997
33333664
33333886
33333334
3333335f
33333305
33333998
33333665
33333337
33332ddc
33333887
33333335
55555582
55555528
55555bbb
55555888
5555555a
55554fff
55555aaa
55555558
55555580
55555554
55555bb9
55555886
55555aa8
55555556
55555581
55555527
55555bba
55555887
55555559
55554ffe
55555aa9
55555557
00000030
ffffffd6
00000669
00000336
00000008
fffffaad
00000558
00000006
0000002e
00000002
00000667
00000334
00000556
00000004
0000002f
ffffffd5
00000668
00000335
00000007
fffffaac
00000557
00000005
0000b532
0000b4d8
0000bb6b
0000b838
0000b50a
0000afaf
0000ba5a
0000b508
0000b530
0000b504
0000bb69
0000b836
0000ba58
0000b506
0000b531
0000b4d7
0000bb6a
0000b837
0000b509
0000afae
0000ba59
0000b507
ffff4b2a
ffff4ad0
ffff5163
ffff4e30
ffff4b02
ffff45a7
ffff5052
ffff4b00
ffff4b28
ffff4afc
ffff5161
ffff4e2e
ffff5050
ffff4afe
ffff4b29
ffff4acf
ffff5162
ffff4e2f
ffff4b01
ffff45a6
ffff5051
ffff4aff
66666694
6666663a
66666ccd
6666699a
6666666c
66666111
66666bbc
6666666a
66666692
66666666
66666ccb
66666998
66666bba
66666668
66666693
66666639
66666ccc
66666999
6666666b
66666110
66666bbb
66666669
33333361
33333307
3333399a
33333667
33333339
33332dde
33333889
33333337
3333335f
33333333
33333998
33333665
33333887
33333335
33333360
33333306
33333999
33333666
33333338
33332ddd
33333888
33333336
00000033
ffffffd9
0000066c
00000339
0000000b
fffffab0
0000055b
00000009
00000031
00000005
0000066a
00000337
00000559
00000007
00000032
ffffffd8
0000066b
00000338
0000000a
fffffaaf
0000055a
00000008
aaaaaad8
aaaaaa7e
aaaab111
aaaaadde
aaaaaab0
c000003f
fdffffff
00000000
00000000
00000000

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