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Cleaned up SelBusWord

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This commit is contained in:
David Harris 2022-08-25 11:18:13 -07:00
parent 7a129af9ad
commit d7be94fab2
5 changed files with 11 additions and 11 deletions
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4
pipelined/src/cache/cache.sv vendored
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@ -56,7 +56,7 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, LOGBWPL, WORDLEN, MUXINTE
output logic CacheFetchLine,
output logic CacheWriteLine,
input logic CacheBusAck,
input logic SelLSUBusWord,
input logic SelBusWord,
input logic [LOGBWPL-1:0] WordCount,
input logic [LINELEN-1:0] FetchBuffer,
output logic [`PA_BITS-1:0] CacheBusAdr,
@ -146,7 +146,7 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, LOGBWPL, WORDLEN, MUXINTE
// like to fix this.
if(DCACHE)
mux2 #(LOGBWPL) WordAdrrMux(.d0(PAdr[$clog2(LINELEN/8) - 1 : $clog2(MUXINTERVAL/8)]),
.d1(WordCount), .s(SelLSUBusWord),
.d1(WordCount), .s(SelBusWord),
.y(WordOffsetAddr));
else assign WordOffsetAddr = PAdr[$clog2(LINELEN/8) - 1 : $clog2(MUXINTERVAL/8)];

4
pipelined/src/ifu/ifu.sv
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@ -201,7 +201,7 @@ module ifu (
busdp #(WORDSPERLINE, LINELEN, LOGBWPL, `ICACHE)
busdp(.clk, .reset,
.HRDATA(HRDATA), .BusAck(IFUBusAck), .BusInit(IFUBusInit), .BusWrite(), .SelLSUBusWord(),
.HRDATA(HRDATA), .BusAck(IFUBusAck), .BusInit(IFUBusInit), .BusWrite(), .SelBusWord(),
.BusRead(IFUBusRead), .HSIZE(), .HBURST(IFUHBURST), .HTRANS(IFUHTRANS), .BusTransComplete(IFUTransComplete),
.Funct3(3'b010), .HADDR(IFUHADDR), .CacheBusAdr(ICacheBusAdr),
.WordCount(),
@ -228,7 +228,7 @@ module ifu (
.CacheWriteLine(), .ReadDataWord(FinalInstrRawF),
.Cacheable(CacheableF),
.CacheMiss(ICacheMiss), .CacheAccess(ICacheAccess),
.ByteMask('0), .WordCount('0), .SelLSUBusWord('0),
.ByteMask('0), .WordCount('0), .SelBusWord('0),
.FinalWriteData('0),
.RW(2'b10),
.Atomic('0), .FlushCache('0),

4
pipelined/src/lsu/busdp.sv
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@ -66,7 +66,7 @@ module busdp #(parameter WORDSPERLINE, LINELEN, LOGWPL, CACHE_ENABLED)
input logic CPUBusy,
input logic Cacheable,
input logic [2:0] Funct3,
output logic SelLSUBusWord,
output logic SelBusWord,
output logic BusStall,
output logic BusCommitted);
@ -90,6 +90,6 @@ module busdp #(parameter WORDSPERLINE, LINELEN, LOGWPL, CACHE_ENABLED)
busfsm #(WordCountThreshold, LOGWPL, CACHE_ENABLED) busfsm(
.clk, .reset, .IgnoreRequest, .RW, .CacheFetchLine, .CacheWriteLine,
.BusAck, .BusInit, .CPUBusy, .Cacheable, .BusStall, .BusWrite, .SelLSUBusWord, .BusRead, .BufferCaptureEn,
.BusAck, .BusInit, .CPUBusy, .Cacheable, .BusStall, .BusWrite, .SelBusWord, .BusRead, .BufferCaptureEn,
.HBURST, .HTRANS, .BusTransComplete, .CacheBusAck, .BusCommitted, .SelUncachedAdr, .WordCount, .WordCountDelayed);
endmodule

4
pipelined/src/lsu/busfsm.sv
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@ -47,7 +47,7 @@ module busfsm #(parameter integer WordCountThreshold,
output logic BusStall,
output logic BusWrite,
output logic SelLSUBusWord,
output logic SelBusWord,
output logic BusRead,
output logic [2:0] HBURST,
output logic BusTransComplete,
@ -168,7 +168,7 @@ module busfsm #(parameter integer WordCountThreshold,
assign UnCachedBusWrite = (BusCurrState == STATE_BUS_READY & UnCachedAccess & RW[0] & ~IgnoreRequest) |
(BusCurrState == STATE_BUS_UNCACHED_WRITE);
assign BusWrite = UnCachedBusWrite | (BusCurrState == STATE_BUS_WRITE & ~WordCountFlag);
assign SelLSUBusWord = (BusCurrState == STATE_BUS_READY & UnCachedAccess & RW[0]) |
assign SelBusWord = (BusCurrState == STATE_BUS_READY & UnCachedAccess & RW[0]) |
(BusCurrState == STATE_BUS_UNCACHED_WRITE) |
(BusCurrState == STATE_BUS_WRITE);

6
pipelined/src/lsu/lsu.sv
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@ -108,7 +108,7 @@ module lsu (
logic InterlockStall;
logic IgnoreRequestTLB;
logic BusCommittedM, DCacheCommittedM;
logic SelLSUBusWord;
logic SelBusWord;
logic DataDAPageFaultM;
logic [`XLEN-1:0] IMWriteDataM, IMAWriteDataM;
logic [`LLEN-1:0] IMAFWriteDataM;
@ -226,7 +226,7 @@ module lsu (
.clk, .reset,
.HRDATA, .BusAck(LSUBusAck), .BusInit(LSUBusInit), .BusWrite(LSUBusWrite),
.BusRead(LSUBusRead), .HSIZE(LSUHSIZE), .HBURST(LSUHBURST), .HTRANS(LSUHTRANS), .BusTransComplete(LSUTransComplete),
.WordCount, .SelLSUBusWord,
.WordCount, .SelBusWord,
.Funct3(LSUFunct3M), .HADDR(LSUHADDR), .CacheBusAdr(DCacheBusAdr), .CacheFetchLine(DCacheFetchLine),
.CacheWriteLine(DCacheWriteLine), .CacheBusAck(DCacheBusAck), .FetchBuffer, .PAdr(LSUPAdrM),
.SelUncachedAdr, .IgnoreRequest, .RW(LSURWM), .CPUBusy, .Cacheable(CacheableM),
@ -239,7 +239,7 @@ module lsu (
if(`DCACHE) begin : dcache
cache #(.LINELEN(`DCACHE_LINELENINBITS), .NUMLINES(`DCACHE_WAYSIZEINBYTES*8/LINELEN),
.NUMWAYS(`DCACHE_NUMWAYS), .LOGBWPL(LOGBWPL), .WORDLEN(`LLEN), .MUXINTERVAL(`XLEN), .DCACHE(1)) dcache(
.clk, .reset, .CPUBusy, .SelLSUBusWord, .RW(LSURWM), .Atomic(LSUAtomicM),
.clk, .reset, .CPUBusy, .SelBusWord, .RW(LSURWM), .Atomic(LSUAtomicM),
.FlushCache(FlushDCacheM), .NextAdr(LSUAdrE), .PAdr(LSUPAdrM),
.ByteMask(ByteMaskM), .WordCount,
.FinalWriteData(LSUWriteDataM), .Cacheable(CacheableM),