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Replaced DTIM and IROM with DTIM_SUPPORTED, IROM_SUPPORTED, and base and range for each

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This commit is contained in:
David Harris 2022-08-26 20:26:12 -07:00
parent 906f6f2990
commit 6409548c8b
15 changed files with 86 additions and 37 deletions
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8
pipelined/config/buildroot/wally-config.vh
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@ -49,8 +49,6 @@
`define UARCH_SINGLECYCLE 0
// LSU microarchitectural Features
`define DTIM 0
`define IROM 0
`define BUS 1
`define DCACHE 1
`define ICACHE 1
@ -87,6 +85,12 @@
// Peripheral Addresses
// Peripheral memory space extends from BASE to BASE+RANGE
// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
`define DTIM_SUPPORTED 0
`define DTIM_BASE 34'h80000000
`define DTIM_RANGE 34'h00001FFF
`define IROM_SUPPORTED 0
`define IROM_BASE 34'h80000000
`define IROM_RANGE 34'h00001FFF
`define BOOTROM_SUPPORTED 1'b1
`define BOOTROM_BASE 56'h00001000
`define BOOTROM_RANGE 56'h00000FFF

9
pipelined/config/fpga/wally-config.vh
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@ -51,8 +51,6 @@
`define UARCH_SINGLECYCLE 0
// LSU microarchitectural Features
`define DTIM 0
`define IROM 0
`define BUS 1
`define DCACHE 1
`define ICACHE 1
@ -89,6 +87,13 @@
// Peripheral Addresses
// Peripheral memory space extends from BASE to BASE+RANGE
// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
`define DTIM_SUPPORTED 0
`define DTIM_BASE 34'h80000000
`define DTIM_RANGE 34'h00001FFF
`define IROM_SUPPORTED 0
`define IROM_BASE 34'h80000000
`define IROM_RANGE 34'h00001FFF
`define BOOTROM_SUPPORTED 1'b1
`define BOOTROM_BASE 56'h00001000
`define BOOTROM_RANGE 56'h00000FFF

8
pipelined/config/rv32e/wally-config.vh
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@ -50,8 +50,6 @@
`define UARCH_SUPERSCALR 0
`define UARCH_SINGLECYCLE 0
// LSU microarchitectural Features
`define DTIM 0
`define IROM 0
`define BUS 1
`define DCACHE 0
`define ICACHE 0
@ -88,6 +86,12 @@
// Peripheral Addresses
// Peripheral memory space extends from BASE to BASE+RANGE
// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
`define DTIM_SUPPORTED 0
`define DTIM_BASE 34'h80000000
`define DTIM_RANGE 34'h00001FFF
`define IROM_SUPPORTED 0
`define IROM_BASE 34'h80000000
`define IROM_RANGE 34'h00001FFF
`define BOOTROM_SUPPORTED 1'b1
`define BOOTROM_BASE 34'h00001000
`define BOOTROM_RANGE 34'h00000FFF

8
pipelined/config/rv32gc/wally-config.vh
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@ -49,8 +49,6 @@
`define UARCH_SUPERSCALR 0
`define UARCH_SINGLECYCLE 0
// LSU microarchitectural Features
`define DTIM 0
`define IROM 0
`define BUS 1
`define DCACHE 1
`define ICACHE 1
@ -87,6 +85,12 @@
// Peripheral Addresses
// Peripheral memory space extends from BASE to BASE+RANGE
// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
`define DTIM_SUPPORTED 0
`define DTIM_BASE 34'h80000000
`define DTIM_RANGE 34'h00001FFF
`define IROM_SUPPORTED 0
`define IROM_BASE 34'h80000000
`define IROM_RANGE 34'h00001FFF
`define BOOTROM_SUPPORTED 1'b1
`define BOOTROM_BASE 34'h00001000
`define BOOTROM_RANGE 34'h00000FFF

8
pipelined/config/rv32i/wally-config.vh
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@ -50,8 +50,6 @@
`define UARCH_SUPERSCALR 0
`define UARCH_SINGLECYCLE 0
// LSU microarchitectural Features
`define DTIM 0
`define IROM 0
`define BUS 1
`define DCACHE 1
`define ICACHE 1
@ -88,6 +86,12 @@
// Peripheral Addresses
// Peripheral memory space extends from BASE to BASE+RANGE
// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
`define DTIM_SUPPORTED 0
`define DTIM_BASE 34'h80000000
`define DTIM_RANGE 34'h00001FFF
`define IROM_SUPPORTED 0
`define IROM_BASE 34'h80000000
`define IROM_RANGE 34'h00001FFF
`define BOOTROM_SUPPORTED 1'b1
`define BOOTROM_BASE 34'h00001000
`define BOOTROM_RANGE 34'h00000FFF

12
pipelined/config/rv32ic/wally-config.vh
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@ -49,8 +49,6 @@
`define UARCH_SUPERSCALR 0
`define UARCH_SINGLECYCLE 0
// LSU microarchitectural Features
`define DTIM 1
`define IROM 1
`define BUS 0
`define DCACHE 0
`define ICACHE 0
@ -87,10 +85,16 @@
// Peripheral Addresses
// Peripheral memory space extends from BASE to BASE+RANGE
// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
`define BOOTROM_SUPPORTED 1'b1
`define DTIM_SUPPORTED 1
`define DTIM_BASE 34'h80000000
`define DTIM_RANGE 34'h00001FFF
`define IROM_SUPPORTED 1
`define IROM_BASE 34'h80000000
`define IROM_RANGE 34'h00001FFF
`define BOOTROM_SUPPORTED 1'b0
`define BOOTROM_BASE 34'h00001000
`define BOOTROM_RANGE 34'h00000FFF
`define UNCORE_RAM_SUPPORTED 1'b1
`define UNCORE_RAM_SUPPORTED 1'b0
`define UNCORE_RAM_BASE 34'h80000000
`define UNCORE_RAM_RANGE 34'h07FFFFFF
`define EXT_MEM_SUPPORTED 1'b0

8
pipelined/config/rv64BP/wally-config.vh
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@ -51,8 +51,6 @@
`define UARCH_SUPERSCALR 0
`define UARCH_SINGLECYCLE 0
// LSU microarchitectural Features
`define DTIM 0
`define IROM 0
`define BUS 1
`define DCACHE 1
`define ICACHE 1
@ -92,6 +90,12 @@
// Peripheral memory space extends from BASE to BASE+RANGE
// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
`define DTIM_SUPPORTED 0
`define DTIM_BASE 34'h80000000
`define DTIM_RANGE 34'h00001FFF
`define IROM_SUPPORTED 0
`define IROM_BASE 34'h80000000
`define IROM_RANGE 34'h00001FFF
`define BOOTROM_SUPPORTED 1'b1
`define BOOTROM_BASE 56'h00001000
`define BOOTROM_RANGE 56'h00000FFF

8
pipelined/config/rv64fp/wally-config.vh
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@ -52,8 +52,6 @@
`define UARCH_SINGLECYCLE 0
// LSU microarchitectural Features
`define DTIM 0
`define IROM 0
`define BUS 1
`define DCACHE 1
`define ICACHE 1
@ -95,6 +93,12 @@
// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
// *** each of these is `PA_BITS wide. is this paramaterizable INSIDE the config file?
`define DTIM_SUPPORTED 0
`define DTIM_BASE 34'h80000000
`define DTIM_RANGE 34'h00001FFF
`define IROM_SUPPORTED 0
`define IROM_BASE 34'h80000000
`define IROM_RANGE 34'h00001FFF
`define BOOTROM_SUPPORTED 1'b1
`define BOOTROM_BASE 56'h00001000 // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder
`define BOOTROM_RANGE 56'h00000FFF

8
pipelined/config/rv64fpquad/wally-config.vh
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@ -51,8 +51,6 @@
`define UARCH_SINGLECYCLE 0
// LSU microarchitectural Features
`define DTIM 0
`define IROM 0
`define BUS 1
`define DCACHE 1
`define ICACHE 1
@ -94,6 +92,12 @@
// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
// *** each of these is `PA_BITS wide. is this paramaterizable INSIDE the config file?
`define DTIM_SUPPORTED 0
`define DTIM_BASE 34'h80000000
`define DTIM_RANGE 34'h00001FFF
`define IROM_SUPPORTED 0
`define IROM_BASE 34'h80000000
`define IROM_RANGE 34'h00001FFF
`define BOOTROM_SUPPORTED 1'b1
`define BOOTROM_BASE 56'h00001000 // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder
`define BOOTROM_RANGE 56'h00000FFF

8
pipelined/config/rv64gc/wally-config.vh
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@ -51,8 +51,6 @@
`define UARCH_SINGLECYCLE 0
// LSU microarchitectural Features
`define DTIM 0
`define IROM 0
`define BUS 1
`define DCACHE 1
`define ICACHE 1
@ -94,6 +92,12 @@
// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
// *** each of these is `PA_BITS wide. is this paramaterizable INSIDE the config file?
`define DTIM_SUPPORTED 0
`define DTIM_BASE 34'h80000000
`define DTIM_RANGE 34'h00001FFF
`define IROM_SUPPORTED 0
`define IROM_BASE 34'h80000000
`define IROM_RANGE 34'h00001FFF
`define BOOTROM_SUPPORTED 1'b1
`define BOOTROM_BASE 56'h00001000 // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder
`define BOOTROM_RANGE 56'h00000FFF

8
pipelined/config/rv64i/wally-config.vh
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@ -51,8 +51,6 @@
`define UARCH_SINGLECYCLE 0
// LSU microarchitectural Features
`define DTIM 0
`define IROM 0
`define BUS 1
`define DCACHE 1
`define ICACHE 1
@ -94,6 +92,12 @@
// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
// *** each of these is `PA_BITS wide. is this paramaterizable INSIDE the config file?
`define DTIM_SUPPORTED 0
`define DTIM_BASE 34'h80000000
`define DTIM_RANGE 34'h00001FFF
`define IROM_SUPPORTED 0
`define IROM_BASE 34'h80000000
`define IROM_RANGE 34'h00001FFF
`define BOOTROM_SUPPORTED 1'b1
`define BOOTROM_BASE 56'h00001000 // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder
`define BOOTROM_RANGE 56'h00000FFF

12
pipelined/config/rv64ic/wally-config.vh
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@ -51,8 +51,6 @@
`define UARCH_SINGLECYCLE 0
// LSU microarchitectural Features
`define DTIM 1
`define IROM 1
`define BUS 0
`define DCACHE 0
`define ICACHE 0
@ -94,10 +92,16 @@
// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
// *** each of these is `PA_BITS wide. is this paramaterizable INSIDE the config file?
`define BOOTROM_SUPPORTED 1'b1
`define DTIM_SUPPORTED 1
`define DTIM_BASE 34'h80000000
`define DTIM_RANGE 34'h00001FFF
`define IROM_SUPPORTED 1
`define IROM_BASE 34'h80000000
`define IROM_RANGE 34'h00001FFF
`define BOOTROM_SUPPORTED 1'b0
`define BOOTROM_BASE 56'h00001000 // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder
`define BOOTROM_RANGE 56'h00000FFF
`define UNCORE_RAM_SUPPORTED 1'b1
`define UNCORE_RAM_SUPPORTED 1'b0
`define UNCORE_RAM_BASE 56'h80000000
`define UNCORE_RAM_RANGE 56'h7FFFFFFF
`define EXT_MEM_SUPPORTED 1'b0

2
pipelined/src/ifu/ifu.sv
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@ -184,7 +184,7 @@ module ifu (
logic [`XLEN-1:0] AllInstrRawF;
assign InstrRawF = AllInstrRawF[31:0];
if (`IROM) begin : irom
if (`IROM_SUPPORTED) begin : irom
irom irom(.clk, .reset, .Adr(CPUBusy | reset ? PCFSpill : PCNextFSpill), .ReadData(FinalInstrRawF));
end

2
pipelined/src/lsu/lsu.sv
View File

@ -198,7 +198,7 @@ module lsu (
// use the same UNCORE_RAM_BASE addresss for both the DTIM and any RAM in the Uncore.
// *** becomes DTIM_RAM_BASE
if (`DTIM) begin : dtim
if (`DTIM_SUPPORTED) begin : dtim
// The DTIM uses untranslated addresses, so it is not compatible with virtual memory.
dtim dtim(.clk, .reset, .LSURWM,
.IEUAdrE(CPUBusy | LSURWM[0] | reset ? IEUAdrM : IEUAdrE),

14
pipelined/testbench/testbench.sv
View File

@ -232,9 +232,9 @@ logic [3:0] dummy;
// force sdc timers
force dut.uncore.uncore.sdc.SDC.LimitTimers = 1;
end else begin
if (`IROM) $readmemh(memfilename, dut.core.ifu.irom.irom.rom.ROM);
if (`IROM_SUPPORTED) $readmemh(memfilename, dut.core.ifu.irom.irom.rom.ROM);
else if (`BUS) $readmemh(memfilename, dut.uncore.uncore.ram.ram.memory.RAM);
if (`DTIM) $readmemh(memfilename, dut.core.lsu.dtim.dtim.ram.RAM);
if (`DTIM_SUPPORTED) $readmemh(memfilename, dut.core.lsu.dtim.dtim.ram.RAM);
end
if (riscofTest) begin
@ -328,12 +328,12 @@ logic [3:0] dummy;
/* verilator lint_off INFINITELOOP */
while (signature[i] !== 'bx) begin
logic [`XLEN-1:0] sig;
if (`DTIM) sig = dut.core.lsu.dtim.dtim.ram.RAM[testadrNoBase+i];
if (`DTIM_SUPPORTED) sig = dut.core.lsu.dtim.dtim.ram.RAM[testadrNoBase+i];
else if (`UNCORE_RAM_SUPPORTED) sig = dut.uncore.uncore.ram.ram.memory.RAM[testadrNoBase+i];
//$display("signature[%h] = %h sig = %h", i, signature[i], sig);
if (signature[i] !== sig & (signature[i] !== DCacheFlushFSM.ShadowRAM[testadr+i])) begin
errors = errors+1;
$display(" Error on test %s result %d: adr = %h sim (D$) %h sim (DTIM) = %h, signature = %h",
$display(" Error on test %s result %d: adr = %h sim (D$) %h sim (DTIM_SUPPORTED) = %h, signature = %h",
tests[test], i, (testadr+i)*(`XLEN/8), DCacheFlushFSM.ShadowRAM[testadr+i], sig, signature[i]);
$stop;//***debug
end
@ -361,9 +361,9 @@ logic [3:0] dummy;
if (riscofTest) memfilename = {pathname, tests[test], "/ref/ref.elf.memfile"};
else memfilename = {pathname, tests[test], ".elf.memfile"};
//$readmemh(memfilename, dut.uncore.uncore.ram.ram.memory.RAM);
if (`IROM) $readmemh(memfilename, dut.core.ifu.irom.irom.rom.ROM);
if (`IROM_SUPPORTED) $readmemh(memfilename, dut.core.ifu.irom.irom.rom.ROM);
else if (`UNCORE_RAM_SUPPORTED) $readmemh(memfilename, dut.uncore.uncore.ram.ram.memory.RAM);
if (`DTIM) $readmemh(memfilename, dut.core.lsu.dtim.dtim.ram.RAM);
if (`DTIM_SUPPORTED) $readmemh(memfilename, dut.core.lsu.dtim.dtim.ram.RAM);
if (riscofTest) begin
ProgramAddrMapFile = {pathname, tests[test], "/ref/ref.elf.objdump.addr"};
@ -456,7 +456,7 @@ module riscvassertions;
assert (`ZICSR_SUPPORTED == 1 | (`PMP_ENTRIES == 0 & `VIRTMEM_SUPPORTED == 0)) else $error("PMP_ENTRIES and VIRTMEM_SUPPORTED must be zero if ZICSR not supported.");
assert (`ZICSR_SUPPORTED == 1 | (`S_SUPPORTED == 0 & `U_SUPPORTED == 0)) else $error("S and U modes not supported if ZISR not supported");
assert (`U_SUPPORTED | (`S_SUPPORTED == 0)) else $error ("S mode only supported if U also is supported");
assert (`VIRTMEM_SUPPORTED == 0 | (`DTIM == 0 & `IROM == 0)) else $error("Can't simultaneously have virtual memory and DTIM/IROM because local memories don't translate addresses");
assert (`VIRTMEM_SUPPORTED == 0 | (`DTIM_SUPPORTED == 0 & `IROM_SUPPORTED == 0)) else $error("Can't simultaneously have virtual memory and DTIM_SUPPORTED/IROM_SUPPORTED because local memories don't translate addresses");
assert (`DCACHE | `VIRTMEM_SUPPORTED ==0) else $error("Virtual memory needs dcache");
assert (`ICACHE | `VIRTMEM_SUPPORTED ==0) else $error("Virtual memory needs icache");
assert ((`DCACHE == 0 & `ICACHE == 0) | `BUS) else $error("Dcache and Icache requires DBUS.");