Fixed typo in bpred preventing compiling

2023-01-27 05:55:53 -08:00 · 2023-01-27 05:55:53 -08:00 · 767cfdc8a5
commit 767cfdc8a5
parent c2139eba93
1 changed files with 1 additions and 1 deletions
--- a/pipelined/src/ifu/bpred/bpred.sv
+++ b/pipelined/src/ifu/bpred/bpred.sv
@ -49,7 +49,7 @@ module bpred (
  // Branch and jump outcome
  input  logic             PCSrcE,                    // Executation stage branch is taken
  input  logic [`XLEN-1:0] IEUAdrE,                   // The branch/jump target address
-  input  logic [`XLEN-1:0]  dPCLinkE,                   // The address following the branch instruction. (AKA Fall through address)
+  input  logic [`XLEN-1:0] PCLinkE,                   // The address following the branch instruction. (AKA Fall through address)
  output logic [3:0]       InstrClassM,               // The valid instruction class. 1-hot encoded as jalr, ret, jr (not ret), j, br

  // Report branch prediction status