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one bitt removed from inital lignment shift

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This commit is contained in:
Katherine Parry 2022-12-28 17:46:53 -06:00
parent 7c19665dea
commit 1b4fa38510
10 changed files with 46 additions and 45 deletions
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4
pipelined/config/shared/wally-shared.vh
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@ -104,9 +104,9 @@
`define CVTLEN ((`NF<`XLEN) ? (`XLEN) : (`NF))
`define LLEN ((`FLEN<`XLEN) ? (`XLEN) : (`FLEN))
`define LOGCVTLEN $unsigned($clog2(`CVTLEN+1))
`define NORMSHIFTSZ ((`QLEN+`NF+1) > (3*`NF+8) ? (`QLEN+`NF+1) : (3*`NF+8))
`define NORMSHIFTSZ ((`QLEN+`NF+1) > (3*`NF+7) ? (`QLEN+`NF+1) : (3*`NF+7))//change
`define LOGNORMSHIFTSZ ($clog2(`NORMSHIFTSZ))
`define CORRSHIFTSZ ((`DIVRESLEN+`NF) > (3*`NF+8) ? (`DIVRESLEN+`NF) : (3*`NF+6))
`define CORRSHIFTSZ ((`DIVRESLEN+`NF) > (3*`NF+7) ? (`DIVRESLEN+`NF) : (3*`NF+5))//change
// division constants
`define RADIX 32'h2

11
pipelined/src/fpu/fma/fma.sv
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@ -37,18 +37,18 @@ module fma(
input logic XZero, YZero, ZZero, // is the input zero
input logic [2:0] OpCtrl, // 000 = fmadd (X*Y)+Z, 001 = fmsub (X*Y)-Z, 010 = fnmsub -(X*Y)+Z, 011 = fnmadd -(X*Y)-Z, 100 = fmul (X*Y)
output logic ZmSticky, // sticky bit that is calculated during alignment
output logic [3*`NF+5:0] Sm, // the positive sum's significand
output logic [3*`NF+4:0] Sm,//change // the positive sum's significand
output logic InvA, // Was A inverted for effective subtraction (P-A or -P+A)
output logic As, // the aligned addend's sign (modified Z sign for other opperations)
output logic Ps, // the product's sign
output logic Ss, // the sum's sign
output logic [`NE+1:0] Se,
output logic [$clog2(3*`NF+7)-1:0] SCnt // normalization shift count
output logic [$clog2(3*`NF+6)-1:0] SCnt//change // normalization shift count
);
logic [2*`NF+1:0] Pm; // the product's significand in U(2.2Nf) format
logic [3*`NF+5:0] Am; // addend aligned's mantissa for addition in U(NF+5.2NF+1)
logic [3*`NF+5:0] AmInv; // aligned addend's mantissa possibly inverted
logic [3*`NF+4:0] Am;//change // addend aligned's mantissa for addition in U(NF+5.2NF+1)
logic [3*`NF+4:0] AmInv; //change // aligned addend's mantissa possibly inverted
logic [2*`NF+1:0] PmKilled; // the product's mantissa possibly killed
logic KillProd; // set the product to zero before addition if the product is too small to matter
logic [`NE+1:0] Pe; // the product's exponent B(NE+2.0) format; adds 2 bits to allow for size of number and negative sign
@ -85,7 +85,8 @@ module fma(
fmaadd add(.Am, .Pm, .Ze, .Pe, .Ps, .KillProd, .ZmSticky, .AmInv, .PmKilled, .InvA, .Sm, .Se, .Ss);
fmalza #(3*`NF+6) lza(.A(AmInv), .Pm({PmKilled, 1'b0, InvA&Ps&ZmSticky&KillProd}), .Cin(InvA & ~(ZmSticky & ~KillProd)), .sub(InvA), .SCnt);
//change
fmalza #(3*`NF+5) lza(.A(AmInv), .Pm({PmKilled, 1'b0, InvA&Ps&ZmSticky&KillProd}), .Cin(InvA & ~(ZmSticky & ~KillProd)), .sub(InvA), .SCnt);
endmodule

12
pipelined/src/fpu/fma/fmaadd.sv
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@ -31,7 +31,7 @@
`include "wally-config.vh"
module fmaadd(
input logic [3*`NF+5:0] Am, // aligned addend's mantissa for addition in U(NF+5.2NF+1)
input logic [3*`NF+4:0] Am, //change // aligned addend's mantissa for addition in U(NF+5.2NF+1)
input logic [2*`NF+1:0] Pm, // the product's mantissa
input logic Ps, // the product sign and the alligend addeded's sign (Modified Z sign for other opperations)
input logic InvA, // invert the aligned addend
@ -39,13 +39,13 @@ module fmaadd(
input logic ZmSticky,
input logic [`NE-1:0] Ze,
input logic [`NE+1:0] Pe,
output logic [3*`NF+5:0] AmInv, // aligned addend possibly inverted
output logic [3*`NF+4:0] AmInv,//change // aligned addend possibly inverted
output logic [2*`NF+1:0] PmKilled, // the product's mantissa possibly killed
output logic Ss,
output logic [`NE+1:0] Se,
output logic [3*`NF+5:0] Sm // the positive sum
output logic [3*`NF+4:0] Sm//change // the positive sum
);
logic [3*`NF+5:0] PreSum, NegPreSum; // possibly negitive sum
logic [3*`NF+4:0] PreSum, NegPreSum;//change // possibly negitive sum
logic [3*`NF+5:0] PreSumdebug, NegPreSumdebug; // possibly negitive sum
logic NegSum; // was the sum negitive
logic NegSumdebug; // was the sum negitive
@ -65,8 +65,8 @@ module fmaadd(
// ie ~(InvA&ZmSticky&~KillProd)&InvA = (~ZmSticky|KillProd)&InvA
// addend - prod where product is killed (and not exactly zero) then don't add +1 from negation
// ie ~(InvA&ZmSticky&KillProd)&InvA = (~ZmSticky|~KillProd)&InvA
assign {NegSum, PreSum} = {{`NF+3{1'b0}}, PmKilled, 2'b0} + {InvA, AmInv} + {{3*`NF+6{1'b0}}, (~ZmSticky|KillProd)&InvA};
assign NegPreSum = Am + {{`NF+2{1'b1}}, ~PmKilled, 2'b0} + {(3*`NF+3)'(0), (~ZmSticky|~KillProd)&InvA, 2'b0};
assign {NegSum, PreSum} = {{`NF+2{1'b0}}, PmKilled, 2'b0} + {InvA, AmInv} + {{3*`NF+5{1'b0}}, (~ZmSticky|KillProd)&InvA};//change
assign NegPreSum = Am + {{`NF+1{1'b1}}, ~PmKilled, 2'b0} + {(3*`NF+2)'(0), (~ZmSticky|~KillProd)&InvA, 2'b0};//change
// Choose the positive sum and accompanying LZA result.
assign Sm = NegSum ? NegPreSum : PreSum;

20
pipelined/src/fpu/fma/fmaalign.sv
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@ -35,14 +35,14 @@ module fmaalign(
input logic [`NE-1:0] Xe, Ye, Ze, // biased exponents in B(NE.0) format
input logic [`NF:0] Zm, // significand in U(0.NF) format]
input logic XZero, YZero, ZZero, // is the input zero
output logic [3*`NF+5:0] Am, // addend aligned for addition in U(NF+5.2NF+1)
output logic [3*`NF+4:0] Am,//change // addend aligned for addition in U(NF+5.2NF+1)
output logic ZmSticky, // Sticky bit calculated from the aliged addend
output logic KillProd // should the product be set to zero
);
logic [`NE+1:0] ACnt; // how far to shift the addend to align with the product in Q(NE+2.0) format
logic [4*`NF+5:0] ZmShifted; // output of the alignment shifter including sticky bits U(NF+5.3NF+1)
logic [4*`NF+5:0] ZmPreshifted; // input to the alignment shifter U(NF+5.3NF+1)
logic [4*`NF+4:0] ZmShifted;//change // output of the alignment shifter including sticky bits U(NF+5.3NF+1)
logic [4*`NF+4:0] ZmPreshifted;//change // input to the alignment shifter U(NF+5.3NF+1)
logic KillZ;
///////////////////////////////////////////////////////////////////////////////
@ -53,16 +53,16 @@ module fmaalign(
// - negitive means Z is larger, so shift Z left
// - positive means the product is larger, so shift Z right
// This could have been done using Pe, but ACnt is on the critical path so we replicate logic for speed
assign ACnt = {2'b0, Xe} + {2'b0, Ye} - {2'b0, (`NE)'(`BIAS)} + (`NE+2)'(`NF+3) - {2'b0, Ze};
assign ACnt = {2'b0, Xe} + {2'b0, Ye} - {2'b0, (`NE)'(`BIAS)} + (`NE+2)'(`NF+2) - {2'b0, Ze};
// Defualt Addition with only inital left shift
// | 54'b0 | 106'b(product) | 2'b0 |
// | 53'b0 | 106'b(product) | 2'b0 |
// | addnend |
assign ZmPreshifted = {Zm,(3*`NF+5)'(0)};
assign ZmPreshifted = {Zm,(3*`NF+4)'(0)}; //change
assign KillProd = (ACnt[`NE+1]&~ZZero)|XZero|YZero;
assign KillZ = $signed(ACnt)>$signed((`NE+2)'(3)*(`NE+2)'(`NF)+(`NE+2)'(5));
assign KillZ = $signed(ACnt)>$signed((`NE+2)'(3)*(`NE+2)'(`NF)+(`NE+2)'(4));//change
always_comb
begin
@ -72,7 +72,7 @@ module fmaalign(
// | 54'b0 | 106'b(product) | 2'b0 |
// | addnend |
if (KillProd) begin
ZmShifted = {(`NF+3)'(0), Zm, (2*`NF+2)'(0)};
ZmShifted = {(`NF+2)'(0), Zm, (2*`NF+2)'(0)};//change
ZmSticky = ~(XZero|YZero);
// If the addend is too small to effect the addition
@ -90,12 +90,12 @@ module fmaalign(
// | addnend |
end else begin
ZmShifted = ZmPreshifted >> ACnt;
ZmSticky = |(ZmShifted[`NF-1:0]);
ZmSticky = |(ZmShifted[`NF-1:0]);
end
end
assign Am = ZmShifted[4*`NF+5:`NF];
assign Am = ZmShifted[4*`NF+4:`NF];//change
endmodule

2
pipelined/src/fpu/fma/fmalza.sv
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@ -42,7 +42,7 @@ module fmalza #(WIDTH) ( // [Schmookler & Nowka, Leading zero anticipation and d
logic [WIDTH-1:0] B, P, G, K;
logic [WIDTH-1:0] Pp1, Gm1, Km1;
assign B = {{(`NF+2){1'b0}}, Pm}; // Zero extend product
assign B = {{(`NF+1){1'b0}}, Pm};//change // Zero extend product
assign P = A^B;
assign G = A&B;

8
pipelined/src/fpu/fpu.sv
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@ -109,14 +109,14 @@ module fpu (
logic XExpMaxE; // is the exponent all ones (max value)
// Fma Signals
logic [3*`NF+5:0] SmE, SmM;
logic [3*`NF+4:0] SmE, SmM;//change
logic ZmStickyE, ZmStickyM;
logic [`NE+1:0] SeE,SeM;
logic InvAE, InvAM;
logic AsE, AsM;
logic PsE, PsM;
logic SsE, SsM;
logic [$clog2(3*`NF+7)-1:0] SCntE, SCntM;
logic [$clog2(3*`NF+6)-1:0] SCntE, SCntM;//change
// Cvt Signals
logic [`NE:0] CeE, CeM; // the calculated expoent
@ -352,8 +352,8 @@ module fpu (
{XsE, YsE, XZeroE, YZeroE, ZZeroE, XInfE, YInfE, ZInfE, XNaNE, YNaNE, ZNaNE, XSNaNE, YSNaNE, ZSNaNE, ZDenormE},
{XsM, YsM, XZeroM, YZeroM, ZZeroM, XInfM, YInfM, ZInfM, XNaNM, YNaNM, ZNaNM, XSNaNM, YSNaNM, ZSNaNM, ZDenormM});
flopenrc #(1) EMRegCmpFlg (clk, reset, FlushM, ~StallM, PreNVE, PreNVM);
flopenrc #(3*`NF+6) EMRegFma2(clk, reset, FlushM, ~StallM, SmE, SmM);
flopenrc #($clog2(3*`NF+7)+7+`NE) EMRegFma4(clk, reset, FlushM, ~StallM,
flopenrc #(3*`NF+5) EMRegFma2(clk, reset, FlushM, ~StallM, SmE, SmM);//change
flopenrc #($clog2(3*`NF+6)+7+`NE) EMRegFma4(clk, reset, FlushM, ~StallM, //change
{ZmStickyE, InvAE, SCntE, AsE, PsE, SsE, SeE},
{ZmStickyM, InvAM, SCntM, AsM, PsM, SsM, SeM});
flopenrc #(`NE+`LOGCVTLEN+`CVTLEN+4) EMRegCvt(clk, reset, FlushM, ~StallM,

14
pipelined/src/fpu/postproc/fmashiftcalc.sv
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@ -30,15 +30,15 @@
`include "wally-config.vh"
module fmashiftcalc(
input logic [3*`NF+5:0] FmaSm, // the positive sum
input logic [$clog2(3*`NF+7)-1:0] FmaSCnt, // normalization shift count
input logic [3*`NF+4:0] FmaSm,//change // the positive sum
input logic [$clog2(3*`NF+6)-1:0] FmaSCnt,//change // normalization shift count
input logic [`FMTBITS-1:0] Fmt, // precision 1 = double 0 = single
input logic [`NE+1:0] FmaSe,
output logic [`NE+1:0] NormSumExp, // exponent of the normalized sum not taking into account denormal or zero results
output logic FmaSZero, // is the result denormalized - calculated before LZA corection
output logic FmaPreResultDenorm, // is the result denormalized - calculated before LZA corection
output logic [$clog2(3*`NF+7)-1:0] FmaShiftAmt, // normalization shift count
output logic [3*`NF+7:0] FmaShiftIn // is the sum zero
output logic [$clog2(3*`NF+6)-1:0] FmaShiftAmt,//change // normalization shift count
output logic [3*`NF+6:0] FmaShiftIn//change // is the sum zero
);
logic [`NE+1:0] PreNormSumExp; // the exponent of the normalized sum with the `FLEN bias
logic [`NE+1:0] BiasCorr;
@ -50,7 +50,7 @@ module fmashiftcalc(
// Determine if the sum is zero
assign FmaSZero = ~(|FmaSm);
// calculate the sum's exponent
assign PreNormSumExp = FmaSe + {{`NE+2-$unsigned($clog2(3*`NF+7)){1'b1}}, ~FmaSCnt} + (`NE+2)'(`NF+4);
assign PreNormSumExp = FmaSe + {{`NE+2-$unsigned($clog2(3*`NF+6)){1'b1}}, ~FmaSCnt} + (`NE+2)'(`NF+3);//change
//convert the sum's exponent into the proper percision
if (`FPSIZES == 1) begin
@ -150,7 +150,7 @@ module fmashiftcalc(
// - shift once if killing a product and the result is denormalized
assign FmaShiftIn = {2'b0, FmaSm};
if (`FPSIZES == 1)
assign FmaShiftAmt = FmaPreResultDenorm ? FmaSe[$clog2(3*`NF+7)-1:0]+($clog2(3*`NF+7))'(`NF+3): FmaSCnt+1;
assign FmaShiftAmt = FmaPreResultDenorm ? FmaSe[$clog2(3*`NF+6)-1:0]+($clog2(3*`NF+6))'(`NF+2): FmaSCnt+1;//change
else
assign FmaShiftAmt = FmaPreResultDenorm ? FmaSe[$clog2(3*`NF+7)-1:0]+($clog2(3*`NF+7))'(`NF+3)+BiasCorr[$clog2(3*`NF+7)-1:0]: FmaSCnt+1;
assign FmaShiftAmt = FmaPreResultDenorm ? FmaSe[$clog2(3*`NF+6)-1:0]+($clog2(3*`NF+6))'(`NF+2)+BiasCorr[$clog2(3*`NF+6)-1:0]: FmaSCnt+1;//change
endmodule

12
pipelined/src/fpu/postproc/postprocess.sv
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@ -47,10 +47,10 @@ module postprocess (
input logic FmaAs, // the modified Z sign - depends on instruction
input logic FmaPs, // the product's sign
input logic [`NE+1:0] FmaSe,
input logic [3*`NF+5:0] FmaSm, // the positive sum
input logic [3*`NF+4:0] FmaSm,//change // the positive sum
input logic FmaZmS, // sticky bit that is calculated during alignment
input logic FmaSs,
input logic [$clog2(3*`NF+7)-1:0] FmaSCnt, // the normalization shift count
input logic [$clog2(3*`NF+6)-1:0] FmaSCnt,//change // the normalization shift count
//divide signals
input logic DivS,
// input logic DivDone,
@ -89,10 +89,10 @@ module postprocess (
// fma signals
logic [`NE+1:0] FmaMe; // exponent of the normalized sum
logic FmaSZero; // is the sum zero
logic [3*`NF+7:0] FmaShiftIn; // shift input
logic [3*`NF+6:0] FmaShiftIn;//change // shift input
logic [`NE+1:0] NormSumExp; // exponent of the normalized sum not taking into account denormal or zero results
logic FmaPreResultDenorm; // is the result denormalized - calculated before LZA corection
logic [$clog2(3*`NF+7)-1:0] FmaShiftAmt; // normalization shift count
logic [$clog2(3*`NF+6)-1:0] FmaShiftAmt;//change // normalization shift count
// division singals
logic [`LOGNORMSHIFTSZ-1:0] DivShiftAmt;
logic [`NORMSHIFTSZ-1:0] DivShiftIn;
@ -152,8 +152,8 @@ module postprocess (
always_comb
case(PostProcSel)
2'b10: begin // fma
ShiftAmt = {{`LOGNORMSHIFTSZ-$clog2(3*`NF+7){1'b0}}, FmaShiftAmt};
ShiftIn = {FmaShiftIn, {`NORMSHIFTSZ-(3*`NF+8){1'b0}}};
ShiftAmt = {{`LOGNORMSHIFTSZ-$clog2(3*`NF+6){1'b0}}, FmaShiftAmt};//change
ShiftIn = {FmaShiftIn, {`NORMSHIFTSZ-(3*`NF+7){1'b0}}};//change
end
2'b00: begin // cvt
ShiftAmt = {{`LOGNORMSHIFTSZ-$clog2(`CVTLEN+1){1'b0}}, CvtShiftAmt};

4
pipelined/src/fpu/postproc/shiftcorrection.sv
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@ -43,7 +43,7 @@ module shiftcorrection(
output logic [`NE+1:0] Qe,
output logic [`NE+1:0] FmaMe // exponent of the normalized sum
);
logic [3*`NF+5:0] CorrSumShifted; // the shifted sum after LZA correction
logic [3*`NF+4:0] CorrSumShifted;//change // the shifted sum after LZA correction
logic [`CORRSHIFTSZ-1:0] CorrQmShifted;
logic ResDenorm; // is the result denormalized
logic LZAPlus1; // add one or two to the sum's exponent due to LZA correction
@ -56,7 +56,7 @@ module shiftcorrection(
assign CorrQmShifted = (LZAPlus1|(DivQe==1&~LZAPlus1)) ? Shifted[`NORMSHIFTSZ-2:`NORMSHIFTSZ-`CORRSHIFTSZ-1] : Shifted[`NORMSHIFTSZ-3:`NORMSHIFTSZ-`CORRSHIFTSZ-2];
// if the result of the divider was calculated to be denormalized, then the result was correctly normalized, so select the top shifted bits
always_comb
if(FmaOp) Mf = {CorrSumShifted, {`CORRSHIFTSZ-(3*`NF+6){1'b0}}};
if(FmaOp) Mf = {CorrSumShifted, {`CORRSHIFTSZ-(3*`NF+5){1'b0}}};//change
else if (DivOp&~DivResDenorm) Mf = CorrQmShifted;
else Mf = Shifted[`NORMSHIFTSZ-1:`NORMSHIFTSZ-`CORRSHIFTSZ];
// Determine sum's exponent

4
pipelined/testbench/testbench-fp.sv
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@ -94,8 +94,8 @@ module testbenchfp;
logic [`NE+1:0] Se;
logic ZmSticky;
logic KillProd;
logic [$clog2(3*`NF+7)-1:0] SCnt;
logic [3*`NF+5:0] Sm;
logic [$clog2(3*`NF+6)-1:0] SCnt;
logic [3*`NF+4:0] Sm;
logic InvA;
logic NegSum;
logic As;