forked from Github_Repos/cvw
updated tests to reflect non-writeable bits of deleg
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@ -108,8 +108,8 @@
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00000000
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00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
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00000000
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fffff7ff # medeleg after attempted write of all 1's (only some bits are writeable)
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ffffffff
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0000b3ff # medeleg after attempted write of all 1's (only some bits are writeable)
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00000000
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00000222 # mideleg after attempted write of all 1's (only some bits are writeable)
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00000000 # skipping instruction address fault since they're impossible with compressed instrs enabled
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00000001 # mcause from an instruction access fault
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@ -98,8 +98,8 @@
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00000000
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00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0
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00000000
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fffff7ff # medeleg after attempted write of all 1's (only some bits are writeable)
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ffffffff
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0000b3ff # medeleg after attempted write of all 1's (only some bits are writeable)
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00000000
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00000222 # mideleg after attempted write of all 1's (only some bits are writeable)
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00000000
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0000000b # scause from M mode ecall
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@ -92,8 +92,8 @@
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00000000
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00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0
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00000000
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fffff7ff # medeleg after attempted write of all 1's (only some bits are writeable)
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ffffffff
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0000b3ff # medeleg after attempted write of all 1's (only some bits are writeable)
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00000000
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00000222 # mideleg after attempted write of all 1's (only some bits are writeable)
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00000000
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0000000b # scause from M mode ecall
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