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Merge branch 'main' of https://github.com/openhwgroup/cvw

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This commit is contained in:
Ross Thompson 2023-03-09 13:29:38 -06:00
commit fa8a550e12
8 changed files with 91 additions and 42 deletions
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2
config/rv32gc/wally-config.vh
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@ -43,7 +43,7 @@
`define COUNTERS 32
`define ZICOUNTERS_SUPPORTED 1
`define ZFH_SUPPORTED 0
`define SSTC_SUPPORTED 0
`define SSTC_SUPPORTED 1
// LSU microarchitectural Features
`define BUS_SUPPORTED 1

2
config/rv64gc/wally-config.vh
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@ -44,7 +44,7 @@
`define COUNTERS 32
`define ZICOUNTERS_SUPPORTED 1
`define ZFH_SUPPORTED 0
`define SSTC_SUPPORTED 0
`define SSTC_SUPPORTED 1
// LSU microarchitectural Features
`define BUS_SUPPORTED 1

7
sim/imperas.ic
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@ -1,12 +1,14 @@
#--showoverrides
#--help --helpall
--traceregs
--override cpu/show_c_prefix=T
--override cpu/unaligned=F
--override cpu/ignore_non_leaf_DAU=1
--override cpu/wfi_is_nop=T
# this should be 16 not 0
--override cpu/PMP_registers=0
# Enable the Imperas instruction coverage
#-extlib refRoot/cpu/cv=imperas.com/intercept/riscvInstructionCoverage/1.0
#-override refRoot/cpu/cv/cover=basic
@ -32,9 +34,6 @@
# Store simulator output to logfile
--output imperas.log
--override cpu/PMP_registers=0
#--showoverrides
#--mpdconsole
# ignore settings of bits DAU for non leaf page table walks
--override cpu/ignore_non_leaf_DAU=1

6
src/privileged/csrs.sv
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@ -102,10 +102,10 @@ module csrs #(parameter
flopens #(32) SCOUNTERENreg(clk, reset, WriteSCOUNTERENM, CSRWriteValM[31:0], SCOUNTEREN_REGW);
if (`SSTC_SUPPORTED) begin
if (`XLEN == 64)
flopenr #(`XLEN) STIMECMPreg(clk, reset, WriteSTIMECMPM, CSRWriteValM, STIMECMP_REGW);
flopenl #(`XLEN) STIMECMPreg(clk, reset, WriteSTIMECMPM, CSRWriteValM, 64'hFFFFFFFFFFFFFFFF, STIMECMP_REGW);
else begin
flopenr #(`XLEN) STIMECMPreg(clk, reset, WriteSTIMECMPM, CSRWriteValM, STIMECMP_REGW[31:0]);
flopenr #(`XLEN) STIMECMPHreg(clk, reset, WriteSTIMECMPHM, CSRWriteValM, STIMECMP_REGW[63:32]);
flopenl #(`XLEN) STIMECMPreg(clk, reset, WriteSTIMECMPM, CSRWriteValM, 32'hFFFFFFFF, STIMECMP_REGW[31:0]);
flopenl #(`XLEN) STIMECMPHreg(clk, reset, WriteSTIMECMPHM, CSRWriteValM, 32'hFFFFFFFF, STIMECMP_REGW[63:32]);
end
end else assign STIMECMP_REGW = 0;

31
testbench/common/wallyTracer.sv
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@ -98,6 +98,37 @@ module wallyTracer(rvviTrace rvvi);
if(valid) begin
// machine CSRs
// *** missing PMP and performance counters.
// PMPCFG space is 0-15 3a0 - 3af
int i, i4, i8, csrid;
logic [`XLEN-1:0] pmp;
for (i=0; i<`PMP_ENTRIES; i+=8) begin
i4 = i / 4;
i8 = (i / 8) * 8;
pmp = 0;
pmp |= testbench.dut.core.priv.priv.csr.csrm.PMPCFG_ARRAY_REGW[i8+0] << 0;
pmp |= testbench.dut.core.priv.priv.csr.csrm.PMPCFG_ARRAY_REGW[i8+1] << 8;
pmp |= testbench.dut.core.priv.priv.csr.csrm.PMPCFG_ARRAY_REGW[i8+2] << 16;
pmp |= testbench.dut.core.priv.priv.csr.csrm.PMPCFG_ARRAY_REGW[i8+3] << 24;
pmp |= testbench.dut.core.priv.priv.csr.csrm.PMPCFG_ARRAY_REGW[i8+4] << 32;
pmp |= testbench.dut.core.priv.priv.csr.csrm.PMPCFG_ARRAY_REGW[i8+5] << 40;
pmp |= testbench.dut.core.priv.priv.csr.csrm.PMPCFG_ARRAY_REGW[i8+6] << 48;
pmp |= testbench.dut.core.priv.priv.csr.csrm.PMPCFG_ARRAY_REGW[i8+7] << 56;
csrid = 12'h3A0 + i4;
//if (CSRArray[csrid] != pmp) $display("Info: %m pmpcfg%0d [%03X] %016X -> %016X", i4, csrid, CSRArray[csrid], pmp);
CSRArray[csrid] = pmp;
end
// PMPADDR space is 0-63 3b0 - 3ef
for (i=0; i<`PMP_ENTRIES; i++) begin
pmp = testbench.dut.core.priv.priv.csr.csrm.PMPADDR_ARRAY_REGW[i];
csrid = 12'h3B0 + i;
//if (CSRArray[csrid] != pmp) $display("Info: %m Change pmpaddr%0d [%03X] %016X -> %016X", i, csrid, CSRArray[csrid], pmp);
CSRArray[csrid] = pmp;
end
CSRArray[12'h300] = testbench.dut.core.priv.priv.csr.csrm.MSTATUS_REGW;
CSRArray[12'h310] = testbench.dut.core.priv.priv.csr.csrm.MSTATUSH_REGW;
CSRArray[12'h305] = testbench.dut.core.priv.priv.csr.csrm.MTVEC_REGW;

25
testbench/testbench_imperas.sv
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@ -27,7 +27,7 @@
`include "wally-config.vh"
// This is set from the commsnd line script
// This is set from the command line script
// `define USE_IMPERAS_DV
`ifdef USE_IMPERAS_DV
@ -121,10 +121,11 @@ module testbench;
end
rvviTrace #(.XLEN(`XLEN), .FLEN(`FLEN)) rvvi();
wallyTracer wallyTracer(rvvi);
`ifdef USE_IMPERAS_DV
rvviTrace #(.XLEN(`XLEN), .FLEN(`FLEN)) rvvi();
wallyTracer wallyTracer(rvvi);
trace2log idv_trace2log(rvvi);
trace2cov idv_trace2cov(rvvi);
@ -139,6 +140,7 @@ module testbench;
int PRIV_RWX = RVVI_MEMORY_PRIVILEGE_READ | RVVI_MEMORY_PRIVILEGE_WRITE | RVVI_MEMORY_PRIVILEGE_EXEC;
int PRIV_RW = RVVI_MEMORY_PRIVILEGE_READ | RVVI_MEMORY_PRIVILEGE_WRITE;
int PRIV_RX = RVVI_MEMORY_PRIVILEGE_READ | RVVI_MEMORY_PRIVILEGE_EXEC;
int PRIV_X = RVVI_MEMORY_PRIVILEGE_EXEC;
initial begin
@ -170,11 +172,12 @@ module testbench;
// pending and taken
void'(rvviRefCsrSetVolatile(0, 32'h344)); // MIP
void'(rvviRefCsrSetVolatile(0, 32'h144)); // SIP
/*
// Memory lo, hi, priv (RVVI_MEMORY_PRIVILEGE_{READ,WRITE,EXEC})
void'(rvviRefMemorySetPrivilege(56'h0, 56'h7fffffffff, 0));
if (`BOOTROM_SUPPORTED)
void'(rvviRefMemorySetPrivilege(`BOOTROM_BASE, (`BOOTROM_BASE + `BOOTROM_RANGE), PRIV_X));
void'(rvviRefMemorySetPrivilege(`BOOTROM_BASE, (`BOOTROM_BASE + `BOOTROM_RANGE), PRIV_RX));
if (`UNCORE_RAM_SUPPORTED)
void'(rvviRefMemorySetPrivilege(`UNCORE_RAM_BASE, (`UNCORE_RAM_BASE + `UNCORE_RAM_RANGE), PRIV_RWX));
if (`EXT_MEM_SUPPORTED)
@ -200,6 +203,7 @@ module testbench;
void'(rvviRefMemorySetPrivilege(`SDC_BASE, (`SDC_BASE + `SDC_RANGE), PRIV_RW));
void'(rvviRefMemorySetVolatile(`SDC_BASE, (`SDC_BASE + `SDC_RANGE)));
end
*/
if(`XLEN==32) begin
void'(rvviRefCsrSetVolatile(0, 32'hC80)); // CYCLEH
@ -210,15 +214,6 @@ module testbench;
void'(rvviRefCsrSetVolatile(0, 32'h104)); // SIE - Temporary!!!!
// These should be done in the attached client
// // Enable the trace2log module
// if ($value$plusargs("TRACE2LOG_ENABLE=%d", TRACE2LOG_ENABLE)) begin
// msgnote($sformatf("%m @ t=%0t: TRACE2LOG_ENABLE is %0d", $time, TRACE2LOG_ENABLE));
// end
//
// if ($value$plusargs("TRACE2COV_ENABLE=%d", TRACE2COV_ENABLE)) begin
// msgnote($sformatf("%m @ t=%0t: TRACE2COV_ENABLE is %0d", $time, TRACE2COV_ENABLE));
// end
end
always @(dut.core.MTimerInt) void'(rvvi.net_push("MTimerInterrupt", dut.core.MTimerInt));

33
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-TEST-LIB-32.h
View File

@ -125,20 +125,31 @@ cause_m_time_interrupt:
lw t2, 0(t5) // low word of MTIME
lw t6, 4(t5) // high word of MTIME
add t3, t2, t3 // add desired offset to the current time
bgtu t3, t2, nowrap // check new time exceeds current time (no wraparound)
bgtu t3, t2, nowrap_m // check new time exceeds current time (no wraparound)
addi t6, t6, 1 // if wrap, increment most significant word
sw t6,4(t4) // store into most significant word of MTIMECMP
nowrap:
nowrap_m:
sw t3, 0(t4) // store into least significant word of MTIMECMP
time_loop:
time_loop_m:
addi a3, a3, -1
bnez a3, time_loop // go through this loop for [a3 value] iterations before returning without performing interrupt
bnez a3, time_loop_m // go through this loop for [a3 value] iterations before returning without performing interrupt
ret
cause_s_time_interrupt:
li t3, 0x20
csrs mip, t3 // set supervisor time interrupt pending. SIP is a subset of MIP, so writing this should also change MIP.
nop // added extra nops in so the csrs can get through the pipeline before returning.
li t3, 0x30 // Desired offset from the present time
mv a3, t3 // copy value in to know to stop waiting for interrupt after this many cycles
la t5, 0x0200BFF8 // MTIME register in CLINT *** we still read from mtime since stimecmp is compared to it
lw t2, 0(t5) // low word of MTIME
lw t6, 4(t5) // high word of MTIME
add t3, t2, t3 // add desired offset to the current time
bgtu t3, t2, nowrap_s // check new time exceeds current time (no wraparound)
addi t6, t6, 1 // if wrap, increment most significant word
nowrap_s:
csrw stimecmp, t3 // store into STIMECMP
csrw stimecmph, t6 // store into STIMECMPH
time_loop_s:
addi a3, a3, -1
bnez a3, time_loop_s // go through this loop for [a3 value] iterations before returning without performing interrupt
ret
cause_m_soft_interrupt:
@ -545,8 +556,12 @@ soft_interrupt_\MODE\():
time_interrupt_\MODE\():
la t0, 0x02004000 // MTIMECMP register in CLINT
li t2, 0xFFFFFFFF
sw t2, 0(t0) // reset interrupt by setting mtimecmp to 0xFFFFFFFF
sw t2, 0(t0) // reset interrupt by setting mtimecmp to max
//sw t2, 4(t0) // reset interrupt by setting mtimecmpH to max
csrw stimecmp, t2 // reset stime interrupts by doing the same to stimecmp and stimecmpH.
csrw stimecmph, t2
li t0, 0x20
csrc \MODE\()ip, t0
lw ra, -4(sp) // load return address from stack into ra (the address to return to after the loop is complete)

27
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-TEST-LIB-64.h
View File

@ -127,22 +127,30 @@ cause_m_time_interrupt:
lw t2, 0(t5) // low word of MTIME
lw t6, 4(t5) // high word of MTIME
add t3, t2, t3 // add desired offset to the current time
bgtu t3, t2, nowrap // check new time exceeds current time (no wraparound)
bgtu t3, t2, nowrap_m // check new time exceeds current time (no wraparound)
addi t6, t6, 1 // if wrap, increment most significant word
sw t6,4(t4) // store into most significant word of MTIMECMP
nowrap:
nowrap_m:
sw t3, 0(t4) // store into least significant word of MTIMECMP
time_loop:
time_loop_m:
addi a3, a3, -1
bnez a3, time_loop // go through this loop for [a3 value] iterations before returning without performing interrupt
bnez a3, time_loop_m // go through this loop for [a3 value] iterations before returning without performing interrupt
ret
cause_s_time_interrupt:
li t3, 0x20
csrs mip, t3 // set supervisor time interrupt pending.
nop // added extra nops in so the csrs can get through the pipeline before returning.
li t3, 0x30 // Desired offset from the present time
mv a3, t3 // copy value in to know to stop waiting for interrupt after this many cycles
// la t4, 0x02004000 // MTIMECMP register in CLINT
la t5, 0x0200BFF8 // MTIME register in CLINT *** we still read from mtime since stimecmp is compared to it
lw t2, 0(t5) // low word of MTIME
lw t6, 4(t5) // high word of MTIME
add t3, t2, t3 // add desired offset to the current time
csrw stimecmp, t3 // store into most significant word of STIMECMP
time_loop_s:
addi a3, a3, -1
bnez a3, time_loop_s // go through this loop for [a3 value] iterations before returning without performing interrupt
ret
cause_m_soft_interrupt:
la t3, 0x02000000 // MSIP register in CLINT
li t4, 1 // 1 in the lsb
@ -539,7 +547,8 @@ soft_interrupt_\MODE\():
time_interrupt_\MODE\():
la t0, 0x02004000 // MTIMECMP register in CLINT
li t2, 0xFFFFFFFF
sd t2, 0(t0) // reset interrupt by setting mtimecmp to 0xFFFFFFFF
sd t2, 0(t0) // reset interrupt by setting mtimecmp to max
csrw stimecmp, t2 // reset stime interrupts by doing the same.
li t0, 0x20
csrc \MODE\()ip, t0