Moved CPUBusy out of HPTW.

pipelined/src/lsu/lsu.sv

@@ -129,18 +129,18 @@ module lsu (
   /////////////////////////////////////////////////////////////////////////////////////////////
 
   if(`VIRTMEM_SUPPORTED) begin : VIRTMEM_SUPPORTED
-    hptw hptw(.clk, .reset, .StallW, .MemRWM, .AtomicM, .ITLBMissF, .ITLBWriteF,
+    hptw hptw(.clk, .reset, .MemRWM, .AtomicM, .ITLBMissF, .ITLBWriteF,
       .DTLBMissM, .DTLBWriteM, .InstrDAPageFaultF, .DataDAPageFaultM,
       .FlushW, .DCacheStallM, .SATP_REGW, .PCF,
       .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP, .PrivilegeModeW,
       .ReadDataM(ReadDataM[`XLEN-1:0]), .WriteDataM, .Funct3M, .LSUFunct3M, .Funct7M, .LSUFunct7M,
       .IEUAdrExtM, .PTE, .IHWriteDataM, .PageType, .PreLSURWM, .LSUAtomicM,
-      .IHAdrM, .CPUBusy, .HPTWStall, .SelHPTW,
+      .IHAdrM, .HPTWStall, .SelHPTW,
       .IgnoreRequestTLB, .LSULoadAccessFaultM, .LSUStoreAmoAccessFaultM, 
       .LoadAccessFaultM, .StoreAmoAccessFaultM, .HPTWInstrAccessFaultM);
   end else begin
     assign {HPTWStall, SelHPTW, PTE, PageType, DTLBWriteM, ITLBWriteF, IgnoreRequestTLB} = '0;
-    assign CPUBusy = StallW; assign PreLSURWM = MemRWM; 
+    assign PreLSURWM = MemRWM; 
     assign IHAdrM = IEUAdrExtM;
     assign LSUFunct3M = Funct3M;  assign LSUFunct7M = Funct7M; assign LSUAtomicM = AtomicM;
     assign IHWriteDataM = WriteDataM;
@@ -155,6 +155,7 @@ module lsu (
   // There is not a clean way to restore back to a partial executed instruction.  CommiteedM will
   // delay the interrupt until the LSU is in a clean state.
   assign CommittedM = SelHPTW | DCacheCommittedM | BusCommittedM;
+  assign CPUBusy = StallW & ~SelHPTW;
 
   // MMU and Misalignment fault logic required if privileged unit exists
   if(`ZICSR_SUPPORTED == 1) begin : dmmu

pipelined/src/mmu/hptw.sv

@@ -31,7 +31,7 @@
 `include "wally-config.vh"
 
 module hptw (
-	input logic                 clk, reset, StallW,
+	input logic                 clk, reset,
    	input logic [`XLEN-1:0]     SATP_REGW, // includes SATP.MODE to determine number of levels in page table
 	input logic [`XLEN-1:0]     PCF,  // addresses to translate
  	input logic [`XLEN+1:0]     IEUAdrExtM, // addresses to translate
@@ -61,7 +61,6 @@ module hptw (
    	output logic [6:0]          LSUFunct7M,
    	output logic IgnoreRequestTLB,
    	output logic SelHPTW,
-   	output logic                CPUBusy,
    	output logic HPTWStall,
     input logic  LSULoadAccessFaultM, LSUStoreAmoAccessFaultM, 
     output logic LoadAccessFaultM, StoreAmoAccessFaultM, HPTWInstrAccessFaultM
@@ -291,7 +290,6 @@ module hptw (
   // to the orignal data virtual address.
   assign SelHPTWAdr = SelHPTW & ~(DTLBWriteM | ITLBWriteF);
   // always block interrupts when using the hardware page table walker.
-  assign CPUBusy = StallW & ~SelHPTW;
 
   // multiplex the outputs to LSU
   if(`XLEN == 64) assign HPTWAdrExt = {{(`XLEN+2-`PA_BITS){1'b0}}, HPTWAdr}; // extend to 66 bits