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Continue fixing memory macros for synthesis

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This commit is contained in:
David Harris 2023-02-17 15:15:37 -08:00
parent 3523318acb
commit 2060683770
8 changed files with 8 additions and 8 deletions
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2
src/generic/mem/ram1p1rwbe_64x128.sv
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@ -36,6 +36,6 @@ module ram1p1rwbe_64x128(
// replace "generic64x128RAM" with "TS1N..64X128.." module from your memory vendor
//generic64x128RAM sramIP (.CLK, .CEB, .WEB, .A, .D, .BWEB, .Q);
ts1n28hpcpsvtb64x128m4sw_180a sramIP(.CLK, .CEB, .WEB, .A, .D, .BWEB, .Q);
TS1N28HPCPSVTB64X128M4SW sramIP(.CLK, .CEB, .WEB, .A, .D, .BWEB, .Q);
endmodule

2
src/generic/mem/ram1p1rwbe_64x22.sv
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@ -36,7 +36,7 @@ module ram1p1rwbe_64x22(
// replace "generic64x22RAM" with "TS1N..64X22.." module from your memory vendor
// use part of a larger RAM to avoid generating more flavors of RAM
ts1n28hpcpsvtb64x44m4sw_180a sramIP(.CLK, .CEB, .WEB, .A, .D(D[21:0]), .BWEB(BWEB[21:0]), .Q(Q[21:0]));
TS1N28HPCPSVTB64X44M4SW sramIP(.CLK, .CEB, .WEB, .A, .D(D[21:0]), .BWEB(BWEB[21:0]), .Q(Q[21:0]));
//generic64x22RAM sramIP (.CLK, .CEB, .WEB, .A, .D, .BWEB, .Q);
endmodule

2
src/generic/mem/ram1p1rwbe_64x44.sv
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@ -36,6 +36,6 @@ module ram1p1rwbe_64x44(
// replace "generic64x44RAM" with "TS1N..64X44.." module from your memory vendor
// generic64x44RAM sramIP (.CLK, .CEB, .WEB, .A, .D, .BWEB, .Q);
ts1n28hpcpsvtb64x44m4sw_180a sramIP(.CLK, .CEB, .WEB, .A, .D, .BWEB, .Q);
TS1N28HPCPSVTB64X44M4SW sramIP(.CLK, .CEB, .WEB, .A, .D, .BWEB, .Q);
endmodule

2
src/generic/mem/ram2p1r1wbe_1024x36.sv
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@ -45,7 +45,7 @@ module ram2p1r1wbe_1024x36(
//generic1024x36RAM sramIP (.CLKA, .CLKB, .CEBA, .CEBB, .WEBA, .WEBB,
// .AA, .AB, .DA, .DB, .BWEBA, .BWEBB, .QA, .QB);
// use part of a larger RAM to avoid generating more flavors of RAM
tsdn28hpcpa1024x68m4mw_130a sramIP(.CLKA, .CLKB, .CEBA, .CEBB, .WEBA, .WEBB,
TSDN28HPCPA1024X68M4MW sramIP(.CLKA, .CLKB, .CEBA, .CEBB, .WEBA, .WEBB,
.AA, .AB, .DA(DA[35:0]), .DB(DB[35:0]),
.BWEBA(BWEBA[35:0]), .BWEBB(BWEBB[35:0]), .QA(QA[35:0]), .QB(QB[35:0]));

2
src/generic/mem/ram2p1r1wbe_1024x68.sv
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@ -44,7 +44,7 @@ module ram2p1r1wbe_1024x68(
// replace "generic1024x68RAM" with "TSDN..1024X68.." module from your memory vendor
//generic1024x68RAM sramIP (.CLKA, .CLKB, .CEBA, .CEBB, .WEBA, .WEBB,
// .AA, .AB, .DA, .DB, .BWEBA, .BWEBB, .QA, .QB);
tsdn28hpcpa1024x68m4mw_130a sramIP(.CLKA, .CLKB, .CEBA, .CEBB, .WEBA, .WEBB,
TSDN28HPCPA1024X68M4MW sramIP(.CLKA, .CLKB, .CEBA, .CEBB, .WEBA, .WEBB,
.AA, .AB, .DA, .DB, .BWEBA, .BWEBB, .QA, .QB);
endmodule

2
src/generic/mem/ram2p1r1wbe_64x32.sv
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@ -46,6 +46,6 @@ module ram2p1r1wbe_64x32(
// .AA, .AB, .DA, .DB, .BWEBA, .BWEBB, .QA, .QB);
//generic64x32RAM sramIP (.CLKA, .CLKB, .CEBA, .CEBB, .WEBA, .WEBB,
// .AA, .AB, .DA, .DB, .BWEBA, .BWEBB, .QA, .QB);
tsdn28hpcpa64x32m4mw_130a sramIP(.CLKA, .CLKB, .CEBA, .CEBB, .WEBA, .WEBB,
TSDN28HPCPA64X32M4MW sramIP(.CLKA, .CLKB, .CEBA, .CEBB, .WEBA, .WEBB,
.AA, .AB, .DA, .DB, .BWEBA, .BWEBB, .QA, .QB);
endmodule

2
synthDC/.synopsys_dc.setup
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@ -67,7 +67,7 @@ set cache_read $cache_write
lappend search_path ./scripts
lappend search_path ./hdl
lappend search_path ./mapped
if {$tech == "tsmc28"} {
if {$tech == "tsmc28" || $tech == "tsmc28psyn"} {
set memory /home/jstine/WallyMem/rv64gc/
lappend target_library $memory/ts3n28hpcpa128x64m8m_130a/NLDM/ts3n28hpcpa128x64m8m_tt0p9v25c.db
lappend target_library $memory/ts1n28hpcpsvtb64x128m4sw_180a/NLDM/ts1n28hpcpsvtb64x128m4sw_tt0p9v25c.db

2
synthDC/extractSummary.py
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@ -85,7 +85,7 @@ def freqPlot(tech, width, config):
freqsL, delaysL, areasL = ([[], []] for i in range(3))
for oneSynth in allSynths:
if (width == oneSynth.width) & (config == oneSynth.config) & (tech == oneSynth.tech) & ('orig' == oneSynth.mod):
ind = (1000/oneSynth.delay < oneSynth.freq) # when delay is within target clock period
ind = (1000/oneSynth.delay < (0.95*oneSynth.freq)) # when delay is within target clock period
freqsL[ind] += [oneSynth.freq]
delaysL[ind] += [oneSynth.delay]
areasL[ind] += [oneSynth.area]