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Found possible optimization as the way selection is shared in cache, cacheway, and cachelru.

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Ross Thompson 2022-12-04 01:20:51 -06:00
parent 62e495c739
commit 74d5ccc2b1
1 changed files with 1 additions and 1 deletions
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pipelined/src/cache/cacheway.sv vendored
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@ -85,7 +85,7 @@ module cacheway #(parameter NUMLINES=512, parameter LINELEN = 256, TAGLEN = 26,
mux2 #(1) selectedwaymux(HitWay, SelTag, SelFlush | SetValid, SelectedWay);
// RT: Can we merge these two muxes?
// RT: Can we merge these two muxes? This is also shared in cacheLRU.
// mux3 #(1) selectwaymux(HitWay, VictimWay, FlushWay, {SelFlush, SetValid}, SelectedWay);
//mux3 #(1) selecteddatamux(HitWay, VictimWay, FlushWay, {SelFlush, SelEvict}, SelData);