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FPU cleanup

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This commit is contained in:
David Harris 2023-01-11 12:27:00 -08:00
parent 4ff2627a50
commit 99ff78b902
9 changed files with 12 additions and 16 deletions
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2
pipelined/src/fpu/fclassify.sv
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@ -4,7 +4,7 @@
// Written: me@KatherineParry.com
// Modified: 7/5/2022
//
// Purpose: classify unit
// Purpose: Floating-point classify unit
//
// A component of the Wally configurable RISC-V project.
//

2
pipelined/src/fpu/fcmp.sv
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@ -5,7 +5,7 @@
// Written: me@KatherineParry.com
// Modified: 7/5/2022
//
// Purpose: Comparison unit
// Purpose: Floating-point comparison unit
//
// A component of the Wally configurable RISC-V project.
//

2
pipelined/src/fpu/fctrl.sv
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@ -4,7 +4,7 @@
// Written: me@KatherineParry.com
// Modified: 7/5/2022
//
// Purpose: control unit
// Purpose: floating-point control unit
//
// A component of the Wally configurable RISC-V project.
//

2
pipelined/src/fpu/fregfile.sv
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@ -4,7 +4,7 @@
// Written: David_Harris@hmc.edu 9 January 2021
// Modified: James Stine
//
// Purpose: 3-port output register file
// Purpose: 3R1W 4-port register file for FPU
//
// A component of the Wally configurable RISC-V project.
//

2
pipelined/src/fpu/postproc/divshiftcalc.sv
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@ -4,7 +4,7 @@
// Written: me@KatherineParry.com
// Modified: 7/5/2022
//
// Purpose: Conversion shift calculation
// Purpose: Division shift calculation
//
// A component of the Wally configurable RISC-V project.
//

2
pipelined/src/fpu/postproc/fmashiftcalc.sv
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@ -4,7 +4,7 @@
// Written: me@KatherineParry.com
// Modified: 7/5/2022
//
// Purpose: Fma shift calculation
// Purpose: FMA shift calculation
//
// A component of the Wally configurable RISC-V project.
//

12
pipelined/src/fpu/postproc/negateintres.sv
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@ -35,16 +35,12 @@ module negateintres(
output logic [`XLEN+1:0] CvtNegRes
);
logic [2:0] CvtNegResMsbs3;
// round and negate the positive res if needed
assign CvtNegRes = Xs ? -({2'b0, Shifted[`NORMSHIFTSZ-1:`NORMSHIFTSZ-`XLEN]}+{{`XLEN+1{1'b0}}, Plus1}) : {2'b0, Shifted[`NORMSHIFTSZ-1:`NORMSHIFTSZ-`XLEN]}+{{`XLEN+1{1'b0}}, Plus1};
always_comb
if(Signed)
if(Int64) CvtNegResMsbs = CvtNegRes[`XLEN:`XLEN-1];
else CvtNegResMsbs = CvtNegRes[32:31];
else
if(Int64) CvtNegResMsbs = CvtNegRes[`XLEN+1:`XLEN];
else CvtNegResMsbs = CvtNegRes[33:32];
// select 2 most significant bits
mux2 #(3) msb3mux(CvtNegRes[33:31], CvtNegRes[`XLEN+1:`XLEN-1], Int64, CvtNegResMsbs3);
mux2 #(2) msb2mux(CvtNegResMsbs3[2:1], CvtNegRes[1:0], Signed, CvtNegResMsbs);
endmodule

2
pipelined/src/fpu/unpack.sv
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@ -4,7 +4,7 @@
// Written: me@KatherineParry.com
// Modified: 7/5/2022
//
// Purpose: unpack all inputs
// Purpose: unpack X, Y, Z floating-point inputs
//
// A component of the Wally configurable RISC-V project.
//

2
pipelined/src/fpu/unpackinput.sv
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@ -4,7 +4,7 @@
// Written: me@KatherineParry.com
// Modified: 7/5/2022
//
// Purpose: unpack input
// Purpose: unpack input: extract sign, exponent, significand, characteristics
//
// A component of the Wally configurable RISC-V project.
//