forked from Github_Repos/cvw
testbench code visual improvements
This commit is contained in:
Limnanthes Serafini
parent
38349e6a4f
commit
0862688168
@ -52,29 +52,29 @@ module testbench;
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string tests[];
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logic [3:0] dummy;
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logic [`AHBW-1:0] HRDATAEXT;
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logic HREADYEXT, HRESPEXT;
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logic [`AHBW-1:0] HRDATAEXT;
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logic HREADYEXT, HRESPEXT;
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logic [`PA_BITS-1:0] HADDR;
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logic [`AHBW-1:0] HWDATA;
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logic [`XLEN/8-1:0] HWSTRB;
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logic HWRITE;
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logic [2:0] HSIZE;
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logic [2:0] HBURST;
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logic [3:0] HPROT;
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logic [1:0] HTRANS;
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logic HMASTLOCK;
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logic HCLK, HRESETn;
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logic [`XLEN-1:0] PCW;
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logic [`AHBW-1:0] HWDATA;
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logic [`XLEN/8-1:0] HWSTRB;
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logic HWRITE;
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logic [2:0] HSIZE;
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logic [2:0] HBURST;
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logic [3:0] HPROT;
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logic [1:0] HTRANS;
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logic HMASTLOCK;
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logic HCLK, HRESETn;
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logic [`XLEN-1:0] PCW;
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string ProgramAddrMapFile, ProgramLabelMapFile;
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integer ProgramAddrLabelArray [string] = '{ "begin_signature" : 0, "tohost" : 0 };
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string ProgramAddrMapFile, ProgramLabelMapFile;
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integer ProgramAddrLabelArray [string] = '{ "begin_signature" : 0, "tohost" : 0 };
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logic DCacheFlushDone, DCacheFlushStart;
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logic DCacheFlushDone, DCacheFlushStart;
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logic riscofTest;
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logic StartSample, EndSample;
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flopenr #(`XLEN) PCWReg(clk, reset, ~dut.core.ieu.dp.StallW, dut.core.ifu.PCM, PCW);
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flopenr #(32) InstrWReg(clk, reset, ~dut.core.ieu.dp.StallW, dut.core.ifu.InstrM, InstrW);
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flopenr #(32) InstrWReg(clk, reset, ~dut.core.ieu.dp.StallW, dut.core.ifu.InstrM, InstrW);
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// check assertions for a legal configuration
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riscvassertions riscvassertions();
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@ -149,7 +149,7 @@ module testbench;
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end
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end
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string signame, memfilename, pathname, objdumpfilename, adrstr, outputfile;
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string signame, memfilename, pathname, objdumpfilename, adrstr, outputfile;
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integer outputFilePointer;
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logic [31:0] GPIOIN, GPIOOUT, GPIOEN;
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@ -160,16 +160,16 @@ module testbench;
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logic SDCCmdOut;
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logic SDCCmdOE;
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logic [3:0] SDCDatIn;
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tri1 [3:0] SDCDat;
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tri1 [3:0] SDCDat;
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tri1 SDCCmd;
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logic HREADY;
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logic HSELEXT;
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logic InitializingMemories;
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logic InitializingMemories;
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integer ResetCount, ResetThreshold;
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logic InReset;
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logic Begin;
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logic InReset;
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logic BeginSample;
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// instantiate device to be tested
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assign GPIOIN = 0;
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@ -225,13 +225,14 @@ module testbench;
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totalerrors = 0;
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testadr = 0;
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testadrNoBase = 0;
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// riscof tests have a different signature, tests[0] == "1" refers to RiscvArchTests and tests[0] == "2" refers to WallyRiscvArchTests
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// riscof tests have a different signature, tests[0] == "1" refers to RiscvArchTests
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// and tests[0] == "2" refers to WallyRiscvArchTests
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riscofTest = tests[0] == "1" | tests[0] == "2";
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// fill memory with defined values to reduce Xs in simulation
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// Quick note the memory will need to be initialized. The C library does not
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// guarantee the initialized reads. For example a strcmp can read 6 byte
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// strings, but uses a load double to read them in. If the last 2 bytes are
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// not initialized the compare results in an 'x' which propagates through
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// guarantee the initialized reads. For example a strcmp can read 6 byte
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// strings, but uses a load double to read them in. If the last 2 bytes are
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// not initialized the compare results in an 'x' which propagates through
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// the design.
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if (TEST == "coremark")
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for (i=MemStartAddr; i<MemEndAddr; i = i+1)
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@ -243,7 +244,7 @@ module testbench;
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pathname = tvpaths[0];
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else pathname = tvpaths[1]; */
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if (riscofTest) memfilename = {pathname, tests[test], "/ref/ref.elf.memfile"};
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else memfilename = {pathname, tests[test], ".elf.memfile"};
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else memfilename = {pathname, tests[test], ".elf.memfile"};
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if (`FPGA) begin
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string romfilename, sdcfilename;
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romfilename = {"../tests/custom/fpga-test-sdc/bin/fpga-test-sdc.memfile"};
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@ -253,9 +254,9 @@ module testbench;
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// force sdc timers
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force dut.uncore.uncore.sdc.SDC.LimitTimers = 1;
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end else begin
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if (`IROM_SUPPORTED) $readmemh(memfilename, dut.core.ifu.irom.irom.rom.ROM);
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if (`IROM_SUPPORTED) $readmemh(memfilename, dut.core.ifu.irom.irom.rom.ROM);
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else if (`BUS_SUPPORTED) $readmemh(memfilename, dut.uncore.uncore.ram.ram.memory.RAM);
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if (`DTIM_SUPPORTED) $readmemh(memfilename, dut.core.lsu.dtim.dtim.ram.RAM);
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if (`DTIM_SUPPORTED) $readmemh(memfilename, dut.core.lsu.dtim.dtim.ram.RAM);
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end
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if (riscofTest) begin
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@ -265,8 +266,9 @@ module testbench;
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ProgramAddrMapFile = {pathname, tests[test], ".elf.objdump.addr"};
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ProgramLabelMapFile = {pathname, tests[test], ".elf.objdump.lab"};
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end
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// declare memory labels that interest us, the updateProgramAddrLabelArray task will find the addr of each label and fill the array
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// to expand, add more elements to this array and initialize them to zero (also initilaize them to zero at the start of the next test)
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// declare memory labels that interest us, the updateProgramAddrLabelArray task will find
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// the addr of each label and fill the array. To expand, add more elements to this array
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// and initialize them to zero (also initilaize them to zero at the start of the next test)
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if(!`FPGA) begin
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updateProgramAddrLabelArray(ProgramAddrMapFile, ProgramLabelMapFile, ProgramAddrLabelArray);
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$display("Read memfile %s", memfilename);
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@ -294,99 +296,99 @@ module testbench;
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ResetCount = 0;
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end
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end else begin
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if (TEST == "coremark")
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if (TEST == "coremark")
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if (dut.core.priv.priv.EcallFaultM) begin
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$display("Benchmark: coremark is done.");
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$stop;
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$display("Benchmark: coremark is done.");
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$stop;
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end
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// Termination condition (i.e. we finished running current test)
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if (DCacheFlushDone) begin
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// Termination condition (i.e. we finished running current test)
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if (DCacheFlushDone) begin
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integer begin_signature_addr;
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InReset = 1;
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begin_signature_addr = ProgramAddrLabelArray["begin_signature"];
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if (!begin_signature_addr)
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$display("begin_signature addr not found in %s", ProgramLabelMapFile);
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$display("begin_signature addr not found in %s", ProgramLabelMapFile);
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testadr = ($unsigned(begin_signature_addr))/(`XLEN/8);
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testadrNoBase = (begin_signature_addr - `UNCORE_RAM_BASE)/(`XLEN/8);
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#600; // give time for instructions in pipeline to finish
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if (TEST == "embench") begin
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// Writes contents of begin_signature to .sim.output file
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// this contains instret and cycles for start and end of test run, used by embench python speed script to calculate embench speed score
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// also begin_signature contains the results of the self checking mechanism, which will be read by the python script for error checking
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// this contains instret and cycles for start and end of test run, used by embench
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// python speed script to calculate embench speed score.
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// also, begin_signature contains the results of the self checking mechanism,
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// which will be read by the python script for error checking
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$display("Embench Benchmark: %s is done.", tests[test]);
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if (riscofTest) outputfile = {pathname, tests[test], "/ref/ref.sim.output"};
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else outputfile = {pathname, tests[test], ".sim.output"};
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outputFilePointer = $fopen(outputfile);
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i = 0;
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while ($unsigned(i) < $unsigned(5'd5)) begin
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$fdisplayh(outputFilePointer, DCacheFlushFSM.ShadowRAM[testadr+i]);
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i = i + 1;
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$fdisplayh(outputFilePointer, DCacheFlushFSM.ShadowRAM[testadr+i]);
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i = i + 1;
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end
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$fclose(outputFilePointer);
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$display("Embench Benchmark: created output file: %s", outputfile);
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end else if (TEST == "coverage64gc") begin
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$display("Coverage tests don't get checked");
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end else begin
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// for tests with no self checking mechanism, read .signature.output file and compare to check for errors
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// clear signature to prevent contamination from previous tests
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for(i=0; i<SIGNATURESIZE; i=i+1) begin
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// for tests with no self checking mechanism, read .signature.output file and compare to check for errors
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// clear signature to prevent contamination from previous tests
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for(i=0; i<SIGNATURESIZE; i=i+1) begin
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sig32[i] = 'bx;
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end
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if (riscofTest) signame = {pathname, tests[test], "/ref/Reference-sail_c_simulator.signature"};
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else signame = {pathname, tests[test], ".signature.output"};
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// read signature, reformat in 64 bits if necessary
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$readmemh(signame, sig32);
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i = 0;
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while (i < SIGNATURESIZE) begin
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end
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if (riscofTest) signame = {pathname, tests[test], "/ref/Reference-sail_c_simulator.signature"};
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else signame = {pathname, tests[test], ".signature.output"};
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// read signature, reformat in 64 bits if necessary
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$readmemh(signame, sig32);
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i = 0;
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while (i < SIGNATURESIZE) begin
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if (`XLEN == 32) begin
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signature[i] = sig32[i];
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i = i+1;
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signature[i] = sig32[i];
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i = i+1;
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end else begin
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signature[i/2] = {sig32[i+1], sig32[i]};
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i = i + 2;
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signature[i/2] = {sig32[i+1], sig32[i]};
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i = i + 2;
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end
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if (i >= 4 & sig32[i-4] === 'bx) begin
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if (i == 4) begin
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if (i == 4) begin
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i = SIGNATURESIZE+1; // flag empty file
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$display(" Error: empty test file");
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end else i = SIGNATURESIZE; // skip over the rest of the x's for efficiency
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end else i = SIGNATURESIZE; // skip over the rest of the x's for efficiency
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end
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end
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end
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// Check errors
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errors = (i == SIGNATURESIZE+1); // error if file is empty
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i = 0;
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/* verilator lint_off INFINITELOOP */
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while (signature[i] !== 'bx) begin
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// Check errors
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errors = (i == SIGNATURESIZE+1); // error if file is empty
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i = 0;
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/* verilator lint_off INFINITELOOP */
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while (signature[i] !== 'bx) begin
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logic [`XLEN-1:0] sig;
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if (`DTIM_SUPPORTED) sig = dut.core.lsu.dtim.dtim.ram.RAM[testadrNoBase+i];
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else if (`UNCORE_RAM_SUPPORTED) sig = dut.uncore.uncore.ram.ram.memory.RAM[testadrNoBase+i];
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//$display("signature[%h] = %h sig = %h", i, signature[i], sig);
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if (signature[i] !== sig & (signature[i] !== DCacheFlushFSM.ShadowRAM[testadr+i])) begin
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errors = errors+1;
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$display(" Error on test %s result %d: adr = %h sim (D$) %h sim (DTIM_SUPPORTED) = %h, signature = %h",
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tests[test], i, (testadr+i)*(`XLEN/8), DCacheFlushFSM.ShadowRAM[testadr+i], sig, signature[i]);
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$stop;//***debug
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errors = errors+1;
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$display(" Error on test %s result %d: adr = %h sim (D$) %h sim (DTIM_SUPPORTED) = %h, signature = %h",
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tests[test], i, (testadr+i)*(`XLEN/8), DCacheFlushFSM.ShadowRAM[testadr+i], sig, signature[i]);
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$stop; //***debug
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end
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i = i + 1;
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end
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/* verilator lint_on INFINITELOOP */
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if (errors == 0) begin
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end
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/* verilator lint_on INFINITELOOP */
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if (errors == 0) begin
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$display("%s succeeded. Brilliant!!!", tests[test]);
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end
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else begin
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end else begin
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$display("%s failed with %d errors. :(", tests[test], errors);
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totalerrors = totalerrors+1;
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end
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end
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end
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// move onto the next test, check to see if we're done
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test = test + 1;
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if (test == tests.size()) begin
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if (totalerrors == 0) $display("SUCCESS! All tests ran without failures.");
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else $display("FAIL: %d test programs had errors", totalerrors);
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$stop;
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end
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else begin
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if (totalerrors == 0) $display("SUCCESS! All tests ran without failures.");
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else $display("FAIL: %d test programs had errors", totalerrors);
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$stop;
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end else begin
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InitializingMemories = 1;
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// If there are still additional tests to run, read in information for the next test
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//pathname = tvpaths[tests[0]];
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@ -394,7 +396,7 @@ module testbench;
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else memfilename = {pathname, tests[test], ".elf.memfile"};
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//$readmemh(memfilename, dut.uncore.uncore.ram.ram.memory.RAM);
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if (`IROM_SUPPORTED) $readmemh(memfilename, dut.core.ifu.irom.irom.rom.ROM);
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else if (`UNCORE_RAM_SUPPORTED) $readmemh(memfilename, dut.uncore.uncore.ram.ram.memory.RAM);
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else if (`UNCORE_RAM_SUPPORTED) $readmemh(memfilename, dut.uncore.uncore.ram.ram.memory.RAM);
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if (`DTIM_SUPPORTED) $readmemh(memfilename, dut.core.lsu.dtim.dtim.ram.RAM);
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if (riscofTest) begin
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@ -405,22 +407,22 @@ module testbench;
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ProgramLabelMapFile = {pathname, tests[test], ".elf.objdump.lab"};
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end
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ProgramAddrLabelArray = '{ "begin_signature" : 0, "tohost" : 0 };
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if(!`FPGA) begin
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if(!`FPGA) begin
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updateProgramAddrLabelArray(ProgramAddrMapFile, ProgramLabelMapFile, ProgramAddrLabelArray);
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$display("Read memfile %s", memfilename);
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end
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end
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end
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end // if (DCacheFlushDone)
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end // if (DCacheFlushDone)
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end
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end // always @ (negedge clk)
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if(`PrintHPMCounters & `ZICOUNTERS_SUPPORTED) begin : HPMCSample
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integer HPMCindex;
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logic StartSampleFirst;
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logic StartSampleDelayed, BeginDelayed;
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logic EndSampleFirst, EndSampleDelayed;
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logic [`XLEN-1:0] InitialHPMCOUNTERH[`COUNTERS-1:0];
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integer HPMCindex;
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logic StartSampleFirst;
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logic StartSampleDelayed, BeginDelayed;
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logic EndSampleFirst, EndSampleDelayed;
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logic [`XLEN-1:0] InitialHPMCOUNTERH[`COUNTERS-1:0];
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string HPMCnames[] = '{"Mcycle",
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"------",
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@ -433,8 +435,8 @@ module testbench;
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"BP Target Wrong",
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"RAS Wrong",
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"Instr Class Wrong",
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"Load Stall",
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"Store Stall",
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"Load Stall",
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"Store Stall",
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"D Cache Access",
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"D Cache Miss",
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"D Cache Cycles",
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@ -447,56 +449,55 @@ module testbench;
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"Interrupt",
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"Exception",
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"Divide Cycles"
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};
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};
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if(TEST == "embench") begin
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// embench runs warmup then runs start_trigger
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// embench end with stop_trigger.
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assign StartSampleFirst = FunctionName.FunctionName.FunctionName == "start_trigger";
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flopr #(1) StartSampleReg(clk, reset, StartSampleFirst, StartSampleDelayed);
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assign StartSample = StartSampleFirst & ~ StartSampleDelayed;
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if(TEST == "embench") begin
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// embench runs warmup then runs start_trigger
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// embench end with stop_trigger.
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assign StartSampleFirst = FunctionName.FunctionName.FunctionName == "start_trigger";
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flopr #(1) StartSampleReg(clk, reset, StartSampleFirst, StartSampleDelayed);
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assign StartSample = StartSampleFirst & ~ StartSampleDelayed;
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assign EndSampleFirst = FunctionName.FunctionName.FunctionName == "stop_trigger";
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flopr #(1) EndSampleReg(clk, reset, EndSampleFirst, EndSampleDelayed);
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assign EndSample = EndSampleFirst & ~ EndSampleDelayed;
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assign EndSampleFirst = FunctionName.FunctionName.FunctionName == "stop_trigger";
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flopr #(1) EndSampleReg(clk, reset, EndSampleFirst, EndSampleDelayed);
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assign EndSample = EndSampleFirst & ~ EndSampleDelayed;
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end else if(TEST == "coremark") begin
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// embench runs warmup then runs start_trigger
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// embench end with stop_trigger.
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assign StartSampleFirst = FunctionName.FunctionName.FunctionName == "start_time";
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flopr #(1) StartSampleReg(clk, reset, StartSampleFirst, StartSampleDelayed);
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assign StartSample = StartSampleFirst & ~ StartSampleDelayed;
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end else if(TEST == "coremark") begin
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// embench runs warmup then runs start_trigger
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// embench end with stop_trigger.
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assign StartSampleFirst = FunctionName.FunctionName.FunctionName == "start_time";
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flopr #(1) StartSampleReg(clk, reset, StartSampleFirst, StartSampleDelayed);
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assign StartSample = StartSampleFirst & ~ StartSampleDelayed;
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assign EndSampleFirst = FunctionName.FunctionName.FunctionName == "stop_time";
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flopr #(1) EndSampleReg(clk, reset, EndSampleFirst, EndSampleDelayed);
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assign EndSample = EndSampleFirst & ~ EndSampleDelayed;
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assign EndSampleFirst = FunctionName.FunctionName.FunctionName == "stop_time";
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flopr #(1) EndSampleReg(clk, reset, EndSampleFirst, EndSampleDelayed);
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assign EndSample = EndSampleFirst & ~ EndSampleDelayed;
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end else begin
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// default start condiction is reset
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// default end condiction is end of test (DCacheFlushDone)
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assign StartSampleFirst = InReset;
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flopr #(1) StartSampleReg(clk, reset, StartSampleFirst, StartSampleDelayed);
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assign StartSample = StartSampleFirst & ~ StartSampleDelayed;
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assign EndSample = DCacheFlushStart & ~DCacheFlushDone;
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end else begin
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// default start condiction is reset
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// default end condiction is end of test (DCacheFlushDone)
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assign StartSampleFirst = InReset;
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flopr #(1) StartSampleReg(clk, reset, StartSampleFirst, StartSampleDelayed);
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assign StartSample = StartSampleFirst & ~ StartSampleDelayed;
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assign EndSample = DCacheFlushStart & ~DCacheFlushDone;
|
||||
|
||||
flop #(1) BeginReg(clk, StartSampleFirst, BeginDelayed);
|
||||
assign Begin = StartSampleFirst & ~BeginDelayed;
|
||||
flop #(1) BeginReg(clk, StartSampleFirst, BeginDelayed);
|
||||
assign BeginSample = StartSampleFirst & ~BeginDelayed;
|
||||
|
||||
end
|
||||
|
||||
end
|
||||
always @(negedge clk) begin
|
||||
if(StartSample) begin
|
||||
for(HPMCindex = 0; HPMCindex < 32; HPMCindex += 1) begin
|
||||
InitialHPMCOUNTERH[HPMCindex] <= dut.core.priv.priv.csr.counters.counters.HPMCOUNTER_REGW[HPMCindex];
|
||||
end
|
||||
end
|
||||
if(StartSample) begin
|
||||
for(HPMCindex = 0; HPMCindex < 32; HPMCindex += 1) begin
|
||||
InitialHPMCOUNTERH[HPMCindex] <= dut.core.priv.priv.csr.counters.counters.HPMCOUNTER_REGW[HPMCindex];
|
||||
end
|
||||
end
|
||||
if(EndSample) begin
|
||||
for(HPMCindex = 0; HPMCindex < HPMCnames.size(); HPMCindex += 1) begin
|
||||
// unlikely to have more than 10M in any counter.
|
||||
$display("Cnt[%2d] = %7d %s", HPMCindex, dut.core.priv.priv.csr.counters.counters.HPMCOUNTER_REGW[HPMCindex] - InitialHPMCOUNTERH[HPMCindex], HPMCnames[HPMCindex]);
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
@ -535,24 +536,24 @@ module testbench;
|
||||
if (`BPRED_SUPPORTED) begin
|
||||
integer adrindex;
|
||||
|
||||
always @(*) begin
|
||||
if(reset) begin
|
||||
for(adrindex = 0; adrindex < 2**`BTB_SIZE; adrindex++) begin
|
||||
force dut.core.ifu.bpred.bpred.TargetPredictor.memory.mem[adrindex] = 0;
|
||||
end
|
||||
for(adrindex = 0; adrindex < 2**`BPRED_SIZE; adrindex++) begin
|
||||
force dut.core.ifu.bpred.bpred.Predictor.DirPredictor.PHT.mem[adrindex] = 0;
|
||||
end
|
||||
#1;
|
||||
for(adrindex = 0; adrindex < 2**`BTB_SIZE; adrindex++) begin
|
||||
release dut.core.ifu.bpred.bpred.TargetPredictor.memory.mem[adrindex];
|
||||
end
|
||||
for(adrindex = 0; adrindex < 2**`BPRED_SIZE; adrindex++) begin
|
||||
release dut.core.ifu.bpred.bpred.Predictor.DirPredictor.PHT.mem[adrindex];
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
always @(*) begin
|
||||
if(reset) begin
|
||||
for(adrindex = 0; adrindex < 2**`BTB_SIZE; adrindex++) begin
|
||||
force dut.core.ifu.bpred.bpred.TargetPredictor.memory.mem[adrindex] = 0;
|
||||
end
|
||||
for(adrindex = 0; adrindex < 2**`BPRED_SIZE; adrindex++) begin
|
||||
force dut.core.ifu.bpred.bpred.Predictor.DirPredictor.PHT.mem[adrindex] = 0;
|
||||
end
|
||||
#1;
|
||||
for(adrindex = 0; adrindex < 2**`BTB_SIZE; adrindex++) begin
|
||||
release dut.core.ifu.bpred.bpred.TargetPredictor.memory.mem[adrindex];
|
||||
end
|
||||
for(adrindex = 0; adrindex < 2**`BPRED_SIZE; adrindex++) begin
|
||||
release dut.core.ifu.bpred.bpred.Predictor.DirPredictor.PHT.mem[adrindex];
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
if (`ICACHE_SUPPORTED && `I_CACHE_ADDR_LOGGER) begin : ICacheLogger
|
||||
@ -565,28 +566,28 @@ end
|
||||
dut.core.ifu.immu.immu.pmachecker.Cacheable &
|
||||
~dut.core.ifu.bus.icache.icache.cachefsm.FlushStage &
|
||||
~reset;
|
||||
flop #(1) ResetDReg(clk, reset, resetD);
|
||||
assign resetEdge = ~reset & resetD;
|
||||
flop #(1) ResetDReg(clk, reset, resetD);
|
||||
assign resetEdge = ~reset & resetD;
|
||||
|
||||
flop #(1) InvalReg(clk, dut.core.ifu.InvalidateICacheM, InvalDelayed);
|
||||
assign InvalEdge = dut.core.ifu.InvalidateICacheM & ~InvalDelayed;
|
||||
assign InvalEdge = dut.core.ifu.InvalidateICacheM & ~InvalDelayed;
|
||||
|
||||
initial begin
|
||||
LogFile = $psprintf("ICache.log");
|
||||
LogFile = $psprintf("ICache.log");
|
||||
file = $fopen(LogFile, "w");
|
||||
$fwrite(file, "BEGIN %s\n", memfilename);
|
||||
end
|
||||
$fwrite(file, "BEGIN %s\n", memfilename);
|
||||
end
|
||||
string AccessTypeString, HitMissString;
|
||||
assign HitMissString = dut.core.ifu.bus.icache.icache.CacheHit ? "H" :
|
||||
dut.core.ifu.bus.icache.icache.vict.cacheLRU.AllValid ? "E" : "M";
|
||||
always @(posedge clk) begin
|
||||
if(resetEdge) $fwrite(file, "TRAIN\n");
|
||||
if(Begin) $fwrite(file, "BEGIN %s\n", memfilename);
|
||||
if(Enable) begin // only log i cache reads
|
||||
$fwrite(file, "%h R %s\n", dut.core.ifu.PCPF, HitMissString);
|
||||
end
|
||||
if(resetEdge) $fwrite(file, "TRAIN\n");
|
||||
if(BeginSample) $fwrite(file, "BEGIN %s\n", memfilename);
|
||||
if(Enable) begin // only log i cache reads
|
||||
$fwrite(file, "%h R %s\n", dut.core.ifu.PCPF, HitMissString);
|
||||
end
|
||||
if(InvalEdge) $fwrite(file, "0 I X\n");
|
||||
if(EndSample) $fwrite(file, "END %s\n", memfilename);
|
||||
if(EndSample) $fwrite(file, "END %s\n", memfilename);
|
||||
end
|
||||
end
|
||||
|
||||
@ -615,18 +616,18 @@ end
|
||||
(AccessTypeString != "NULL");
|
||||
|
||||
initial begin
|
||||
LogFile = $psprintf("DCache.log");
|
||||
LogFile = $psprintf("DCache.log");
|
||||
file = $fopen(LogFile, "w");
|
||||
$fwrite(file, "BEGIN %s\n", memfilename);
|
||||
end
|
||||
$fwrite(file, "BEGIN %s\n", memfilename);
|
||||
end
|
||||
always @(posedge clk) begin
|
||||
if(resetEdge) $fwrite(file, "TRAIN\n");
|
||||
if(Begin) $fwrite(file, "BEGIN %s\n", memfilename);
|
||||
if(Enabled) begin
|
||||
$fwrite(file, "%h %s %s\n", dut.core.lsu.PAdrM, AccessTypeString, HitMissString);
|
||||
end
|
||||
if(dut.core.lsu.bus.dcache.dcache.cachefsm.FlushFlag) $fwrite(file, "0 F X\n");
|
||||
if(EndSample) $fwrite(file, "END %s\n", memfilename);
|
||||
if(resetEdge) $fwrite(file, "TRAIN\n");
|
||||
if(BeginSample) $fwrite(file, "BEGIN %s\n", memfilename);
|
||||
if(Enabled) begin
|
||||
$fwrite(file, "%h %s %s\n", dut.core.lsu.PAdrM, AccessTypeString, HitMissString);
|
||||
end
|
||||
if(dut.core.lsu.bus.dcache.dcache.cachefsm.FlushFlag) $fwrite(file, "0 F X\n");
|
||||
if(EndSample) $fwrite(file, "END %s\n", memfilename);
|
||||
end
|
||||
end
|
||||
|
||||
@ -634,45 +635,45 @@ end
|
||||
if (`BPRED_LOGGER) begin
|
||||
string direction;
|
||||
int file;
|
||||
logic PCSrcM;
|
||||
string LogFile;
|
||||
logic resetD, resetEdge;
|
||||
flopenrc #(1) PCSrcMReg(clk, reset, dut.core.FlushM, ~dut.core.StallM, dut.core.ifu.bpred.bpred.Predictor.DirPredictor.PCSrcE, PCSrcM);
|
||||
flop #(1) ResetDReg(clk, reset, resetD);
|
||||
assign resetEdge = ~reset & resetD;
|
||||
logic PCSrcM;
|
||||
string LogFile;
|
||||
logic resetD, resetEdge;
|
||||
flopenrc #(1) PCSrcMReg(clk, reset, dut.core.FlushM, ~dut.core.StallM, dut.core.ifu.bpred.bpred.Predictor.DirPredictor.PCSrcE, PCSrcM);
|
||||
flop #(1) ResetDReg(clk, reset, resetD);
|
||||
assign resetEdge = ~reset & resetD;
|
||||
initial begin
|
||||
LogFile = $psprintf("branch_%s%0d.log", `BPRED_TYPE, `BPRED_SIZE);
|
||||
LogFile = $psprintf("branch_%s%0d.log", `BPRED_TYPE, `BPRED_SIZE);
|
||||
file = $fopen(LogFile, "w");
|
||||
end
|
||||
end
|
||||
always @(posedge clk) begin
|
||||
if(resetEdge) $fwrite(file, "TRAIN\n");
|
||||
if(StartSample) $fwrite(file, "BEGIN %s\n", memfilename);
|
||||
if(dut.core.ifu.InstrClassM[0] & ~dut.core.StallW & ~dut.core.FlushW & dut.core.InstrValidM) begin
|
||||
direction = PCSrcM ? "t" : "n";
|
||||
$fwrite(file, "%h %s\n", dut.core.PCM, direction);
|
||||
end
|
||||
if(EndSample) $fwrite(file, "END %s\n", memfilename);
|
||||
end
|
||||
if(resetEdge) $fwrite(file, "TRAIN\n");
|
||||
if(StartSample) $fwrite(file, "BEGIN %s\n", memfilename);
|
||||
if(dut.core.ifu.InstrClassM[0] & ~dut.core.StallW & ~dut.core.FlushW & dut.core.InstrValidM) begin
|
||||
direction = PCSrcM ? "t" : "n";
|
||||
$fwrite(file, "%h %s\n", dut.core.PCM, direction);
|
||||
end
|
||||
if(EndSample) $fwrite(file, "END %s\n", memfilename);
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// check for hange up.
|
||||
// check for hang up.
|
||||
logic [`XLEN-1:0] OldPCW;
|
||||
integer WatchDogTimerCount;
|
||||
localparam WatchDogTimerThreshold = 1000000;
|
||||
logic WatchDogTimeOut;
|
||||
integer WatchDogTimerCount;
|
||||
localparam WatchDogTimerThreshold = 1000000;
|
||||
logic WatchDogTimeOut;
|
||||
always_ff @(posedge clk) begin
|
||||
OldPCW <= PCW;
|
||||
if(OldPCW == PCW) WatchDogTimerCount = WatchDogTimerCount + 1'b1;
|
||||
else WatchDogTimerCount = '0;
|
||||
OldPCW <= PCW;
|
||||
if(OldPCW == PCW) WatchDogTimerCount = WatchDogTimerCount + 1'b1;
|
||||
else WatchDogTimerCount = '0;
|
||||
end
|
||||
|
||||
always_comb begin
|
||||
WatchDogTimeOut = WatchDogTimerCount >= WatchDogTimerThreshold;
|
||||
if(WatchDogTimeOut) begin
|
||||
$display("FAILURE: Watch Dog Time Out triggered. PCW stuck at %x for more than %d cycles", PCW, WatchDogTimerCount);
|
||||
$stop;
|
||||
end
|
||||
WatchDogTimeOut = WatchDogTimerCount >= WatchDogTimerThreshold;
|
||||
if(WatchDogTimeOut) begin
|
||||
$display("FAILURE: Watch Dog Time Out triggered. PCW stuck at %x for more than %d cycles", PCW, WatchDogTimerCount);
|
||||
$stop;
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
@ -690,34 +691,34 @@ module DCacheFlushFSM
|
||||
|
||||
logic [`XLEN-1:0] ShadowRAM[`UNCORE_RAM_BASE>>(1+`XLEN/32):(`UNCORE_RAM_RANGE+`UNCORE_RAM_BASE)>>1+(`XLEN/32)];
|
||||
|
||||
if(`DCACHE_SUPPORTED) begin
|
||||
localparam numlines = testbench.dut.core.lsu.bus.dcache.dcache.NUMLINES;
|
||||
localparam numways = testbench.dut.core.lsu.bus.dcache.dcache.NUMWAYS;
|
||||
localparam linebytelen = testbench.dut.core.lsu.bus.dcache.dcache.LINEBYTELEN;
|
||||
localparam linelen = testbench.dut.core.lsu.bus.dcache.dcache.LINELEN;
|
||||
localparam sramlen = testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[0].SRAMLEN;
|
||||
localparam cachesramwords = testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[0].NUMSRAM;
|
||||
localparam numwords = sramlen/`XLEN;
|
||||
localparam lognumlines = $clog2(numlines);
|
||||
localparam loglinebytelen = $clog2(linebytelen);
|
||||
localparam lognumways = $clog2(numways);
|
||||
localparam tagstart = lognumlines + loglinebytelen;
|
||||
if(`DCACHE_SUPPORTED) begin
|
||||
localparam numlines = testbench.dut.core.lsu.bus.dcache.dcache.NUMLINES;
|
||||
localparam numways = testbench.dut.core.lsu.bus.dcache.dcache.NUMWAYS;
|
||||
localparam linebytelen = testbench.dut.core.lsu.bus.dcache.dcache.LINEBYTELEN;
|
||||
localparam linelen = testbench.dut.core.lsu.bus.dcache.dcache.LINELEN;
|
||||
localparam sramlen = testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[0].SRAMLEN;
|
||||
localparam cachesramwords = testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[0].NUMSRAM;
|
||||
localparam numwords = sramlen/`XLEN;
|
||||
localparam lognumlines = $clog2(numlines);
|
||||
localparam loglinebytelen = $clog2(linebytelen);
|
||||
localparam lognumways = $clog2(numways);
|
||||
localparam tagstart = lognumlines + loglinebytelen;
|
||||
|
||||
|
||||
|
||||
genvar index, way, cacheWord;
|
||||
logic [sramlen-1:0] CacheData [numways-1:0] [numlines-1:0] [cachesramwords-1:0];
|
||||
logic [sramlen-1:0] cacheline;
|
||||
logic [`XLEN-1:0] CacheTag [numways-1:0] [numlines-1:0] [cachesramwords-1:0];
|
||||
logic CacheValid [numways-1:0] [numlines-1:0] [cachesramwords-1:0];
|
||||
logic CacheDirty [numways-1:0] [numlines-1:0] [cachesramwords-1:0];
|
||||
logic [`PA_BITS-1:0] CacheAdr [numways-1:0] [numlines-1:0] [cachesramwords-1:0];
|
||||
genvar index, way, cacheWord;
|
||||
logic [sramlen-1:0] CacheData [numways-1:0] [numlines-1:0] [cachesramwords-1:0];
|
||||
logic [sramlen-1:0] cacheline;
|
||||
logic [`XLEN-1:0] CacheTag [numways-1:0] [numlines-1:0] [cachesramwords-1:0];
|
||||
logic CacheValid [numways-1:0] [numlines-1:0] [cachesramwords-1:0];
|
||||
logic CacheDirty [numways-1:0] [numlines-1:0] [cachesramwords-1:0];
|
||||
logic [`PA_BITS-1:0] CacheAdr [numways-1:0] [numlines-1:0] [cachesramwords-1:0];
|
||||
for(index = 0; index < numlines; index++) begin
|
||||
for(way = 0; way < numways; way++) begin
|
||||
for(cacheWord = 0; cacheWord < cachesramwords; cacheWord++) begin
|
||||
copyShadow #(.tagstart(tagstart),
|
||||
.loglinebytelen(loglinebytelen), .sramlen(sramlen))
|
||||
copyShadow(.clk,
|
||||
for(way = 0; way < numways; way++) begin
|
||||
for(cacheWord = 0; cacheWord < cachesramwords; cacheWord++) begin
|
||||
copyShadow #(.tagstart(tagstart),
|
||||
.loglinebytelen(loglinebytelen), .sramlen(sramlen))
|
||||
copyShadow(.clk,
|
||||
.start,
|
||||
.tag(testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[way].CacheTagMem.RAM[index][`PA_BITS-1-tagstart:0]),
|
||||
.valid(testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[way].ValidBits[index]),
|
||||
@ -766,18 +767,18 @@ endmodule
|
||||
|
||||
module copyShadow
|
||||
#(parameter tagstart, loglinebytelen, sramlen)
|
||||
(input logic clk,
|
||||
input logic start,
|
||||
input logic [`PA_BITS-1:tagstart] tag,
|
||||
input logic valid, dirty,
|
||||
input logic [sramlen-1:0] data,
|
||||
input logic [32-1:0] index,
|
||||
input logic [32-1:0] cacheWord,
|
||||
output logic [sramlen-1:0] CacheData,
|
||||
output logic [`PA_BITS-1:0] CacheAdr,
|
||||
output logic [`XLEN-1:0] CacheTag,
|
||||
output logic CacheValid,
|
||||
output logic CacheDirty);
|
||||
(input logic clk,
|
||||
input logic start,
|
||||
input logic [`PA_BITS-1:tagstart] tag,
|
||||
input logic valid, dirty,
|
||||
input logic [sramlen-1:0] data,
|
||||
input logic [32-1:0] index,
|
||||
input logic [32-1:0] cacheWord,
|
||||
output logic [sramlen-1:0] CacheData,
|
||||
output logic [`PA_BITS-1:0] CacheAdr,
|
||||
output logic [`XLEN-1:0] CacheTag,
|
||||
output logic CacheValid,
|
||||
output logic CacheDirty);
|
||||
|
||||
|
||||
always_ff @(posedge clk) begin
|
||||
@ -806,8 +807,7 @@ task automatic updateProgramAddrLabelArray;
|
||||
integer returncode;
|
||||
returncode = $fscanf(ProgramLabelMapFP, "%s\n", label);
|
||||
returncode = $fscanf(ProgramAddrMapFP, "%s\n", adrstr);
|
||||
if (ProgramAddrLabelArray.exists(label))
|
||||
ProgramAddrLabelArray[label] = adrstr.atohex();
|
||||
if (ProgramAddrLabelArray.exists(label)) ProgramAddrLabelArray[label] = adrstr.atohex();
|
||||
end
|
||||
end
|
||||
$fclose(ProgramLabelMapFP);
|
||||
|
||||
Loading…
Reference in New Issue
Block a user