forked from Github_Repos/cvw
fdivsqrt post processing major simplification
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@ -101,15 +101,16 @@ module fdivsqrtpostproc(
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if (`IDIV_ON_FPU) begin // Int supported
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logic [`DIVBLEN:0] NormShiftM;
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logic [`DIVb+3:0] IntQuotM, NormRemM, NormRemDM, NormQuotM;
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logic [`DIVb+3:0] UnsignedQuotM, NormRemM, NormRemDM, NormQuotM;
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assign W = $signed(Sum) >>> `LOGR;
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assign DM = {4'b0001, D};
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assign UnsignedQuotM = {3'b000, PreQmM};
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// Integer remainder: sticky and sign correction muxes
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mux2 #(`DIVb+4) normremdmux(W, W+DM, NegStickyM, NormRemDM);
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mux2 #(`DIVb+4) normremsmux(NormRemDM, -NormRemDM, AsM, NormRemM);
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mux2 #(`DIVb+4) quotresmux({3'b000, PreQmM}, {3'b111, -PreQmM}, NegQuotM, NormQuotM);
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mux2 #(`DIVb+4) quotresmux(UnsignedQuotM, -UnsignedQuotM, NegQuotM, NormQuotM);
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// special case logic
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always_comb
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@ -120,17 +121,12 @@ module fdivsqrtpostproc(
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if (RemOpM) SpecialFPIntDivResultM = AM;
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else SpecialFPIntDivResultM = '0;
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end else begin
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logic [`DIVb+3:0] PreIntQuotM;
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PreIntQuotM = {3'b000, PreQmM};
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// flip sign if necessary
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if (NegQuotM) IntQuotM = -PreIntQuotM;
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else IntQuotM = PreIntQuotM;
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if (RemOpM) begin
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NormShiftM = ALTBM ? 0 : (mM + (`DIVBLEN+1)'(`DIVa)); // no postshift if forwarding input A to remainder
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PreResultM = NormRemM;
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end else begin
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NormShiftM = ((`DIVBLEN+1)'(`DIVb) - (nM * (`DIVBLEN+1)'(`LOGR)));
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PreResultM = IntQuotM;
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PreResultM = NormQuotM;
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end
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PreFPIntDivResultM = $signed(PreResultM >>> NormShiftM);
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SpecialFPIntDivResultM = PreFPIntDivResultM[`XLEN-1:0];
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