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Moving postprocessing into postproc block

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This commit is contained in:
David Harris 2022-09-07 06:42:37 -07:00
parent f40c6b0ec4
commit 825d3169d9
3 changed files with 40 additions and 49 deletions
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22
pipelined/src/fpu/fdivsqrt.sv
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@ -66,12 +66,20 @@ module fdivsqrt(
logic [`DURLEN-1:0] Dur;
logic NegSticky;
logic [`DIVCOPIES-1:0] qn;
logic WZero;
fdivsqrtpreproc fdivsqrtpreproc(.clk, .DivStart(DivStartE), .Xm(XmE), .QeM, .Xe(XeE), .Fmt(FmtE), .Ye(YeE), .Sqrt(SqrtE), .Dur, .Ym(YmE), .XZero(XZeroE), .X, .Dpreproc);
fdivsqrtfsm fdivsqrtfsm(.reset, .qn, .LastSM, .LastC, .FirstSM, .FirstC, .D, .XsE, .SqrtE, .SqrtM, .NextWSN, .NextWCN, .WS, .WC, .Dur, .DivBusy, .clk, .DivStart(DivStartE),.StallE, .StallM, .DivDone, .XZeroE, .YZeroE, .DivSE(DivSM), .XNaNE, .YNaNE,
.StickyWSA, .XInfE, .YInfE, .NegSticky(NegSticky), .EarlyTermShiftE(EarlyTermShiftM));
fdivsqrtiter fdivsqrtiter(.clk, .qn, .D, .LastSM, .LastC, .FirstSM, .FirstC, .SqrtE, .SqrtM, .X,.Dpreproc, .NegSticky, .FirstWS(WS), .FirstWC(WC), .NextWSN, .NextWCN, .DivStart(DivStartE), .Xe(XeE), .Ye(YeE), .XZeroE, .YZeroE,
.StickyWSA, .DivBusy, .Qm(QmM));
// fdivsqrtpostproc fdivsqrtpostproc();
fdivsqrtpreproc fdivsqrtpreproc(
.clk, .DivStart(DivStartE), .Xm(XmE), .QeM, .Xe(XeE), .Fmt(FmtE), .Ye(YeE),
.Sqrt(SqrtE), .Dur, .Ym(YmE), .XZero(XZeroE), .X, .Dpreproc);
fdivsqrtfsm fdivsqrtfsm(
.reset, .qn, .LastSM, .LastC, .FirstSM, .FirstC, .D, .XsE, .SqrtE, .SqrtM, .NextWSN, .NextWCN,
.WS, .WC, .Dur, .DivBusy, .clk, .DivStart(DivStartE),.StallE, .StallM, .DivDone, .XZeroE, .YZeroE,
.XNaNE, .YNaNE,
.StickyWSA, .XInfE, .YInfE, .EarlyTermShiftE(EarlyTermShiftM), .WZero);
fdivsqrtiter fdivsqrtiter(
.clk, .qn, .D, .LastSM, .LastC, .FirstSM, .FirstC, .SqrtE, .SqrtM,
.X,.Dpreproc, .NegSticky, .FirstWS(WS), .FirstWC(WC), .NextWSN, .NextWCN,
.DivStart(DivStartE), .Xe(XeE), .Ye(YeE), .XZeroE, .YZeroE,
.StickyWSA, .DivBusy, .Qm(QmM));
fdivsqrtpostproc fdivsqrtpostproc(.WS, .WC, .D, .FirstSM, .FirstC, .qn, .SqrtM, .WZero, .DivSM, .NegSticky);
endmodule

24
pipelined/src/fpu/fdivsqrtfsm.sv
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@ -51,10 +51,11 @@ module fdivsqrtfsm(
input logic [`DIVb-1:0] LastC,
input logic [`DIVb-1:0] FirstC,
input logic [`DIVCOPIES-1:0] qn,
input logic WZero,
output logic [`DURLEN-1:0] EarlyTermShiftE,
output logic DivSE,
// output logic DivSE,
output logic DivDone,
output logic NegSticky,
// output logic NegSticky,
output logic DivBusy
);
@ -63,25 +64,6 @@ module fdivsqrtfsm(
logic [`DURLEN-1:0] step;
logic SpecialCase;
logic WZero;
logic [`DIVb+3:0] W;
// check for early termination on an exact result. If the result is not exact, the sticky should be set
if (`RADIX == 2) begin
logic [`DIVb+3:0] FZero;
logic [`DIVb+2:0] FirstK;
assign FirstK = ({3'b111, FirstC<<1} & ~({3'b111, FirstC<<1} << 1));
assign FZero = SqrtM ? {FirstSM[`DIVb], FirstSM, 2'b0} | {FirstK,1'b0} : {3'b1,D,{`DIVb-`DIVN+2{1'b0}}};
assign WZero = ((WS^WC)=={WS[`DIVb+2:0]|WC[`DIVb+2:0], 1'b0})|(((WS+WC+FZero)==0)&qn[`DIVCOPIES-1]);
end else begin
assign WZero = ((WS^WC)=={WS[`DIVb+2:0]|WC[`DIVb+2:0], 1'b0});
end
assign DivSE = ~WZero;
// Determine if sticky bit is negative
assign W = WC+WS;
assign NegSticky = W[`DIVb+3];
assign EarlyTermShiftE = step;

43
pipelined/src/fpu/fdivsqrtpostproc.sv
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@ -31,32 +31,33 @@
`include "wally-config.vh"
module fdivsqrtpostproc(
input logic clk,
input logic reset,
input logic DivStart,
input logic [`DIVb+3:0] NextWSN, NextWCN, WS, WC,
/* input logic XInfE, YInfE,
input logic XZeroE, YZeroE,
input logic XNaNE, YNaNE,
input logic XsE,
input logic SqrtE,
input logic SqrtM,
input logic StallE,
input logic StallM,*/
input logic [`DIVb+3:0] WS, WC,
input logic [`DIVN-2:0] D, // U0.N-1
input logic [`DIVb+3:0] StickyWSA,
input logic [`DURLEN-1:0] Dur,
input logic [`DIVb:0] LastSM,
input logic [`DIVb:0] FirstSM,
input logic [`DIVb-1:0] LastC,
input logic [`DIVb-1:0] FirstC,
input logic [`DIVCOPIES-1:0] qn,
// output logic [`DURLEN-1:0] EarlyTermShiftE,
output logic DivSE,
// output logic DivDone,
output logic NegSticky,
output logic DivBusy
input logic SqrtM,
output logic WZero,
output logic DivSM,
output logic NegSticky
);
logic [`DIVb+3:0] W;
// check for early termination on an exact result. If the result is not exact, the sticky should be set
if (`RADIX == 2) begin
logic [`DIVb+3:0] FZero;
logic [`DIVb+2:0] FirstK;
assign FirstK = ({3'b111, FirstC<<1} & ~({3'b111, FirstC<<1} << 1));
assign FZero = SqrtM ? {FirstSM[`DIVb], FirstSM, 2'b0} | {FirstK,1'b0} : {3'b1,D,{`DIVb-`DIVN+2{1'b0}}};
assign WZero = ((WS^WC)=={WS[`DIVb+2:0]|WC[`DIVb+2:0], 1'b0})|(((WS+WC+FZero)==0)&qn[`DIVCOPIES-1]);
end else begin
assign WZero = ((WS^WC)=={WS[`DIVb+2:0]|WC[`DIVb+2:0], 1'b0});
end
assign DivSM = ~WZero;
// Determine if sticky bit is negative
assign W = WC+WS;
assign NegSticky = W[`DIVb+3];
endmodule