forked from Github_Repos/cvw
Merge branch 'bit-manip' of github.com:kipmacsaigoren/cvw into bit-manip
This commit is contained in:
Kip Macsai-Goren
commit
9b4b0c7901
@ -58,15 +58,18 @@ module alu #(parameter WIDTH=32) (
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logic [WIDTH-1:0] rotA; // XLEN bit input source to shifter
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logic [1:0] shASelect; // select signal for shifter source generation mux
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assign shASelect = {W64,SubArith};
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// Extract control signals from ALUControl.
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assign {W64, SubArith, ALUOp} = ALUControl;
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// Pack control signals into shifter select
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assign shASelect = {W64,SubArith};
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if (`ZBS_SUPPORTED) begin: zbsdec
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decoder #($clog2(WIDTH)) maskgen (B[$clog2(WIDTH)-1:0], MaskB);
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assign CondMaskB = (BSelect[0]) ? MaskB : B;
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end else assign CondMaskB = B;
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// Sign/Zero extend mux
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if (WIDTH == 64) begin // rv64 must handle word s/z extensions
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always_comb
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@ -99,9 +102,6 @@ module alu #(parameter WIDTH=32) (
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assign Rotate = BSelect[2] & (ALUSelect == 3'b001); //NOTE: Do we want to move this logic into the Decode Stage?
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end else assign Rotate = 1'b0;
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// Extract control signals from ALUControl.
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assign {W64, SubArith, ALUOp} = ALUControl;
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// Addition
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assign CondInvB = SubArith ? ~CondMaskB : CondMaskB;
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assign {Carry, Sum} = CondShiftA + CondInvB + {{(WIDTH-1){1'b0}}, SubArith};
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@ -35,12 +35,14 @@ module bmuctrl(
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// Decode stage control signals
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input logic StallD, FlushD, // Stall, flush Decode stage
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input logic [31:0] InstrD, // Instruction in Decode stage
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output logic [2:0] ALUSelectD, // ALU Mux select signal
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output logic [2:0] ALUSelectD, // ALU Mux select signal in Decode Stage
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output logic [3:0] BSelectD, // Indicates if ZBA_ZBB_ZBC_ZBS instruction in one-hot encoding in Decode stage
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output logic [2:0] ZBBSelectD, // ZBB mux select signal in Decode stage NOTE: do we need this in decode?
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output logic BRegWriteD, // Indicates if it is a R type B instruction
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output logic BW64D, // Indiciates if it is a W type B instruction
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output logic BALUOpD, // Indicates if it is an ALU B instruction
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output logic BRegWriteD, // Indicates if it is a R type B instruction in Decode Stage
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output logic BW64D, // Indiciates if it is a W type B instruction in Decode Stage
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output logic BALUOpD, // Indicates if it is an ALU B instruction in Decode Stage
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output logic BSubArithD, // TRUE if ext, clr, andn, orn, xnor instruction in Decode Stage
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output logic IllegalBitmanipInstrD, // Indicates if it is unrecognized B instruction in Decode Stage
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// Execute stage control signals
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input logic StallE, FlushE, // Stall, flush Execute stage
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output logic [2:0] ALUSelectE,
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@ -54,7 +56,7 @@ module bmuctrl(
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logic [6:0] Funct7D; // Funct7 field in Decode stage
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logic [4:0] Rs2D; // Rs2 source register in Decode stage
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`define BMUCTRLW 13
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`define BMUCTRLW 15
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logic [`BMUCTRLW-1:0] BMUControlsD; // Main B Instructions Decoder control signals
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@ -68,94 +70,93 @@ module bmuctrl(
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// Main Instruction Decoder
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always_comb
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casez({OpD, Funct7D, Funct3D})
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// ALUSelect_BSelect_ZBBSelect_BRegWrite_BW64_BALUOp
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// ALUSelect_BSelect_ZBBSelect_BRegWrite_BW64_BALUOp_BSubArithD_IllegalBitmanipInstrD
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// ZBS
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17'b0010011_0100100_001: BMUControlsD = `BMUCTRLW'b111_0001_000_1_0_1; // bclri
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17'b0010011_0100100_001: BMUControlsD = `BMUCTRLW'b111_0001_000_1_0_1_1_0; // bclri
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17'b0010011_0100101_001: if (`XLEN == 64)
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BMUControlsD = `BMUCTRLW'b111_0001_000_1_0_1; // bclri (rv64)
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BMUControlsD = `BMUCTRLW'b111_0001_000_1_0_1_1_0; // bclri (rv64)
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else
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BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0; // illegal instruction
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17'b0010011_0100100_101: BMUControlsD = `BMUCTRLW'b101_0001_000_1_0_1; // bexti
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BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_0_1; // illegal instruction
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17'b0010011_0100100_101: BMUControlsD = `BMUCTRLW'b101_0001_000_1_0_1_1_0; // bexti
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17'b0010011_0100101_101: if (`XLEN == 64)
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BMUControlsD = `BMUCTRLW'b101_0001_000_1_0_1; // bexti (rv64)
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BMUControlsD = `BMUCTRLW'b101_0001_000_1_0_1_1_0; // bexti (rv64)
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else
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BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0; // illegal instruction
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17'b0010011_0110100_001: BMUControlsD = `BMUCTRLW'b100_0001_000_1_0_1; // binvi
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BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_0_1; // illegal instruction
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17'b0010011_0110100_001: BMUControlsD = `BMUCTRLW'b100_0001_000_1_0_1_0_0; // binvi
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17'b0010011_0110101_001: if (`XLEN == 64)
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BMUControlsD = `BMUCTRLW'b100_0001_000_1_0_1; // binvi (rv64)
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BMUControlsD = `BMUCTRLW'b100_0001_000_1_0_1_0_0; // binvi (rv64)
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else
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BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0; // illegal instruction
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17'b0010011_0010100_001: BMUControlsD = `BMUCTRLW'b110_0001_000_1_0_1; // bseti
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BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_0_1; // illegal instruction
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17'b0010011_0010100_001: BMUControlsD = `BMUCTRLW'b110_0001_000_1_0_1_0_0; // bseti
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17'b0010011_0010101_001: if (`XLEN == 64)
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BMUControlsD = `BMUCTRLW'b110_0001_000_1_0_1; // bseti (rv64)
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BMUControlsD = `BMUCTRLW'b110_0001_000_1_0_1_0_0; // bseti (rv64)
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else
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BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0; // illegal instruction
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17'b0110011_0100100_001: BMUControlsD = `BMUCTRLW'b111_0001_000_1_0_1; // bclr
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17'b0110011_0100100_101: BMUControlsD = `BMUCTRLW'b101_0001_000_1_0_1; // bext
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17'b0110011_0110100_001: BMUControlsD = `BMUCTRLW'b100_0001_000_1_0_1; // binv
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17'b0110011_0010100_001: BMUControlsD = `BMUCTRLW'b110_0001_000_1_0_1; // bset
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17'b0?1?011_0?0000?_?01: BMUControlsD = `BMUCTRLW'b001_0000_000_1_0_1; // sra, srai, srl, srli, sll, slli
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BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_0_1; // illegal instruction
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17'b0110011_0100100_001: BMUControlsD = `BMUCTRLW'b111_0001_000_1_0_1_1_0; // bclr
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17'b0110011_0100100_101: BMUControlsD = `BMUCTRLW'b101_0001_000_1_0_1_1_0; // bext
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17'b0110011_0110100_001: BMUControlsD = `BMUCTRLW'b100_0001_000_1_0_1_0_0; // binv
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17'b0110011_0010100_001: BMUControlsD = `BMUCTRLW'b110_0001_000_1_0_1_0_0; // bset
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17'b0?1?011_0?0000?_?01: BMUControlsD = `BMUCTRLW'b001_0000_000_1_0_1_0_0; // sra, srai, srl, srli, sll, slli
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// ZBC
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17'b0110011_0000101_0??: BMUControlsD = `BMUCTRLW'b000_0010_000_1_0_1; // ZBC instruction
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17'b0110011_0000101_0??: BMUControlsD = `BMUCTRLW'b000_0010_000_1_0_1_0_0; // ZBC instruction
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// ZBA
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17'b0110011_0010000_010: BMUControlsD = `BMUCTRLW'b000_1000_000_1_0_1; // sh1add
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17'b0110011_0010000_100: BMUControlsD = `BMUCTRLW'b000_1000_000_1_0_1; // sh2add
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17'b0110011_0010000_110: BMUControlsD = `BMUCTRLW'b000_1000_000_1_0_1; // sh3add
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17'b0111011_0010000_010: BMUControlsD = `BMUCTRLW'b000_1000_000_1_1_1; // sh1add.uw
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17'b0111011_0010000_100: BMUControlsD = `BMUCTRLW'b000_1000_000_1_1_1; // sh2add.uw
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17'b0111011_0010000_110: BMUControlsD = `BMUCTRLW'b000_1000_000_1_1_1; // sh3add.uw
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17'b0111011_0000100_000: BMUControlsD = `BMUCTRLW'b000_1000_000_1_1_1; // add.uw
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17'b0011011_000010?_001: BMUControlsD = `BMUCTRLW'b001_1000_000_1_1_1; // slli.uw
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17'b0110011_0010000_010: BMUControlsD = `BMUCTRLW'b000_1000_000_1_0_1_0_0; // sh1add
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17'b0110011_0010000_100: BMUControlsD = `BMUCTRLW'b000_1000_000_1_0_1_0_0; // sh2add
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17'b0110011_0010000_110: BMUControlsD = `BMUCTRLW'b000_1000_000_1_0_1_0_0; // sh3add
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17'b0111011_0010000_010: BMUControlsD = `BMUCTRLW'b000_1000_000_1_1_1_0_0; // sh1add.uw
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17'b0111011_0010000_100: BMUControlsD = `BMUCTRLW'b000_1000_000_1_1_1_0_0; // sh2add.uw
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17'b0111011_0010000_110: BMUControlsD = `BMUCTRLW'b000_1000_000_1_1_1_0_0; // sh3add.uw
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17'b0111011_0000100_000: BMUControlsD = `BMUCTRLW'b000_1000_000_1_1_1_0_0; // add.uw
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17'b0011011_000010?_001: BMUControlsD = `BMUCTRLW'b001_1000_000_1_1_1_0_0; // slli.uw
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// ZBB
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17'b0110011_0110000_001: BMUControlsD = `BMUCTRLW'b001_0100_111_1_0_1; // rol
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17'b0111011_0110000_001: BMUControlsD = `BMUCTRLW'b001_0100_111_1_1_1; // rolw
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17'b0110011_0110000_101: BMUControlsD = `BMUCTRLW'b001_0100_111_1_0_1; // ror
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17'b0111011_0110000_101: BMUControlsD = `BMUCTRLW'b001_0100_111_1_1_1; // rorw
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17'b0010011_0110000_101: BMUControlsD = `BMUCTRLW'b001_0100_111_1_0_1; // rori (rv32)
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17'b0110011_0110000_001: BMUControlsD = `BMUCTRLW'b001_0100_111_1_0_1_0_0; // rol
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17'b0111011_0110000_001: BMUControlsD = `BMUCTRLW'b001_0100_111_1_1_1_0_0; // rolw
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17'b0110011_0110000_101: BMUControlsD = `BMUCTRLW'b001_0100_111_1_0_1_0_0; // ror
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17'b0111011_0110000_101: BMUControlsD = `BMUCTRLW'b001_0100_111_1_1_1_0_0; // rorw
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17'b0010011_0110000_101: BMUControlsD = `BMUCTRLW'b001_0100_111_1_0_1_0_0; // rori (rv32)
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17'b0010011_0110001_101: if (`XLEN == 64)
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BMUControlsD = `BMUCTRLW'b001_0100_111_1_0_1; // rori (rv64)
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BMUControlsD = `BMUCTRLW'b001_0100_111_1_0_1_0_0; // rori (rv64)
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else
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BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0; // illegal instruction
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BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_0_1; // illegal instruction
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17'b0011011_0110000_101: if (`XLEN == 64)
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BMUControlsD = `BMUCTRLW'b001_0100_111_1_1_1; // roriw
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BMUControlsD = `BMUCTRLW'b001_0100_111_1_1_1_0_0; // roriw
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else
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BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0; // illegal instruction
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BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_0_1; // illegal instruction
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17'b0010011_0110000_001: if (Rs2D[2])
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BMUControlsD = `BMUCTRLW'b000_0100_100_1_0_1; // sign extend instruction
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BMUControlsD = `BMUCTRLW'b000_0100_100_1_0_1_0_0; // sign extend instruction
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else
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BMUControlsD = `BMUCTRLW'b000_0100_000_1_0_1; // count instruction
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17'b0011011_0110000_001: BMUControlsD = `BMUCTRLW'b000_0100_000_1_1_1; // count word instruction
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BMUControlsD = `BMUCTRLW'b000_0100_000_1_0_1_0_0; // count instruction
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17'b0011011_0110000_001: BMUControlsD = `BMUCTRLW'b000_0100_000_1_1_1_0_0; // count word instruction
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17'b0111011_0000100_100: if (`XLEN == 64)
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BMUControlsD = `BMUCTRLW'b000_0100_100_1_0_1; // zexth (rv64)
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BMUControlsD = `BMUCTRLW'b000_0100_100_1_0_1_0_0; // zexth (rv64)
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else
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BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0; // illegal instruction
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BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_0_1; // illegal instruction
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17'b0110011_0000100_100: if (`XLEN == 32)
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BMUControlsD = `BMUCTRLW'b000_0100_100_1_0_1; // zexth (rv32)
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BMUControlsD = `BMUCTRLW'b000_0100_100_1_0_1_0_0; // zexth (rv32)
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else
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BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0; // illegal instruction
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17'b0110011_0100000_111: BMUControlsD = `BMUCTRLW'b111_0100_111_1_0_1; // andn
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17'b0110011_0100000_110: BMUControlsD = `BMUCTRLW'b110_0100_111_1_0_1; // orn
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17'b0110011_0100000_100: BMUControlsD = `BMUCTRLW'b100_0100_111_1_0_1; // xnor
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BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_0_1; // illegal instruction
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17'b0110011_0100000_111: BMUControlsD = `BMUCTRLW'b111_0100_111_1_0_1_1_0; // andn
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17'b0110011_0100000_110: BMUControlsD = `BMUCTRLW'b110_0100_111_1_0_1_1_0; // orn
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17'b0110011_0100000_100: BMUControlsD = `BMUCTRLW'b100_0100_111_1_0_1_1_0; // xnor
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17'b0010011_0110101_101: if (`XLEN == 64)
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BMUControlsD = `BMUCTRLW'b000_0100_011_1_0_1; // rev8 (rv64)
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BMUControlsD = `BMUCTRLW'b000_0100_011_1_0_1_0_0; // rev8 (rv64)
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else
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BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0; // illegal instruction
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BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_0_1; // illegal instruction
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17'b0010011_0110100_101: if (`XLEN == 32)
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BMUControlsD = `BMUCTRLW'b000_0100_011_1_0_1; // rev8 (rv32)
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BMUControlsD = `BMUCTRLW'b000_0100_011_1_0_1_0_0; // rev8 (rv32)
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else
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BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0; // illegal instruction
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17'b0010011_0010100_101: BMUControlsD = `BMUCTRLW'b000_0100_011_1_0_1; // orc.b
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17'b0110011_0000101_110: BMUControlsD = `BMUCTRLW'b000_0100_101_1_0_1; // max
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17'b0110011_0000101_111: BMUControlsD = `BMUCTRLW'b000_0100_101_1_0_1; // maxu
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17'b0110011_0000101_100: BMUControlsD = `BMUCTRLW'b000_0100_110_1_0_1; // min
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17'b0110011_0000101_101: BMUControlsD = `BMUCTRLW'b000_0100_110_1_0_1; // minu
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BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_0_1; // illegal instruction
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17'b0010011_0010100_101: BMUControlsD = `BMUCTRLW'b000_0100_011_1_0_1_0_0; // orc.b
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17'b0110011_0000101_110: BMUControlsD = `BMUCTRLW'b000_0100_101_1_0_1_0_0; // max
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17'b0110011_0000101_111: BMUControlsD = `BMUCTRLW'b000_0100_101_1_0_1_0_0; // maxu
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17'b0110011_0000101_100: BMUControlsD = `BMUCTRLW'b000_0100_110_1_0_1_0_0; // min
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17'b0110011_0000101_101: BMUControlsD = `BMUCTRLW'b000_0100_110_1_0_1_0_0; // minu
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default: BMUControlsD = {Funct3D, {10'b0}}; // not B instruction or shift
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default: BMUControlsD = {Funct3D, {11'b0}, {1'b1}}; // not B instruction or shift
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endcase
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// Unpack Control Signals
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assign {ALUSelectD,BSelectD,ZBBSelectD, BRegWriteD, BW64D, BALUOpD} = BMUControlsD;
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assign {ALUSelectD,BSelectD,ZBBSelectD, BRegWriteD, BW64D, BALUOpD, BSubArithD, IllegalBitmanipInstrD} = BMUControlsD;
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@ -92,6 +92,9 @@ module controller(
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logic [2:0] ResultSrcD, ResultSrcE, ResultSrcM; // Select which result to write back to register file
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logic [1:0] MemRWD, MemRWE; // Store (write to memory)
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logic ALUOpD; // 0 for address generation, 1 for all other operations (must use Funct3)
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logic BaseALUOpD, BaseW64D; // ALU operation and W64 for Base instructions specifically
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logic BaseRegWriteD; // Indicates if Base instruction register write instruction
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logic BaseSubArithD; // Indicates if Base instruction subtracts, sra, slt, sltu
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logic [2:0] ALUControlD; // Determines ALU operation
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logic [2:0] ALUSelectD; // ALU mux select signal
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logic ALUSrcAD, ALUSrcBD; // ALU inputs
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@ -105,10 +108,8 @@ module controller(
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logic PrivilegedD, PrivilegedE; // Privileged instruction
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logic InvalidateICacheE, FlushDCacheE;// Invalidate I$, flush D$
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logic [`CTRLW-1:0] ControlsD; // Main Instruction Decoder control signals
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logic SubArithD; // TRUE for R-type subtracts and sra, slt, sltu
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logic SubArithD; // TRUE for R-type subtracts and sra, slt, sltu or B-type ext clr, andn, orn, xnor
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logic subD, sraD, sltD, sltuD; // Indicates if is one of these instructions
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logic bclrD, bextD; // Indicates if is one of these instructions
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logic andnD, ornD, xnorD; // Indicates if is one of these instructions
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logic maxE, maxuE, minE, minuE; // Indicates if is one of these instructions in Execute Stage
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logic BranchTakenE; // Branch is taken
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logic eqE, ltE; // Comparator outputs
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@ -117,6 +118,7 @@ module controller(
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logic IEURegWriteE; // Register write
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logic BRegWriteE; // Register write from BMU controller in Execute Stage
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logic IllegalERegAdrD; // RV32E attempts to write upper 16 registers
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logic IllegalBitmanipInstrD; // Unrecognized B instruction
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logic [1:0] AtomicE; // Atomic instruction
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logic FenceD, FenceE; // Fence instruction
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logic SFenceVmaD; // sfence.vma instruction
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@ -126,6 +128,7 @@ module controller(
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logic BRegWriteD; // Indicates if it is a R type B instruction in decode stage
|
||||
logic BW64D; // Indiciates if it is a W type B instruction in decode stage
|
||||
logic BALUOpD; // Indicates if it is an ALU B instruction in decode stage
|
||||
logic BSubArithD; // TRUE for B-type ext, clr, andn, orn, xnor
|
||||
|
||||
|
||||
// Extract fields
|
||||
@ -137,7 +140,7 @@ module controller(
|
||||
// Main Instruction Decoder
|
||||
always_comb
|
||||
case(OpD)
|
||||
// RegWrite_ImmSrc_ALUSrc_MemRW_ResultSrc_Branch_ALUOp_Jump_ALUResultSrc_W64_CSRRead_Privileged_Fence_MDU_Atomic_Illegal
|
||||
// RegWrite_ImmSrc_ALUSrc_MemRW_ResultSrc_Branch_BaseALUOp_Jump_ALUResultSrc_W64_CSRRead_Privileged_Fence_MDU_Atomic_Illegal
|
||||
7'b0000000: ControlsD = `CTRLW'b0_000_00_00_000_0_0_0_0_0_0_0_0_0_00_1; // Illegal instruction
|
||||
7'b0000011: ControlsD = `CTRLW'b1_000_01_10_001_0_0_0_0_0_0_0_0_0_00_0; // lw
|
||||
7'b0000111: ControlsD = `CTRLW'b0_000_01_10_001_0_0_0_0_0_0_0_0_0_00_1; // flw - only legal if FP supported
|
||||
@ -162,14 +165,14 @@ module controller(
|
||||
ControlsD = `CTRLW'b1_101_01_11_001_0_0_0_0_0_0_0_0_0_10_0; // amo
|
||||
end else
|
||||
ControlsD = `CTRLW'b0_000_00_00_000_0_0_0_0_0_0_0_0_0_00_1; // Non-implemented instruction
|
||||
7'b0110011: if (Funct7D == 7'b0000000 | Funct7D == 7'b0100000 | ((`ZBB_SUPPORTED & BSelectD[2]) | (`ZBC_SUPPORTED & BSelectD[1]) | (`ZBS_SUPPORTED & BSelectD[0]) | (`ZBA_SUPPORTED & BSelectD[3])))
|
||||
7'b0110011: if (Funct7D == 7'b0000000 | Funct7D == 7'b0100000)
|
||||
ControlsD = `CTRLW'b1_000_00_00_000_0_1_0_0_0_0_0_0_0_00_0; // R-type
|
||||
else if (Funct7D == 7'b0000001 & (`M_SUPPORTED | (`ZMMUL_SUPPORTED & ~Funct3D[2])))
|
||||
ControlsD = `CTRLW'b1_000_00_00_011_0_0_0_0_0_0_0_0_1_00_0; // Multiply/divide
|
||||
else
|
||||
ControlsD = `CTRLW'b0_000_00_00_000_0_0_0_0_0_0_0_0_0_00_1; // Non-implemented instruction
|
||||
7'b0110111: ControlsD = `CTRLW'b1_100_01_00_000_0_0_0_1_0_0_0_0_0_00_0; // lui
|
||||
7'b0111011: if ((Funct7D == 7'b0000000 | Funct7D == 7'b0100000 | (`ZBA_SUPPORTED & BSelectD[3]) | (`ZBB_SUPPORTED & BSelectD[2])) & `XLEN == 64)
|
||||
7'b0111011: if ((Funct7D == 7'b0000000 | Funct7D == 7'b0100000) & `XLEN == 64)
|
||||
ControlsD = `CTRLW'b1_000_00_00_000_0_1_0_0_1_0_0_0_0_00_0; // R-type W instructions for RV64i
|
||||
else if (Funct7D == 7'b0000001 & (`M_SUPPORTED | (`ZMMUL_SUPPORTED & ~Funct3D[2])) & `XLEN == 64)
|
||||
ControlsD = `CTRLW'b1_000_00_00_011_0_0_0_0_1_0_0_0_1_00_0; // W-type Multiply/Divide
|
||||
@ -192,10 +195,17 @@ module controller(
|
||||
// Squash control signals if coming from an illegal compressed instruction
|
||||
// On RV32E, can't write to upper 16 registers. Checking reads to upper 16 is more costly so disregard them.
|
||||
assign IllegalERegAdrD = `E_SUPPORTED & `ZICSR_SUPPORTED & ControlsD[`CTRLW-1] & InstrD[11];
|
||||
assign IllegalBaseInstrD = ControlsD[0] | IllegalERegAdrD;
|
||||
assign {RegWriteD, ImmSrcD, ALUSrcAD, ALUSrcBD, MemRWD,
|
||||
ResultSrcD, BranchD, ALUOpD, JumpD, ALUResultSrcD, W64D, CSRReadD,
|
||||
assign IllegalBaseInstrD = (ControlsD[0] & IllegalBitmanipInstrD) | IllegalERegAdrD ; //NOTE: Do we want to segregate the IllegalBitmanipInstrD into its own output signal
|
||||
//assign IllegalBaseInstrD = 1'b0;
|
||||
assign {BaseRegWriteD, ImmSrcD, ALUSrcAD, ALUSrcBD, MemRWD,
|
||||
ResultSrcD, BranchD, BaseALUOpD, JumpD, ALUResultSrcD, BaseW64D, CSRReadD,
|
||||
PrivilegedD, FenceXD, MDUD, AtomicD, unused} = IllegalIEUFPUInstrD ? `CTRLW'b0 : ControlsD;
|
||||
|
||||
// If either bitmanip signal or base instruction signal
|
||||
assign ALUOpD = BaseALUOpD | BALUOpD;
|
||||
assign RegWriteD = BaseRegWriteD | BRegWriteD;
|
||||
assign W64D = BaseW64D | BW64D;
|
||||
assign SubArithD = BaseSubArithD | BSubArithD; // TRUE If B-type or R-type instruction involves inverted operand
|
||||
|
||||
|
||||
assign CSRZeroSrcD = InstrD[14] ? (InstrD[19:15] == 0) : (Rs1D == 0); // Is a CSR instruction using zero as the source?
|
||||
@ -211,27 +221,13 @@ module controller(
|
||||
assign sltD = (Funct3D == 3'b010);
|
||||
end
|
||||
|
||||
if (`ZBS_SUPPORTED) begin
|
||||
assign bclrD = (ALUSelectD == 3'b111 & BSelectD[0]);
|
||||
assign bextD = (ALUSelectD == 3'b101 & BSelectD[0]);
|
||||
end else begin
|
||||
assign bclrD = 1'b0;
|
||||
assign bextD = 1'b0;
|
||||
end
|
||||
|
||||
if (`ZBB_SUPPORTED) begin
|
||||
assign andnD = (ALUSelectD == 3'b111 & BSelectD[2]);
|
||||
assign ornD = (ALUSelectD == 3'b110 & BSelectD[2]);
|
||||
assign xnorD = (ALUSelectD == 3'b100 & BSelectD[2]);
|
||||
// we only need these signals if we want to calculate a signedD flag in decode stage to pass to the comparator.
|
||||
assign maxE = (Funct3E[1:0] == 2'b10 & BSelectE[2]);
|
||||
assign maxuE = (Funct3E[1:0] == 2'b11 & BSelectE[2]);
|
||||
assign minE = (Funct3E[1:0] == 2'b00 & BSelectE[2]);
|
||||
assign minuE = (Funct3E[1:0] == 2'b01 & BSelectE[2]);
|
||||
end else begin
|
||||
assign andnD = 0;
|
||||
assign ornD = 0;
|
||||
assign xnorD = 0;
|
||||
assign maxE = 0;
|
||||
assign maxuE = 0;
|
||||
assign minE = 0;
|
||||
@ -242,13 +238,14 @@ module controller(
|
||||
assign sltuD = (Funct3D == 3'b011);
|
||||
assign subD = (Funct3D == 3'b000 & Funct7D[5] & OpD[5]); // OpD[5] needed to distinguish sub from addi
|
||||
assign sraD = (Funct3D == 3'b101 & Funct7D[5]);
|
||||
assign BaseSubArithD = ALUOpD & (subD | sraD | sltD | sltuD);
|
||||
assign ALUControlD = {W64D, SubArithD, ALUOpD};
|
||||
|
||||
// BITMANIP Configuration Block
|
||||
if (`ZBS_SUPPORTED | `ZBA_SUPPORTED | `ZBB_SUPPORTED | `ZBC_SUPPORTED) begin: bitmanipi //change the conditional expression to OR any Z supported flags
|
||||
bmuctrl bmuctrl(.clk, .reset, .StallD, .FlushD, .InstrD, .ALUSelectD, .BSelectD, .ZBBSelectD, .BRegWriteD, .BW64D, .BALUOpD, .StallE, .FlushE, .ALUSelectE, .BSelectE, .ZBBSelectE, .BRegWriteE);
|
||||
bmuctrl bmuctrl(.clk, .reset, .StallD, .FlushD, .InstrD, .ALUSelectD, .BSelectD, .ZBBSelectD, .BRegWriteD, .BW64D, .BALUOpD, .BSubArithD, .IllegalBitmanipInstrD, .StallE, .FlushE, .ALUSelectE, .BSelectE, .ZBBSelectE, .BRegWriteE);
|
||||
|
||||
assign RegWriteE = IEURegWriteE | FWriteIntE | BRegWriteE; // IRF register writes could come from IEU, BMU or FPU controllers
|
||||
assign SubArithD = (ALUOpD | BALUOpD) & (subD | sraD | sltD | sltuD | (`ZBS_SUPPORTED & (bextD | bclrD)) | (`ZBB_SUPPORTED & (andnD | ornD | xnorD))); // TRUE for R-type subtracts and sra, slt, sltu, and any B instruction that requires inverted operand
|
||||
assign ALUControlD = {(W64D | BW64D), SubArithD, ALUOpD};
|
||||
//assign SubArithD = (ALUOpD) & (subD | sraD | sltD | sltuD | (`ZBS_SUPPORTED & (bextD | bclrD)) | (`ZBB_SUPPORTED & (andnD | ornD | xnorD))); // TRUE for R-type subtracts and sra, slt, sltu, and any B instruction that requires inverted operand
|
||||
end else begin: bitmanipi
|
||||
assign ALUSelectD = Funct3D;
|
||||
assign ALUSelectE = Funct3E;
|
||||
@ -259,10 +256,10 @@ module controller(
|
||||
assign BW64D = 1'b0;
|
||||
assign BALUOpD = 1'b0;
|
||||
assign BRegWriteE = 1'b0;
|
||||
assign BSubArithD = 1'b0;
|
||||
|
||||
assign RegWriteE = IEURegWriteE | FWriteIntE; // IRF register writes could come from IEU or FPU controllers
|
||||
assign SubArithD = ALUOpD & (subD | sraD | sltD | sltuD);
|
||||
assign ALUControlD = {W64D, SubArithD, ALUOpD};
|
||||
|
||||
assign IllegalBitmanipInstrD = 1'b1;
|
||||
end
|
||||
|
||||
// Fences
|
||||
@ -299,6 +296,7 @@ module controller(
|
||||
// Other execute stage controller signals
|
||||
assign MemReadE = MemRWE[1];
|
||||
assign SCE = (ResultSrcE == 3'b100);
|
||||
assign RegWriteE = IEURegWriteE | FWriteIntE; // IRF register writes could come from IEU or FPU controllers
|
||||
assign IntDivE = MDUE & Funct3E[2]; // Integer division operation
|
||||
|
||||
// Memory stage pipeline control register
|
||||
|
||||
Loading…
Reference in New Issue
Block a user