forked from Github_Repos/cvw
Modified the linux test bench to take a new parameter which can run simulation from 470M out to login prompt. This shouldn't break the regression test or checkpointing.
This commit is contained in:
Ross Thompson
parent
a09360f207
commit
fc5eac6820
@ -35,7 +35,7 @@ if {$2 eq "buildroot" || $2 eq "buildroot-checkpoint"} {
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vlog -lint -work work_${1}_${2} +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench-linux.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583
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# start and run simulation
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vopt +acc work_${1}_${2}.testbench -work work_${1}_${2} -G RISCV_DIR=$3 -G INSTR_LIMIT=$4 -G INSTR_WAVEON=$5 -G CHECKPOINT=$6 -o testbenchopt
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vsim -lib work_${1}_${2} testbenchopt -suppress 8852,12070,3084
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vsim -lib work_${1}_${2} testbenchopt -suppress 8852,12070,3084,3829
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#-- Run the Simulation
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run -all
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@ -44,7 +44,28 @@ if {$2 eq "buildroot" || $2 eq "buildroot-checkpoint"} {
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run -all
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exec ./slack-notifier/slack-notifier.py
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} else {
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} elseif {$2 eq "buildroot-no-trace"} {
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vlog -lint -work work_${1}_${2} +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench-linux.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583
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# start and run simulation
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vopt +acc work_${1}_${2}.testbench -work work_${1}_${2} -G RISCV_DIR=$3 -G INSTR_LIMIT=470350800 -G INSTR_WAVEON=470350800 -G CHECKPOINT=470350800 -G NO_IE_MTIME_CHECKPOINT=1 -o testbenchopt
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vsim -lib work_${1}_${2} testbenchopt -suppress 8852,12070,3084,3829
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#-- Run the Simulation
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echo "!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!"
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echo "Don't forget to change DEBUG_LEVEL = 0."
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echo "!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!"
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run 100 ns
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force -deposit testbench/dut/core/priv/priv/csr/csri/IE_REGW 16'h2aa
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force -deposit testbench/dut/uncore/clint/clint/MTIMECMP 64'h1000
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run 1200 ms
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#add log -recursive /*
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#do linux-wave.do
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#run -all
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exec ./slack-notifier/slack-notifier.py
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} else {
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vlog +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583 -suppress 7063
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vopt +acc work.testbench -G TEST=$2 -G DEBUG=1 -o workopt
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@ -67,3 +88,21 @@ if {$2 eq "buildroot" || $2 eq "buildroot-checkpoint"} {
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view wave
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}
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#elseif {$2 eq "buildroot-no-trace""} {
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# vlog -lint -work work_${1}_${2} +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench-linux.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583
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# start and run simulation
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# vopt +acc work_${1}_${2}.testbench -work work_${1}_${2} -G RISCV_DIR=$3 -G INSTR_LIMIT=470350800 -G INSTR_WAVEON=470350800 -G CHECKPOINT=470350800 -G DEBUG_TRACE=0 -o testbenchopt
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# vsim -lib work_${1}_${2} testbenchopt -suppress 8852,12070,3084,3829
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#-- Run the Simulation
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# run 100 ns
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# force -deposit testbench/dut/core/priv/priv/csr/csri/IE_REGW 16'h2aa
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# force -deposit testbench/dut/uncore/clint/clint/MTIMECMP 64'h1000
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# add log -recursive /*
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# do linux-wave.do
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# run -all
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# exec ./slack-notifier/slack-notifier.py
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#}
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@ -45,6 +45,7 @@ module testbench;
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parameter INSTR_WAVEON = 0; // # of instructions at which to turn on waves in graphical sim
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parameter CHECKPOINT = 0;
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parameter RISCV_DIR = "/opt/riscv";
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parameter NO_IE_MTIME_CHECKPOINT = 0;
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///////////////////////////////////////////////////////////////////////////////
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////////////////////////////////// HARDWARE ///////////////////////////////////
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@ -76,7 +77,16 @@ module testbench;
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logic SDCCmdOut;
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logic SDCCmdOE;
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logic [3:0] SDCDatIn;
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logic probe;
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if (NO_IE_MTIME_CHECKPOINT)
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assign probe = testbench.dut.core.PCM == 64'hffffffff80200c8c
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& testbench.dut.core.InstrM != 32'h14021273
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& testbench.dut.core.InstrValidM;
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else assign probe = 0;
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assign GPIOPinsIn = 0;
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assign UARTSin = 1;
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wallypipelinedsoc dut(.clk, .reset, .reset_ext,
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@ -316,10 +326,12 @@ module testbench;
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`INIT_CHECKPOINT_VAL(PC, [`XLEN-1:0]);
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`INIT_CHECKPOINT_VAL(MEDELEG, [`XLEN-1:0]);
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`INIT_CHECKPOINT_VAL(MIDELEG, [`XLEN-1:0]);
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`INIT_CHECKPOINT_VAL(MIE, [11:0]);
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`INIT_CHECKPOINT_VAL(MIP, [11:0]);
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`INIT_CHECKPOINT_VAL(SIE, [11:0]);
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`INIT_CHECKPOINT_VAL(SIP, [11:0]);
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if(!NO_IE_MTIME_CHECKPOINT) begin
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`INIT_CHECKPOINT_VAL(MIE, [11:0]);
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`INIT_CHECKPOINT_VAL(MIP, [11:0]);
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`INIT_CHECKPOINT_VAL(SIE, [11:0]);
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`INIT_CHECKPOINT_VAL(SIP, [11:0]);
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end
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`INIT_CHECKPOINT_VAL(MCAUSE, [`XLEN-1:0]);
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`INIT_CHECKPOINT_VAL(SCAUSE, [`XLEN-1:0]);
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`INIT_CHECKPOINT_VAL(MEPC, [`XLEN-1:0]);
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@ -350,13 +362,13 @@ module testbench;
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`INIT_CHECKPOINT_VAL(UART_SCR, [7:0]);
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`INIT_CHECKPOINT_PACKED_ARRAY(PLIC_INT_PRIORITY, [2:0],`PLIC_NUM_SRC,1);
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`INIT_CHECKPOINT_PACKED_ARRAY(PLIC_INT_ENABLE, [`PLIC_NUM_SRC:1],1,0);
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`INIT_CHECKPOINT_PACKED_ARRAY(PLIC_THRESHOLD, [2:0],1,0);
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`INIT_CHECKPOINT_PACKED_ARRAY(PLIC_THRESHOLD,[ 2:0],1,0);
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integer memFile;
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integer readResult;
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initial begin
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force dut.core.priv.priv.SwIntM = 0;
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force dut.core.priv.priv.TimerIntM = 0;
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if(!NO_IE_MTIME_CHECKPOINT) force dut.core.priv.priv.TimerIntM = 0;
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force dut.core.priv.priv.MExtIntM = 0;
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$sformat(testvectorDir,"%s/linux-testvectors/",RISCV_DIR);
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$sformat(linuxImageDir,"%s/buildroot/output/images/",RISCV_DIR);
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@ -515,7 +527,8 @@ module testbench;
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release dut.core.ieu.dp.ReadDataM; \
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if(textM.substr(0,5) == "rdtime") begin \
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//$display("%tns, %d instrs: Overwrite MTIME_CLINT on read of MTIME in memory stage.", $time, InstrCountW-1); \
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force dut.uncore.clint.clint.MTIME = ExpectedRegValueM; \
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if(!NO_IE_MTIME_CHECKPOINT) \
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force dut.uncore.clint.clint.MTIME = ExpectedRegValueM; \
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end \
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end \
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end \
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@ -546,7 +559,8 @@ module testbench;
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MIPexpected = NextMIPexpected;
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//force dut.core.priv.priv.csr.csri.MIP_REGW = MIPexpected;
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//force dut.core.priv.priv.csr.csri.SIP_REGW = MIPexpected;
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force dut.core.priv.priv.csr.csri.IP_REGW = MIPexpected;
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if(!NO_IE_MTIME_CHECKPOINT)
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force dut.core.priv.priv.csr.csri.IP_REGW = MIPexpected;
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end
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// $display("%tn: ExpectedCSRArrayM = %p",$time,ExpectedCSRArrayM);
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// $display("%tn: ExpectedCSRArrayValueM = %p",$time,ExpectedCSRArrayValueM);
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@ -563,7 +577,8 @@ module testbench;
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MIPexpected = NextMIPexpected;
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//force dut.core.priv.priv.csr.csri.MIP_REGW = MIPexpected;
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//force dut.core.priv.priv.csr.csri.SIP_REGW = MIPexpected;
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force dut.core.priv.priv.csr.csri.IP_REGW = MIPexpected;
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if(!NO_IE_MTIME_CHECKPOINT)
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force dut.core.priv.priv.csr.csri.IP_REGW = MIPexpected;
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$display("%tns: Finished Executing Delayed MIP. Current MEPC value is %x",$time,dut.core.priv.priv.csr.csrm.MEPC_REGW);
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RequestDelayedMIP = 0;
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end
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@ -656,7 +671,8 @@ module testbench;
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if(~dut.core.StallW) begin
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if(textW.substr(0,5) == "rdtime") begin
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//$display("%tns, %d instrs: Releasing force of MTIME_CLINT.", $time, InstrCountW);
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release dut.uncore.clint.clint.MTIME;
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if(!NO_IE_MTIME_CHECKPOINT)
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release dut.uncore.clint.clint.MTIME;
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end
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//if (ExpectedIEUAdrM == 'h10000005) begin
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//$display("%tns, %d instrs: releasing force of ReadDataM.", $time, InstrCountW);
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