Merge pull request #51 from stineje/main

Modify generic/mem for rv32gc ram2

pipelined/src/generic/mem/ram2p1r1wbe.sv

@@ -64,6 +64,18 @@ module ram2p1r1wbe #(parameter DEPTH=128, WIDTH=256) (
 				  .QA(rd1),
 				  .QB());
 
+   end if (`USE_SRAM == 1 && WIDTH == 36 && DEPTH == 1024) begin
+   
+      ram2p1r1wbe_1024x36 memory1(.CLKA(clk), .CLKB(clk), 
+				  .CEBA(~ce1), .CEBB(~ce2),
+				  .WEBA('0), .WEBB(~we2),			      
+				  .AA(ra1), .AB(wa2),
+				  .DA('0),
+				  .DB(wd2),
+				  .BWEBA('0), .BWEBB('1),
+				  .QA(rd1),
+				  .QB());      
+
    end else if (`USE_SRAM == 1 && WIDTH == 2 && DEPTH == 1024) begin
 
       logic [SRAMWIDTH-1:0]     SRAMReadData;      

pipelined/src/generic/mem/ram2p1r1wbe_1024x36.sv

@@ -0,0 +1,48 @@
+///////////////////////////////////////////
+// ram2p1rwbe_1024x36.sv
+//
+// Written: james.stine@okstate.edu 2 February 2023
+// Modified: 
+//
+// Purpose: RAM wrapper for instantiating RAM IP
+// 
+// A component of the CORE-V-WALLY configurable RISC-V project.
+// 
+// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
+//
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+//
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
+//
+// https://solderpad.org/licenses/SHL-2.1/
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
+////////////////////////////////////////////////////////////////////////////////////////////////
+
+module ram2p1r1wbe_1024x36( 
+  input  logic          CLKA, 
+  input  logic          CLKB, 
+  input  logic 	        CEBA, 
+  input  logic 	        CEBB, 
+  input  logic          WEBA,
+  input  logic          WEBB,
+  input  logic [9:0]    AA, 
+  input  logic [9:0]    AB, 
+  input  logic [35:0]   DA,
+  input  logic [35:0]   DB,
+  input  logic [35:0]   BWEBA, 
+  input  logic [35:0]   BWEBB, 
+  output logic [35:0]   QA,
+  output logic [35:0]   QB
+);
+
+   // replace "generic1024x36RAM" with "TSDN..1024X36.." module from your memory vendor
+   generic1024x36RAM sramIP (.CLKA, .CLKB, .CEBA, .CEBB, .WEBA, .WEBB, 
+   			     .AA, .AB, .DA, .DB, .BWEBA, .BWEBB, .QA, .QB);
+
+endmodule

pipelined/src/generic/mem/ram2p1r1wbe_1024x68.sv

@@ -41,7 +41,7 @@ module ram2p1r1wbe_1024x68(
   output logic [67:0]   QB
 );
 
-   // replace "generic1024x69RAM" with "TSDN..1024X69.." module from your memory vendor
+   // replace "generic1024x68RAM" with "TSDN..1024X68.." module from your memory vendor
    generic1024x68RAM sramIP (.CLKA, .CLKB, .CEBA, .CEBB, .WEBA, .WEBB, 
 			     .AA, .AB, .DA, .DB, .BWEBA, .BWEBB, .QA, .QB);
 

pipelined/src/generic/mem/rom1p1r.sv

@@ -38,9 +38,12 @@ module rom1p1r #(parameter ADDR_WIDTH = 8,
 
    // Core Memory
    logic [DATA_WIDTH-1:0] 	 ROM [(2**ADDR_WIDTH)-1:0];
-   if (`USE_SRAM == 1 && DATA_WIDTH == 64 && `XLEN == 64) begin
+   if (`USE_SRAM == 1 && DATA_WIDTH == 64) begin
       rom1p1r_128x64 rom1 (.CLK(clk), .CEB(~ce), .A(addr[6:0]), .Q(dout));
 
+   end if (`USE_SRAM == 1 && DATA_WIDTH == 32) begin
+      rom1p1r_128x32 rom1 (.CLK(clk), .CEB(~ce), .A(addr[6:0]), .Q(dout));      
+
    end else begin
       always @ (posedge clk) begin
 	 if(ce) dout <= ROM[addr];