forked from Github_Repos/cvw
Begin cleanup of ifu. partial move of pc muxes inside bp.
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@ -41,8 +41,8 @@ module bpred
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// the prediction
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input logic [31:0] InstrD,
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input logic [`XLEN-1:0] PCNextF, // *** forgot to include this one on the I/O list
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output logic [`XLEN-1:0] BPPredPCF,
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output logic SelBPPredF,
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input logic [`XLEN-1:0] PCPlus2or4F,
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output logic [`XLEN-1:0] PCNext0F,
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// Update Predictor
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input logic [`XLEN-1:0] PCE, // The address of the currently executing instruction
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// 1 hot encoding
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@ -57,7 +57,7 @@ module bpred
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output logic [4:0] InstrClassM,
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// Report branch prediction status
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output logic BPPredWrongE,
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output logic BPPredWrongM,
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output logic BPPredWrongM,
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output logic BPPredDirWrongM,
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output logic BTBPredPCWrongM,
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output logic RASPredPCWrongM,
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@ -76,6 +76,10 @@ module bpred
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logic [4:0] InstrClassD, InstrClassE;
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logic BPPredDirWrongE, BTBPredPCWrongE, RASPredPCWrongE, BPPredClassNonCFIWrongE;
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logic SelBPPredF;
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logic [`XLEN-1:0] BPPredPCF;
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// Part 1 branch direction prediction
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@ -250,4 +254,8 @@ module bpred
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.OldState(BPPredE),
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.NewState(UpdateBPPredE));
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mux2 #(`XLEN) pcmux0(.d0(PCPlus2or4F), .d1(BPPredPCF), .s(SelBPPredF), .y(PCNext0F));
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endmodule
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@ -306,16 +306,13 @@ module ifu (
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////////////////////////////////////////////////////////////////////////////////////////////////
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if (`BPRED_ENABLED) begin : bpred
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logic BPPredWrongM;
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logic SelBPPredF;
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logic [`XLEN-1:0] BPPredPCF;
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bpred bpred(.clk, .reset,
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.StallF, .StallD, .StallE, .StallM,
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.FlushD, .FlushE, .FlushM,
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.InstrD, .PCNextF, .BPPredPCF, .SelBPPredF, .PCE, .PCSrcE, .IEUAdrE,
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.InstrD, .PCNextF, .PCPlus2or4F, .PCNext0F, .PCE, .PCSrcE, .IEUAdrE,
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.PCD, .PCLinkE, .InstrClassM, .BPPredWrongE, .BPPredWrongM,
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.BPPredDirWrongM, .BTBPredPCWrongM, .RASPredPCWrongM, .BPPredClassNonCFIWrongM);
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mux2 #(`XLEN) pcmux0(.d0(PCPlus2or4F), .d1(BPPredPCF), .s(SelBPPredF), .y(PCNext0F));
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// Mux only required on instruction class miss prediction.
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mux2 #(`XLEN) pcmuxBPWrongInvalidateFlush(.d0(PCE), .d1(PCF),
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.s(BPPredWrongM), .y(PCBPWrongInvalidate));
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