Xavi/cvw
1
0
Fork 0
forked from Github_Repos/cvw
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Integrated the missing zifence tests into the regression test.

Browse Source
This commit is contained in:
Ross Thompson 2023-01-20 10:34:49 -06:00
parent 29f45d6203
commit 5b5a615e4a
3 changed files with 15 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
pipelined/regression/regression-wally
View File

@ -66,7 +66,7 @@ tc = TestCase(
configs.append(tc)
tests64gcimperas = ["imperas64i", "imperas64f", "imperas64d", "imperas64m", "imperas64c"] # unused
tests64gc = ["arch64f", "arch64d", "arch64i", "arch64priv", "arch64c", "arch64m", "wally64a", "wally64periph", "wally64priv"]
tests64gc = ["arch64f", "arch64d", "arch64i", "arch64priv", "arch64c", "arch64m", "arch64zi", "wally64a", "wally64periph", "wally64priv"]
for test in tests64gc:
tc = TestCase(
name=test,
@ -85,7 +85,7 @@ for test in tests64i:
configs.append(tc)
tests32gcimperas = ["imperas32i", "imperas32f", "imperas32m", "imperas32c"] # unused
tests32gc = ["arch32f", "arch32d", "arch32i", "arch32priv", "arch32c", "arch32m", "wally32a", "wally32priv", "wally32periph"]
tests32gc = ["arch32f", "arch32d", "arch32i", "arch32priv", "arch32c", "arch32m", "arch32zi", "wally32a", "wally32priv", "wally32periph"]
for test in tests32gc:
tc = TestCase(
name=test,
@ -95,7 +95,7 @@ for test in tests32gc:
configs.append(tc)
tests32icimperas = ["imperas32i", "imperas32c"] # unused
tests32ic = ["arch32i", "arch32c","wally32periph"]
tests32ic = ["arch32i", "arch32c", "wally32periph"]
for test in tests32ic:
tc = TestCase(
name=test,

2
pipelined/testbench/testbench.sv
View File

@ -94,6 +94,7 @@ logic [3:0] dummy;
"arch64m": if (`M_SUPPORTED) tests = arch64m;
"arch64f": if (`F_SUPPORTED) tests = arch64f;
"arch64d": if (`D_SUPPORTED) tests = arch64d;
"arch64zi": if (`ZIFENCEI_SUPPORTED) tests = arch64zi;
"imperas64i": tests = imperas64i;
"imperas64f": if (`F_SUPPORTED) tests = imperas64f;
"imperas64d": if (`D_SUPPORTED) tests = imperas64d;
@ -119,6 +120,7 @@ logic [3:0] dummy;
"arch32m": if (`M_SUPPORTED) tests = arch32m;
"arch32f": if (`F_SUPPORTED) tests = arch32f;
"arch32d": if (`D_SUPPORTED) tests = arch32d;
"arch32zi": if (`ZIFENCEI_SUPPORTED) tests = arch32zi;
"imperas32i": tests = imperas32i;
"imperas32f": if (`F_SUPPORTED) tests = imperas32f;
"imperas32m": if (`M_SUPPORTED) tests = imperas32m;

10
pipelined/testbench/tests.vh
View File

@ -934,6 +934,16 @@ string imperas32f[] = '{
"rv64i_m/privilege/src/misalign-sw-01.S"
};
string arch64zi[] = '{
`RISCVARCHTEST,
"rv64i_m/Zifencei/src/Fencei.S"
};
string arch32zi[] = '{
`RISCVARCHTEST,
"rv32i_m/Zifencei/src/Fencei.S"
};
string arch64m[] = '{
`RISCVARCHTEST,
"rv64i_m/M/src/div-01.S",