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Minor optimizations.

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This commit is contained in:
Ross Thompson 2022-12-23 20:11:36 -06:00
parent 6e9d1eb180
commit b0d6c9616e
2 changed files with 3 additions and 3 deletions
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2
pipelined/src/cache/cachefsm.sv vendored
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@ -185,6 +185,6 @@ module cachefsm
resetDelay;
assign SelFetchBuffer = CurrState == STATE_WRITE_LINE | CurrState == STATE_READ_HOLD;
assign CacheEn = (CurrState == STATE_READY & (~Stall | FlushCache | AnyMiss)) | (CurrState != STATE_READY) | reset;
assign CacheEn = (~Stall | FlushCache | AnyMiss) | (CurrState != STATE_READY) | reset;
endmodule // cachefsm

4
pipelined/src/hazard/hazard.sv
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@ -67,8 +67,8 @@ module hazard(
// Similarly, CSR writes and fences flush all subsequent instructions and refetch them in light of the new operating modes and cache/TLB contents
// Branch misprediction is found in the Execute stage and must flush the next two instructions.
// However, an active division operation resides in the Execute stage, and when the BP incorrectly mispredicts the divide as a taken branch, the divde must still complete
assign FlushDCause = TrapM | RetM | BPPredWrongE | CSRWriteFenceM;
assign FlushECause = TrapM | RetM | (BPPredWrongE & ~(DivBusyE | FDivBusyE)) | CSRWriteFenceM;
assign FlushDCause = TrapM | RetM | CSRWriteFenceM | BPPredWrongE;
assign FlushECause = TrapM | RetM | CSRWriteFenceM |(BPPredWrongE & ~(DivBusyE | FDivBusyE));
assign FlushMCause = TrapM | RetM | CSRWriteFenceM;
assign FlushWCause = TrapM & ~(BreakpointFaultM | EcallFaultM);