forked from Github_Repos/cvw
FPU comments
This commit is contained in:
David Harris
parent
654abcde61
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15026f61f7
@ -43,7 +43,7 @@ module fdivsqrt(
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input logic [`XLEN-1:0] ForwardedSrcAE, ForwardedSrcBE, // these are the src outputs before the mux choosing between them and PCE to put in srcA/B
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input logic [2:0] Funct3E, Funct3M,
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input logic IntDivE, W64E,
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output logic DivSM,
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output logic DivStickyM,
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output logic FDivBusyE, IFDivStartE, FDivDoneE,
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output logic [`NE+1:0] QeM,
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output logic [`DIVb:0] QmM,
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@ -94,7 +94,7 @@ module fdivsqrt(
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fdivsqrtpostproc fdivsqrtpostproc( // Postprocessor
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.clk, .reset, .StallM, .WS, .WC, .D, .FirstU, .FirstUM, .FirstC,
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.SqrtE, .Firstun, .SqrtM, .SpecialCaseM,
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.QmM, .WZeroE, .DivSM,
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.QmM, .WZeroE, .DivStickyM,
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// Int-specific
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.nM, .mM, .ALTBM, .AsM, .BZeroM, .NegQuotM, .W64M, .RemOpM(Funct3M[1]), .AM,
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.FPIntDivResultM);
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@ -40,7 +40,7 @@ module fdivsqrtpostproc(
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input logic [`DIVBLEN:0] nM, mM,
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output logic [`DIVb:0] QmM,
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output logic WZeroE,
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output logic DivSM,
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output logic DivStickyM,
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output logic [`XLEN-1:0] FPIntDivResultM
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);
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@ -86,7 +86,7 @@ module fdivsqrtpostproc(
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//////////////////////////
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// If the result is not exact, the sticky should be set
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assign DivSM = ~WZeroM & ~(SpecialCaseM & SqrtM); // ***unsure why SpecialCaseM has to be gated by SqrtM, but otherwise fails regression on divide
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assign DivStickyM = ~WZeroM & ~(SpecialCaseM & SqrtM); // ***unsure why SpecialCaseM has to be gated by SqrtM, but otherwise fails regression on divide
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// Determine if sticky bit is negative // *** look for ways to optimize this. Shift shouldn't be needed.
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assign Sum = WC + WS;
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@ -29,110 +29,118 @@
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module fpu (
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input logic clk,
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input logic reset,
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input logic [2:0] FRM_REGW, // Rounding mode (from CSR)
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input logic [31:0] InstrD, // instruction (from IFU)
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input logic [`FLEN-1:0] ReadDataW, // Read data (from LSU)
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input logic [`XLEN-1:0] ForwardedSrcAE, ForwardedSrcBE, // Integer input (from IEU)
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// Hazards
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input logic StallE, StallM, StallW, // stall signals (from HZU)
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input logic FlushE, FlushM, FlushW, // flush signals (from HZU)
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input logic [4:0] RdE, RdM, RdW, // which FP register to write to (from IEU)
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input logic [1:0] STATUS_FS, // Is floating-point enabled? (From privileged unit)
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input logic [2:0] Funct3E, Funct3M, // Funct fields of instruction specify type of operations
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input logic IntDivE, W64E, //
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output logic FRegWriteM, // FP register write enable (to privileged unit)
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output logic FpLoadStoreM, // Fp load instruction? (to LSU)
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output logic FPUStallD, // Stall the decode stage (To HZU)
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output logic FDivBusyE, // Is the divide/sqrt unit busy (stall execute stage) (to HZU)
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// CSRs
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input logic [1:0] STATUS_FS, // Is floating-point enabled? (From privileged unit)
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input logic [2:0] FRM_REGW, // Rounding mode (from CSR)
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// Decode stage
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input logic [31:0] InstrD, // instruction (from IFU)
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// Execute stage
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input logic [2:0] Funct3E, // Funct fields of instruction specify type of operations
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input logic IntDivE, W64E, // Integer division on FPU
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input logic [`XLEN-1:0] ForwardedSrcAE, ForwardedSrcBE, // Integer input for convert, move, and int div (from IEU)
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input logic [4:0] RdE, // which FP register to write to (from IEU)
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output logic FWriteIntE, // integer register write enable (to IEU)
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output logic FCvtIntE, // Convert to int (to IEU)
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// Memory stage
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input logic [2:0] Funct3M, // Funct fields of instruction specify type of operations
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input logic [4:0] RdM, // which FP register to write to (from IEU)
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output logic FRegWriteM, // FP register write enable (to privileged unit)
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output logic FpLoadStoreM, // Fp load instruction? (to LSU)
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output logic [`FLEN-1:0] FWriteDataM, // Data to be written to memory (to LSU)
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output logic [`XLEN-1:0] FIntResM, // data to be written to integer register (to IEU)
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output logic [`XLEN-1:0] FCvtIntResW, // convert result to to be written to integer register (to IEU)
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output logic FCvtIntW, // select FCvtIntRes (to IEU)
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output logic FDivBusyE, // Is the divide/sqrt unit busy (stall execute stage) (to HZU)
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output logic IllegalFPUInstrM, // Is the instruction an illegal fpu instruction (to privileged unit)
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output logic [4:0] SetFflagsM, // FPU flags (to privileged unit)
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output logic [`XLEN-1:0] FPIntDivResultW
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// Writeback stage
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input logic [4:0] RdW, // which FP register to write to (from IEU)
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input logic [`FLEN-1:0] ReadDataW, // Read data (from LSU)
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output logic [`XLEN-1:0] FCvtIntResW, // convert result to to be written to integer register (to IEU)
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output logic FCvtIntW, // select FCvtIntRes (to IEU)
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output logic [`XLEN-1:0] FPIntDivResultW // Result from integer division (to IEU)
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);
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// FPU specifics:
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// - uses NaN-blocking format
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// - if there are any unsused bits the most significant bits are filled with 1s
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// single stored in a double: | 32 1s | single precision value |
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// - sets the underflow after rounding
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// RISC-V FPU specifics:
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// - multiprecision support uses NAN-boxing, putting 1's in unused msbs
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// - RISC-V detects underflow after rounding
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// control signals
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logic FRegWriteW; // FP register write enable
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logic [2:0] FrmM; // FP rounding mode
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logic [`FMTBITS-1:0] FmtE, FmtM; // FP precision 0-single 1-double
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logic FDivStartE, IDivStartE; // Start division or squareroot
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logic FWriteIntM; // Write to integer register
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logic [1:0] ForwardXE, ForwardYE, ForwardZE; // forwarding mux control signals
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logic [2:0] OpCtrlE, OpCtrlM; // Select which opperation to do in each component
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logic [1:0] FResSelE, FResSelM, FResSelW; // Select one of the results that finish in the memory stage
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logic [1:0] PostProcSelE, PostProcSelM; // select result in the post processing unit
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logic [4:0] Adr1D, Adr2D, Adr3D; // adresses of each input
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logic [4:0] Adr1E, Adr2E, Adr3E; // adresses of each input
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logic XEnD, YEnD, ZEnD;
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logic XEnE, YEnE, ZEnE;
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logic FRegWriteE;
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logic FRegWriteW; // FP register write enable
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logic [2:0] FrmM; // FP rounding mode
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logic [`FMTBITS-1:0] FmtE, FmtM; // FP precision 0-single 1-double
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logic FDivStartE, IDivStartE; // Start division or squareroot
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logic FWriteIntM; // Write to integer register
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logic [1:0] ForwardXE, ForwardYE, ForwardZE; // forwarding mux control signals
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logic [2:0] OpCtrlE, OpCtrlM; // Select which opperation to do in each component
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logic [1:0] FResSelE, FResSelM, FResSelW; // Select one of the results that finish in the memory stage
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logic [1:0] PostProcSelE, PostProcSelM; // select result in the post processing unit
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logic [4:0] Adr1D, Adr2D, Adr3D; // register adresses of each input
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logic [4:0] Adr1E, Adr2E, Adr3E; // register adresses of each input
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logic XEnD, YEnD, ZEnD; // X, Y, Z inputs used for current operation
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logic XEnE, YEnE, ZEnE; // X, Y, Z inputs used for current operation
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logic FRegWriteE; // Write floating-point register
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// regfile signals
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logic [`FLEN-1:0] FRD1D, FRD2D, FRD3D; // Read Data from FP register - decode stage
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logic [`FLEN-1:0] FRD1E, FRD2E, FRD3E; // Read Data from FP register - execute stage
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logic [`FLEN-1:0] XE; // Input 1 to the various units (after forwarding)
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logic [`FLEN-1:0] FRD1D, FRD2D, FRD3D; // Read Data from FP register - decode stage
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logic [`FLEN-1:0] FRD1E, FRD2E, FRD3E; // Read Data from FP register - execute stage
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logic [`FLEN-1:0] XE; // Input 1 to the various units (after forwarding)
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logic [`XLEN-1:0] IntSrcXE; // Input 1 to the various units (after forwarding)
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logic [`FLEN-1:0] PreYE, YE; // Input 2 to the various units (after forwarding)
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logic [`FLEN-1:0] PreZE, ZE; // Input 3 to the various units (after forwarding)
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logic [`FLEN-1:0] PreYE, YE; // Input 2 to the various units (after forwarding)
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logic [`FLEN-1:0] PreZE, ZE; // Input 3 to the various units (after forwarding)
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// unpacking signals
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logic XsE, YsE, ZsE; // input's sign - execute stage
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logic XsM, YsM; // input's sign - memory stage
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logic [`NE-1:0] XeE, YeE, ZeE; // input's exponent - execute stage
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logic [`NE-1:0] ZeM; // input's exponent - memory stage
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logic [`NF:0] XmE, YmE, ZmE; // input's fraction - execute stage
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logic [`NF:0] XmM, YmM, ZmM; // input's fraction - memory stage
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logic XNaNE, YNaNE, ZNaNE; // is the input a NaN - execute stage
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logic XNaNM, YNaNM, ZNaNM; // is the input a NaN - memory stage
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logic XSNaNE, YSNaNE, ZSNaNE; // is the input a signaling NaN - execute stage
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logic XSNaNM, YSNaNM, ZSNaNM; // is the input a signaling NaN - memory stage
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logic XSubnormE; // is the input Subnormalized
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logic XZeroE, YZeroE, ZZeroE; // is the input zero - execute stage
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logic XZeroM, YZeroM; // is the input zero - memory stage
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logic XInfE, YInfE, ZInfE; // is the input infinity - execute stage
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logic XInfM, YInfM, ZInfM; // is the input infinity - memory stage
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logic XExpMaxE; // is the exponent all ones (max value)
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logic XsE, YsE, ZsE; // input's sign - execute stage
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logic XsM, YsM; // input's sign - memory stage
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logic [`NE-1:0] XeE, YeE, ZeE; // input's exponent - execute stage
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logic [`NE-1:0] ZeM; // input's exponent - memory stage
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logic [`NF:0] XmE, YmE, ZmE; // input's significand - execute stage
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logic [`NF:0] XmM, YmM, ZmM; // input's significand - memory stage
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logic XNaNE, YNaNE, ZNaNE; // is the input a NaN - execute stage
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logic XNaNM, YNaNM, ZNaNM; // is the input a NaN - memory stage
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logic XSNaNE, YSNaNE, ZSNaNE; // is the input a signaling NaN - execute stage
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logic XSNaNM, YSNaNM, ZSNaNM; // is the input a signaling NaN - memory stage
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logic XSubnormE; // is the input Subnormalized
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logic XZeroE, YZeroE, ZZeroE; // is the input zero - execute stage
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logic XZeroM, YZeroM; // is the input zero - memory stage
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logic XInfE, YInfE, ZInfE; // is the input infinity - execute stage
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logic XInfM, YInfM, ZInfM; // is the input infinity - memory stage
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logic XExpMaxE; // is the exponent all ones (max value)
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// Fma Signals
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logic [3*`NF+3:0] SmE, SmM;
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logic FmaAStickyE, FmaAStickyM;
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logic [`NE+1:0] SeE,SeM;
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logic InvAE, InvAM;
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logic AsE, AsM;
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logic PsE, PsM;
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logic SsE, SsM;
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logic [$clog2(3*`NF+5)-1:0] SCntE, SCntM;
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logic [3*`NF+3:0] SmE, SmM; // Sum significand
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logic FmaAStickyE, FmaAStickyM; // FMA addend sticky bit output
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logic [`NE+1:0] SeE,SeM; // Sum exponent
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logic InvAE, InvAM; // Invert addend
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logic AsE, AsM; // Addend sign
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logic PsE, PsM; // Product sign
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logic SsE, SsM; // Sum sign
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logic [$clog2(3*`NF+5)-1:0] SCntE, SCntM; // LZA sum leading zero count
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// Cvt Signals
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logic [`NE:0] CeE, CeM; // the calculated expoent
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logic [`LOGCVTLEN-1:0] CvtShiftAmtE, CvtShiftAmtM; // how much to shift by
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logic CvtResSubnormUfE, CvtResSubnormUfM;// does the result underflow or is Subnormalized
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logic CsE, CsM; // the result's sign
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logic IntZeroE, IntZeroM; // is the integer zero?
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logic [`CVTLEN-1:0] CvtLzcInE, CvtLzcInM; // input to the Leading Zero Counter (priority encoder)
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logic [`NE:0] CeE, CeM; // convert intermediate expoent
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logic [`LOGCVTLEN-1:0] CvtShiftAmtE, CvtShiftAmtM; // how much to shift by
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logic CvtResSubnormUfE, CvtResSubnormUfM; // does the result underflow or is Subnormalized
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logic CsE, CsM; // convert result sign
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logic IntZeroE, IntZeroM; // is the integer zero?
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logic [`CVTLEN-1:0] CvtLzcInE, CvtLzcInM; // input to the Leading Zero Counter (priority encoder)
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logic [`XLEN-1:0] FCvtIntResM; // fcvt integer result (for IEU)
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//divide signals
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logic [`DIVb:0] QmM;
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logic [`NE+1:0] QeM;
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logic DivSM;
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logic FDivDoneE, IFDivStartE;
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// divide signals
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logic [`DIVb:0] QmM; // fdivsqrt signifcand
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logic [`NE+1:0] QeM; // fdivsqrt exponent
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logic DivStickyM; // fdivsqrt sticky bit
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logic FDivDoneE, IFDivStartE; // fdivsqrt control signals
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logic [`XLEN-1:0] FPIntDivResultM; // fdivsqrt integer division result (for IEU)
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// result and flag signals
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logic [`XLEN-1:0] ClassResE; // classify result
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logic [`XLEN-1:0] FIntResE; // classify result
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logic [`FLEN-1:0] FpResM, FpResW; // classify result
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logic [`XLEN-1:0] ClassResE; // classify result
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logic [`XLEN-1:0] FIntResE; // classify result
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logic [`FLEN-1:0] FpResM, FpResW; // classify result
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logic [`FLEN-1:0] PostProcResM; // classify result
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logic [4:0] PostProcFlgM; // classify result
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logic [`XLEN-1:0] FCvtIntResM;
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logic [`FLEN-1:0] CmpFpResE; // compare result
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logic [`XLEN-1:0] CmpIntResE; // compare result
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logic CmpNVE; // compare invalid flag (Not Valid)
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@ -145,7 +153,6 @@ module fpu (
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logic [`FLEN-1:0] BoxedZeroE; // Zero value for Z for multiplication, with NaN boxing if needed
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logic [`FLEN-1:0] BoxedOneE; // Zero value for Z for multiplication, with NaN boxing if needed
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logic StallUnpackedM;
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logic [`XLEN-1:0] FPIntDivResultM;
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// DECODE STAGE
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@ -260,7 +267,7 @@ module fpu (
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fdivsqrt fdivsqrt(.clk, .reset, .FmtE, .XmE, .YmE, .XeE, .YeE, .SqrtE(OpCtrlE[0]), .SqrtM(OpCtrlM[0]),
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.XInfE, .YInfE, .XZeroE, .YZeroE, .XNaNE, .YNaNE, .FDivStartE, .IDivStartE, .XsE,
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.ForwardedSrcAE, .ForwardedSrcBE, .Funct3E, .Funct3M, .IntDivE, .W64E,
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.StallM, .FlushE, .DivSM, .FDivBusyE, .IFDivStartE, .FDivDoneE, .QeM,
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.StallM, .FlushE, .DivStickyM, .FDivBusyE, .IFDivStartE, .FDivDoneE, .QeM,
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.QmM, .FPIntDivResultM /*, .DivDone(DivDoneM) */);
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//
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@ -371,7 +378,7 @@ module fpu (
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.FmaASticky(FmaAStickyM), .XZero(XZeroM), .YZero(YZeroM), .XInf(XInfM), .YInf(YInfM), .DivQm(QmM), .FmaSs(SsM),
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.ZInf(ZInfM), .XNaN(XNaNM), .YNaN(YNaNM), .ZNaN(ZNaNM), .XSNaN(XSNaNM), .YSNaN(YSNaNM), .ZSNaN(ZSNaNM), .FmaSm(SmM), .DivQe(QeM), /*.DivDone(DivDoneM), */
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.FmaAs(AsM), .FmaPs(PsM), .OpCtrl(OpCtrlM), .FmaSCnt(SCntM), .FmaSe(SeM),
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.CvtCe(CeM), .CvtResSubnormUf(CvtResSubnormUfM),.CvtShiftAmt(CvtShiftAmtM), .CvtCs(CsM), .ToInt(FWriteIntM), .DivS(DivSM),
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.CvtCe(CeM), .CvtResSubnormUf(CvtResSubnormUfM),.CvtShiftAmt(CvtShiftAmtM), .CvtCs(CsM), .ToInt(FWriteIntM), .DivS(DivStickyM),
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.CvtLzcIn(CvtLzcInM), .IntZero(IntZeroM), .PostProcSel(PostProcSelM), .PostProcRes(PostProcResM), .PostProcFlg(PostProcFlgM), .FCvtIntRes(FCvtIntResM));
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// FPU flag selection - to privileged
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