added explicit clears to mstatus.mie

tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-mtvec-01.S

@@ -32,12 +32,12 @@ CAUSE_TRAP_TRIGGERS // initialize code that will cause traps for consistent mtva
 TRAP_HANDLER m, VECTORED=0, EXT_SIGNATURE=1 // turn off vectored interrupts, while turning on recording of mstatus bits.
 
 li x28, 0x8
-csrs mstatus, x28 // set sstatus.MIE bit to 1 // *** might be unneccessary for s mode
+csrs mstatus, x28 // set sstatus.MIE bit to 1
 WRITE_READ_CSR mie, 0xFFF
 
 // cause traps, ensuring that we DONT go through the vectored part of the trap handler
 
-jal cause_m_time_interrupt // *** only cause one interrupt because we just want to test the status stack
+jal cause_m_time_interrupt // only cause one interrupt because we just want to test the status stack
 
 END_TESTS
 

tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-sie-01.S

@@ -31,6 +31,8 @@ TRAP_HANDLER m, EXT_SIGNATURE=1 // turn on recording mtval and status bits on tr
 
 li x28, 0x2
 csrs sstatus, x28 // set sstatus.SIE bit to 1
+li x28, 0x8
+csrc mstatus, x28 // clear mstatus.MIE bit
 WRITE_READ_CSR sie, 0x0 // force zeroing out mie CSR.
 
 

tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-status-sie-01.S

@@ -32,6 +32,8 @@ TRAP_HANDLER s, EXT_SIGNATURE=1 // neccessary to handle s mode interrupts.
 
 li x28, 0x2
 csrs sstatus, x28 // set sstatus.SIE bit to 1
+li x28, 0x8
+csrc mstatus, x28 // clear mstatus.MIE bit
 WRITE_READ_CSR mie, 0xFFF // enable all interrupts, including supervisor ones
 WRITE_READ_CSR mideleg 0xFFFF // delegate all interrupts to S mode.
 

tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-stvec-01.S

@@ -34,6 +34,8 @@ TRAP_HANDLER s, VECTORED=0, EXT_SIGNATURE=1 // turn off vectored interrupts, whi
 
 li x28, 0x2
 csrs sstatus, x28 // set sstatus.SIE bit to 1
+li x28, 0x8
+csrc mstatus, x28 // clear mstatus.MIE bit
 WRITE_READ_CSR mie, 0xFFFF
 WRITE_READ_CSR mideleg, 0xFFFFFFFFFFFFFFFF
 

tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-trap-s-01.S

@@ -36,6 +36,8 @@ TRAP_HANDLER s, EXT_SIGNATURE=1 // have S mode trap handler as well
 
 li x28, 0x2
 csrs sstatus, x28 // set sstatus.SIE bit to 1
+li x28, 0x8
+csrc mstatus, x28 // clear mstatus.MIE bit
 WRITE_READ_CSR mie, 0xFFFF // sie is a subset of mie, so writing this also enables sie.
 
 GOTO_S_MODE

tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-trap-u-01.S

@@ -36,6 +36,8 @@ TRAP_HANDLER s, EXT_SIGNATURE=1 // have S mode trap handler as well
 
 li x28, 0x2
 csrs sstatus, x28 // set sstatus.SIE bit to 1. Not strictly necessary but this lets us differentiate which trap handler we went to
+li x28, 0x8
+csrc mstatus, x28 // clear mstatus.MIE bit
 WRITE_READ_CSR mie, 0xFFFF
 
 GOTO_U_MODE

tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-mtvec-01.S

@@ -32,7 +32,7 @@ CAUSE_TRAP_TRIGGERS // initialize code that will cause traps for consistent mtva
 TRAP_HANDLER m, VECTORED=0, EXT_SIGNATURE=1 // turn off vectored interrupts, while turning on recording of mstatus bits.
 
 li x28, 0x8
-csrs mstatus, x28 // set sstatus.MIE bit to 1
+csrs mstatus, x28 // set mstatus.MIE bit to 1
 WRITE_READ_CSR mie, 0xFFF
 
 // cause traps, ensuring that we DONT go through the vectored part of the trap handler

tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-sie-01.S

@@ -31,6 +31,8 @@ TRAP_HANDLER m, EXT_SIGNATURE=1 // turn on recording mtval and status bits on tr
 
 li x28, 0x2
 csrs sstatus, x28 // set sstatus.SIE bit to 1
+li x28, 0x8
+csrc mstatus, x28 // clear mstatus.MIE bit
 WRITE_READ_CSR sie, 0x0 // force zeroing out mie CSR.
 
 

tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-status-sie-01.S

@@ -32,6 +32,8 @@ TRAP_HANDLER s, EXT_SIGNATURE=1 // neccessary to handle s mode interrupts.
 
 li x28, 0x2
 csrs sstatus, x28 // set sstatus.SIE bit to 1
+li x28, 0x8
+csrc mstatus, x28 // clear mstatus.MIE bit
 WRITE_READ_CSR mie, 0xFFF // enable all interrupts, including supervisor ones
 WRITE_READ_CSR mideleg 0xFFFF // delegate all interrupts to S mode.
 

tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-stvec-01.S

@@ -34,6 +34,8 @@ TRAP_HANDLER s, VECTORED=0, EXT_SIGNATURE=1 // turn off vectored interrupts, whi
 
 li x28, 0x2
 csrs sstatus, x28 // set sstatus.SIE bit to 1
+li x28, 0x8
+csrc mstatus, x28 // clear mstatus.MIE bit
 WRITE_READ_CSR mie, 0xFFFF
 WRITE_READ_CSR mideleg, 0xFFFFFFFFFFFFFFFF
 

tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-trap-s-01.S

@@ -36,6 +36,8 @@ TRAP_HANDLER s, EXT_SIGNATURE=1 // have S mode trap handler as well
 
 li x28, 0x2
 csrs sstatus, x28 // set sstatus.SIE bit to 1
+li x28, 0x8
+csrc mstatus, x28 // clear mstatus.MIE bit
 WRITE_READ_CSR mie, 0xFFFF // sie is a subset of mie, so writing this also enables sie.
 
 GOTO_S_MODE

tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-trap-u-01.S

@@ -35,7 +35,9 @@ TRAP_HANDLER s, EXT_SIGNATURE=1 // have S mode trap handler as well
 // Like WALLY-trap, cause all the same traps from U mode and make sure they go to machine mode with zeroed mideleg, medeleg
 
 li x28, 0x2
-csrs sstatus, x28 // set sstatus.SIE bit to 1. Not strictly necessary but this lets us differentiate which trap handler we went to
+csrs sstatus, x28 // set sstatus.SIE bit to 1
+li x28, 0x8
+csrc mstatus, x28 // clear mstatus.MIE bit
 WRITE_READ_CSR mie, 0xFFFF
 
 GOTO_U_MODE