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added logic to handle sign/zero extend instructions

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This commit is contained in:
Kevin Kim 2023-02-18 20:32:40 -08:00
parent 5c563bef43
commit ba968ed95e
3 changed files with 24 additions and 9 deletions
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10
src/ieu/bmu/bmuctrl.sv
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@ -121,8 +121,16 @@ module bmuctrl(
else
BMUControlsD = `BMUCTRLW'b000_0100_000; // count instruction
17'b0011011_0110000_001: BMUControlsD = `BMUCTRLW'b000_0100_000; // count word instruction
17'b0111011_0000100_100: if (`XLEN == 64)
BMUControlsD = `BMUCTRLW'b000_0100_100; // zexth (rv64)
else
BMUControlsD = `BMUCTRLW'b000_0000_000; // illegal instruction
17'b0110011_0000100_100: if (`XLEN == 32)
BMUControlsD = `BMUCTRLW'b000_0100_100; // zexth (rv32)
else
BMUControlsD = `BMUCTRLW'b000_0000_000; // illegal instruction
default: BMUControlsD = {Funct3D, {7'b0}}; // not B instruction or shift
default: BMUControlsD = {Funct3D, {7'b0}}; // not B instruction or shift
endcase
// Unpack Control Signals

16
src/ieu/bmu/ext.sv
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@ -31,13 +31,21 @@
`include "wally-config.vh"
module ext #(parameter WIDTH = 32) (
input logic [WIDTH-1:0] A, // Operand
output logic [WIDTH-1:0] sexthResult, // sign extend halfword result
output logic [WIDTH-1:0] sextbResult, // sign extend byte result
output logic [WIDTH-1:0] zexthResult); // zero extend halfword result
input logic [WIDTH-1:0] A, B, // Operands
output logic [WIDTH-1:0] ExtResult); // Extend Result
logic [WIDTH-1:0] sexthResult, zexthResult, sextbResult;
assign sexthResult = {{(WIDTH-16){A[15]}},A[15:0]};
assign zexthResult = {{(WIDTH-16){1'b0}},A[15:0]};
assign sextbResult = {{(WIDTH-8){A[7]}},A[7:0]};
always_comb
case({B[2],B[0]})
2'b00: ExtResult = zexthResult;
2'b10: ExtResult = sextbResult;
2'b11: ExtResult = sexthResult;
default: ExtResult = 0;
endcase
endmodule

7
src/ieu/bmu/zbb.sv
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@ -47,19 +47,18 @@ module zbb #(parameter WIDTH=32) (
logic [WIDTH-1:0] Rev8Result;
// sign/zero extend results
logic [WIDTH-1:0] sexthResult; // sign extend halfword result
logic [WIDTH-1:0] sextbResult; // sign extend byte result
logic [WIDTH-1:0] zexthResult; // zero extend halfword result
logic [WIDTH-1:0] ExtResult; // sign/zero extend result
cnt #(WIDTH) cnt(.A(A), .B(B), .W64(W64), .CntResult(CntResult));
byteUnit #(WIDTH) bu(.A(A), .OrcBResult(OrcBResult), .Rev8Result(Rev8Result));
ext #(WIDTH) ext(.A(A), .sexthResult(sexthResult), .sextbResult(sextbResult), .zexthResult(zexthResult));
ext #(WIDTH) ext(.A(A), .B(B), .ExtResult(ExtResult));
//can replace with structural mux by looking at bit 4 in rs2 field
always_comb begin
case (ZBBSelect)
3'b111: ZBBResult = ALUResult; // rotate
3'b000: ZBBResult = CntResult; // count
3'b100: ZBBResult = ExtResult; // sign/zero extend
/*15'b0010100_101_00111: ZBBResult = OrcBResult;
15'b0110100_101_11000: ZBBResult = Rev8Result;
15'b0110101_101_11000: ZBBResult = Rev8Result;