comment updates.

This commit is contained in:
Ross Thompson 2022-10-22 16:28:44 -05:00
parent 78586c5a7a
commit f9a04c13df

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@ -205,7 +205,7 @@ module cachefsm
// (CurrState == STATE_FLUSH_CHECK & VictimDirty);
// **** can this be simplified?
assign SelAdr = (CurrState == STATE_READY & (IgnoreRequestTLB & ~TrapM)) | // Ignore Request is needed on TLB miss.
// use the raw requests as we don't want DCacheTrapM in the critical path
// use the raw requests as we don't want TrapM in the critical path
(CurrState == STATE_READY & ((AMO | CacheRW[0]) & CacheHit)) | // changes if store delay hazard removed
(CurrState == STATE_READY & (DoAnyMiss)) |
(CurrState == STATE_MISS_FETCH_WDV) |