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IFU mux for CSRWriteFenceM conditional on ZICSR/ZIFENCEI

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This commit is contained in:
David Harris 2022-12-20 15:38:30 -08:00
parent 35ad49502f
commit 8f640f050f
2 changed files with 7 additions and 8 deletions
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2
pipelined/src/ieu/controller.sv
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@ -130,7 +130,7 @@ module controller(
7'b0001111: if(`ZIFENCEI_SUPPORTED)
ControlsD = `CTRLW'b0_000_00_00_000_0_0_0_0_0_0_0_1_0_00_0; // fence
else
ControlsD = `CTRLW'b0_000_00_00_000_0_0_0_0_0_0_0_0_0_00_0; // fence
ControlsD = `CTRLW'b0_000_00_00_000_0_0_0_0_0_0_0_0_0_00_0; // fence treated as nop
7'b0010011: ControlsD = `CTRLW'b1_000_01_00_000_0_1_0_0_0_0_0_0_0_00_0; // I-type ALU
7'b0010111: ControlsD = `CTRLW'b1_100_11_00_000_0_0_0_0_0_0_0_0_0_00_0; // auipc
7'b0011011: if (`XLEN == 64)

13
pipelined/src/ifu/ifu.sv
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@ -285,16 +285,15 @@ module ifu (
// PCNextF logic
////////////////////////////////////////////////////////////////////////////////////////////////
if(`ICACHE | `ZIFENCEI_SUPPORTED)
if(`ZICSR_SUPPORTED | `ZIFENCEI_SUPPORTED)
mux2 #(`XLEN) pcmux2(.d0(PCNext1F), .d1(NextValidPCE), .s(CSRWriteFenceM),.y(PCNext2F));
// mux2 #(`XLEN) pcmux2(.d0(PCNext1F), .d1(PCM+4), .s(CSRWriteFenceM),.y(PCNext2F));
else assign PCNext2F = PCNext1F;
if(`ZICSR_SUPPORTED) begin
logic PrivilegedChangePCM;
assign PrivilegedChangePCM = RetM | TrapM;
mux2 #(`XLEN) pcmux3(.d0(PCNext2F), .d1(PrivilegedNextPCM), .s(PrivilegedChangePCM),
.y(UnalignedPCNextF));
end else assign UnalignedPCNextF = PCNext2F;
logic PrivilegedChangePCM;
assign PrivilegedChangePCM = RetM | TrapM;
mux2 #(`XLEN) pcmux3(.d0(PCNext2F), .d1(PrivilegedNextPCM), .s(PrivilegedChangePCM), .y(UnalignedPCNextF));
end else
assign UnalignedPCNextF = PCNext2F;
assign PCNextF = {UnalignedPCNextF[`XLEN-1:1], 1'b0}; // hart-SPEC p. 21 about 16-bit alignment
flopenl #(`XLEN) pcreg(clk, reset, ~StallF, PCNextF, `RESET_VECTOR, PCF);