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Finally building ddr3 xilinx ip from script.

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This commit is contained in:
Ross Thompson 2023-04-10 14:36:33 -05:00
parent 5aa614858f
commit d2d528cf3c
2 changed files with 8 additions and 7 deletions
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13
fpga/generator/Makefile
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@ -1,14 +1,14 @@
dst := IP
sdc_src := ~/repos/sdc.tar.gz
# vcu118
#export XILINX_PART := xcvu9p-flga2104-2L-e
#export XILINX_BOARD := xilinx.com:vcu118:part0:2.4
#export board := vcu118
export XILINX_PART := xcvu9p-flga2104-2L-e
export XILINX_BOARD := xilinx.com:vcu118:part0:2.4
export board := vcu118
# vcu108
export XILINX_PART := xcvu095-ffva2104-2-e
export XILINX_BOARD := xilinx.com:vcu108:part0:1.2
export board := vcu108
#export XILINX_PART := xcvu095-ffva2104-2-e
#export XILINX_BOARD := xilinx.com:vcu108:part0:1.2
#export board := vcu108
all: FPGA
@ -18,6 +18,7 @@ FPGA: PreProcessFiles IP SDC
IP: $(dst)/xlnx_proc_sys_reset.log \
$(dst)/xlnx_ddr4-$(board).log \
$(dst)/xlnx_ddr3-artya7.log \
$(dst)/xlnx_axi_clock_converter.log \
$(dst)/xlnx_ahblite_axi_bridge.log

2
fpga/generator/xlnx_ddr3-artya7.tcl
View File

@ -17,7 +17,7 @@ create_ip -name mig_7series -vendor xilinx.com -library ip -module_name $ipName
# 4. Then reconstruct the list with the needed parameters.
# turns out the ddr3 mig cannot be built this way like the ddr 4 mig?!?!?
# instead we need to read the project file, but we have to copy it to the corret location first
cp $WALLY/fpga/generator/xlnx_ddr3-artya7-mig.prj IP/xlnx_ddr3.srcs/sources_1/ip/xlnx_ddr3/
exec cp ../xlnx_ddr3-artya7-mig.prj xlnx_ddr3.srcs/sources_1/ip/xlnx_ddr3/
# unlike the vertex ultra scale and ultra scale + fpga's the atrix 7 mig we only get ui clock.