Xavi/cvw
1
0
Fork 0
forked from Github_Repos/cvw
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Possible fix to AHB burst eviction bug. If HREADY went low during a burst seq the next data phase would only last 1 cycle.

Browse Source
This commit is contained in:
Ross Thompson 2022-09-02 19:58:41 -05:00
parent 4115087b30
commit 3e540a3ca3
1 changed files with 1 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
pipelined/src/lsu/lsu.sv
View File

@ -274,7 +274,7 @@ module lsu (
mux2 #(`XLEN) LSUHWDATAMux(.d0(ReadDataWordM[`XLEN-1:0]), .d1(LSUWriteDataM[`XLEN-1:0]),
.s(SelUncachedAdr), .y(LSUHWDATA_noDELAY));
flop #(`XLEN) wdreg(clk, LSUHWDATA_noDELAY, LSUHWDATA); // delay HWDATA by 1 cycle per spec; *** assumes AHBW = XLEN
flopen #(`XLEN) wdreg(clk, LSUHREADY, LSUHWDATA_noDELAY, LSUHWDATA); // delay HWDATA by 1 cycle per spec; *** assumes AHBW = XLEN
// *** bummer need a second byte mask for bus as it is XLEN rather than LLEN.
// probably can merge by muxing LSUPAdrM's LLEN/8-1 index bit based on HTRANS being != 0.