forked from Github_Repos/cvw
add LRSC test and add wally64a to regression
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@ -62,7 +62,7 @@ tc = TestCase(
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grepstr="400100000 instructions")
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#configs.append(tc) #temporarily removed until I make this checkpoint
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tests64gc = ["arch64i", "arch64priv", "arch64c", "arch64m", "arch64d", "imperas64i", "imperas64f", "imperas64d", "imperas64m", "imperas64a", "imperas64c", "wally64priv"] # , "imperas64mmu" "wally64i", #, "testsBP64"]
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tests64gc = ["arch64i", "arch64priv", "arch64c", "arch64m", "arch64d", "imperas64i", "imperas64f", "imperas64d", "imperas64m", "wally64a", "imperas64c", "wally64priv"] # , "imperas64mmu" "wally64i", #, "testsBP64"]
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for test in tests64gc:
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tc = TestCase(
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name=test,
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@ -91,7 +91,7 @@ logic [3:0] dummy;
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"imperas64f": if (`F_SUPPORTED) tests = imperas64f;
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"imperas64d": if (`D_SUPPORTED) tests = imperas64d;
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"imperas64m": if (`M_SUPPORTED) tests = imperas64m;
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"imperas64a": if (`A_SUPPORTED) tests = imperas64a;
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"wally64a": if (`A_SUPPORTED) tests = wally64a;
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"imperas64c": if (`C_SUPPORTED) tests = imperas64c;
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else tests = imperas64iNOc;
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"testsBP64": tests = testsBP64;
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@ -44,10 +44,10 @@ string tvpaths[] = '{
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"coremark.bare.riscv", "100000"
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};
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string imperas64a[] = '{
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`MYIMPERASTEST,
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"rv64a/WALLY-AMO", "2110",
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"rv64a/WALLY-LRSC", "2110"
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string wally64a[] = '{
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`WALLYTEST,
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"rv64i_m/privilege/WALLY-AMO", "2210",
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"rv64i_m/privilege/WALLY-LRSC", "2410"
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};
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string imperas32a[] = '{
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@ -38,6 +38,7 @@ rv64i_sc_tests = \
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WALLY-scratch-01 \
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WALLY-sscratch-s-01 \
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WALLY-AMO \
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WALLY-LRSC \
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# Don't simulate these because they rely on SoC features that Wally does not offer.
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target_tests_nosim = \
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@ -0,0 +1,24 @@
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fffffffe
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ffffffff
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00000000
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00000000
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0000002a
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00000000
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fffffffd
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ffffffff
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00000001
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00000000
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0000002a
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00000000
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fffffffb
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fffffff7
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00000000
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00000000
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0000002c
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00000000
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ffffffef
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ffffffdf
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00000001
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00000000
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0000002c
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00000000
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@ -0,0 +1,137 @@
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///////////////////////////////////////////
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// WALLY-LRSC.S
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//
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// Tests Atomic LR / SC instructions
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//
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// David_Harris@hmc.edu 7 March 2021
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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// Adapted from Imperas RISCV-TEST_SUITE
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//
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
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// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
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// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
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// is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
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// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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///////////////////////////////////////////
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#include "model_test.h"
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#include "arch_test.h"
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RVTEST_ISA("RV64I")
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.section .text.init
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.globl rvtest_entry_point
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rvtest_entry_point:
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RVMODEL_BOOT
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# ---------------------------------------------------------------------------------------------
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# Addresses for test data and results
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la x6, wally_signature
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la x31, test_data
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# Testcase 0: Do a successful load-reserved / store conditional word operation
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li x11, 42
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lr.w x10, (x31)
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sc.w x12, x11, (x31)
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lw x13, 0(x31)
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sd x10, 0(x6) # should be fffffffffffffffe (sign extended value read from test data)
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sd x12, 8(x6) # should be 0000000000000000 (sc succeeded)
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sd x13, 16(x6) # should be 000000000000002A (value written by SC, in hex)
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# Testcase 1: Do an unsuccessful load-reserved / store conditional word operation
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addi x6, x6, 24
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addi x30, x31, 4
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li x11, 43
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lr.w x10, (x30)
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sc.w x12, x11, (x31) # should fail because not reserved
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lw x13, 0(x31)
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sd x10, 0(x6) # should be fffffffffffffffd (sign extended value read from test data)
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sd x12, 8(x6) # should be 0000000000000001 (sc failed)
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sd x13, 16(x6) # should be 000000000000002A (previous value written by sc)
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# Testcase 2: Do a successful load-reserved / store conditional doubleword operation
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addi x6, x6, 24
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addi x31, x30, 4
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li x11, 44
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lr.d x10, (x31)
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sc.d x12, x11, (x31)
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lw x13, 0(x31)
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sd x10, 0(x6) # should be 0xfffffff7fffffffb (value read from test data)
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sd x12, 8(x6) # should be 0000000000000000 (sc succeeded)
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sd x13, 16(x6) # should be 000000000000002C (value written by SC)
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# Testcase 3: Do an unsuccessful load-reserved / store conditional doubleword operation
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addi x6, x6, 24
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addi x30, x31, 8
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li x11, 45
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lr.d x10, (x30)
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sc.d x12, x11, (x31) # should fail because not reserved
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lw x13, 0(x31)
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sd x10, 0(x6) # should be 0xffffffdfffffffef (sign extended value read from test data)
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sd x12, 8(x6) # should be 0000000000000001 (sc failed)
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sd x13, 16(x6) # should be 000000000000002C (previous value written by sc)
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# ---------------------------------------------------------------------------------------------
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RVMODEL_HALT
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RVTEST_DATA_BEGIN
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.align 8
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test_data:
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.dword 0xfffffffdfffffffe
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.dword 0xfffffff7fffffffb
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.dword 0xffffffdfffffffef
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.dword 0xffffff7fffffffbf
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.dword 0xfffffdfffffffeff
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.dword 0xfffff7fffffffeff
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.dword 0xffffdfffffffefff
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.dword 0xffff7fffffffefff
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.dword 0xfffdfffffffeffff
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.dword 0xfff7fffffffbffff
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.dword 0xffdfffffffefffff
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.dword 0xff7fffffffbfffff
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.dword 0xfdfffffffeffffff
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.dword 0xf7fffffffeffffff
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.dword 0xdfffffffefffffff
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.dword 0x7fffffffefffffff
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.dword 0x00000001ffffffff
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.dword 0x0000000400000002
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.dword 0x0000001000000008
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.dword 0x0000004000000020
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.dword 0x0000010000000080
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.dword 0x0000040000000200
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.dword 0x0000100000000800
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.dword 0x0000400000002000
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.dword 0x0000000100008000
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.dword 0x0004000000000002
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.dword 0x0000001000080000
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.dword 0x0040000000000020
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.dword 0x0000010000800000
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.dword 0x0400000000000200
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.dword 0x0000100008000000
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.dword 0x4000000000002000
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.dword 0x0000000080000000
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#ifdef rvtest_mtrap_routine
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mtrap_sigptr:
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.fill 64*(XLEN/32),4,0xdeadbeef
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#endif
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#ifdef rvtest_gpr_save
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gpr_save:
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.fill 32*(XLEN/32),4,0xdeadbeef
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#endif
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RVTEST_DATA_END
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RVMODEL_DATA_BEGIN
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# signature output
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wally_signature:
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.fill 12, 8, -1
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RVMODEL_DATA_END
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