update to allow running of ImperasDV with linux boot

optimize performance of the tracer

config/buildroot/wally-config.vh

@@ -29,7 +29,7 @@
 `include "wally-shared.vh"
 
 `define FPGA 1
-`define QEMU 1
+`define QEMU 0
 // RV32 or RV64: XLEN = 32 or 64
 `define XLEN 64
 

sim/imperas.ic

@@ -1,4 +1,4 @@
-#--mpdconsole refRoot
+#--mpdconsole
 #--gdbconsole
 --showoverrides
 --showcommands
@@ -18,8 +18,6 @@
 # illegal pmp read contained this
 # --override cpu/tval_ii_code=F
 
---registerset cpu/SCOUNTEREN=0x1
-
 # PMA Settings 
 # 'r': read access allowed
 # 'w': write access allowed
@@ -51,7 +49,7 @@
 
 # Add Imperas simulator application instruction tracing
 --override cpu/show_c_prefix=T
---trace --tracechange --traceshowicount --tracemode -tracemem ASX --monitornetschange --traceafter 10000000
+--trace --tracechange --traceshowicount --tracemode -tracemem ASX --monitornetschange --traceafter 10500000
 
 # Exceptions and pagetables debug
 --override cpu/debugflags=6

sim/run-imperas-linux.sh

@@ -4,6 +4,6 @@ export RISCV=/scratch/moore/RISCV
 
 export IMPERAS_TOOLS=$(pwd)/imperas.ic
 export OTHERFLAGS="+TRACE2LOG_ENABLE=1"
-export OTHERFLAGS="+TRACE2LOG_ENABLE=1 +TRACE2LOG_AFTER=10000000" 
+export OTHERFLAGS="+TRACE2LOG_ENABLE=1 +TRACE2LOG_AFTER=10500000" 
 
 vsim -c -do "do wally-linux-imperas.do buildroot buildroot-no-trace $::env(RISCV) 0 0 0"

testbench/testbench-linux-imperas.sv

@@ -336,9 +336,6 @@ module testbench;
           void'(rvviRefCsrSetVolatile(0, iter));   // MHPMCOUNTERx
         end       
         
-        // ERROR Temporary as it powers up as 0x1
-        void'(rvviRefCsrSet(0, 32'h106, 1));       // RTL sets SCOUNTEREN to 1 for some reason
-        
         // cannot predict this register due to latency between
         // pending and taken
         void'(rvviRefCsrSetVolatile(0, 32'h344));   // MIP