forked from Github_Repos/cvw
Separated out radix 2 and radix 4 stages into different modules
This commit is contained in:
David Harris
parent
b4cb9a678a
commit
81ec1ac858
@ -29,10 +29,10 @@ add wave -group {Divide} -noupdate /testbenchfp/fdivsqrt/fdivsqrt/fdivsqrtiter/Q
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add wave -group {Divide} -noupdate /testbenchfp/fdivsqrt/fdivsqrt/fdivsqrtiter/QNext
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add wave -group {Divide} -noupdate /testbenchfp/fdivsqrt/fdivsqrt/fdivsqrtiter/QMNext
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add wave -group {Divide} -noupdate /testbenchfp/fdivsqrt/fdivsqrt/fdivsqrtiter/*
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add wave -group {Divide} -group inter0 -noupdate /testbenchfp/fdivsqrt/fdivsqrt/fdivsqrtiter/interations[0]/divinteration/*
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add wave -group {Divide} -group inter0 -noupdate /testbenchfp/fdivsqrt/fdivsqrt/fdivsqrtiter/interations[0]/divinteration/otfc/otfc2/*
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add wave -group {Divide} -group inter0 -noupdate /testbenchfp/fdivsqrt/fdivsqrt/fdivsqrtiter/interations[0]/divinteration/qsel/qsel2/*
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# add wave -group {Divide} -group inter0 -noupdate /testbenchfp/fdivsqrt/fdivsqrt/fdivsqrtiter/interations[0]/divinteration/genblk1/qsel4/*
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# add wave -group {Divide} -group inter0 -noupdate /testbenchfp/fdivsqrt/fdivsqrt/fdivsqrtiter/interations[0]/stage/fdivsqrtstage/*
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# add wave -group {Divide} -group inter0 -noupdate /testbenchfp/fdivsqrt/fdivsqrt/fdivsqrtiter/interations[0]/stage/fdivsqrtstage/otfc/otfc2/*
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# add wave -group {Divide} -group inter0 -noupdate /testbenchfp/fdivsqrt/fdivsqrt/fdivsqrtiter/interations[0]/stage/fdivsqrtstage/qsel/qsel2/*
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# add wave -group {Divide} -group inter0 -noupdate /testbenchfp/fdivsqrt/fdivsqrt/fdivsqrtiter/interations[0]/fdivsqrtstage/stage/genblk1/qsel4/*
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add wave -group {Divide} -noupdate /testbenchfp/fdivsqrt/fdivsqrt/fdivsqrtpreproc/*
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add wave -group {Divide} -noupdate /testbenchfp/fdivsqrt/fdivsqrt/fdivsqrtpreproc/expcalc/*
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add wave -group {Divide} -noupdate /testbenchfp/fdivsqrt/fdivsqrt/fdivsqrtfsm/*
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@ -122,9 +122,15 @@ module fdivsqrtiter(
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genvar i;
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generate
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for(i=0; $unsigned(i)<`DIVCOPIES; i++) begin : interations
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divinteration divinteration(.D, .DBar, .D2, .DBar2, .SqrtM,
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.WS(WS[i]), .WC(WC[i]), .WSA(WSA[i]), .WCA(WCA[i]), .Q(Q[i]), .QM(QM[i]), .QNext(QNext[i]), .QMNext(QMNext[i]),
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.C(C[i]), .S(S[i]), .SM(SM[i]), .SNext(SNext[i]), .SMNext(SMNext[i]), .qn(qn[i]));
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if (`RADIX == 2) begin: stage
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fdivsqrtstage2 fdivsqrtstage(.D, .DBar, .D2, .DBar2, .SqrtM,
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.WS(WS[i]), .WC(WC[i]), .WSA(WSA[i]), .WCA(WCA[i]), .Q(Q[i]), .QM(QM[i]), .QNext(QNext[i]), .QMNext(QMNext[i]),
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.C(C[i]), .S(S[i]), .SM(SM[i]), .SNext(SNext[i]), .SMNext(SMNext[i]), .qn(qn[i]));
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end else begin: stage
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fdivsqrtstage4 fdivsqrtstage(.D, .DBar, .D2, .DBar2, .SqrtM,
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.WS(WS[i]), .WC(WC[i]), .WSA(WSA[i]), .WCA(WCA[i]), .Q(Q[i]), .QM(QM[i]), .QNext(QNext[i]), .QMNext(QMNext[i]),
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.C(C[i]), .S(S[i]), .SM(SM[i]), .SNext(SNext[i]), .SMNext(SMNext[i]), .qn(qn[i]));
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end
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if(i<(`DIVCOPIES-1)) begin
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if (`RADIX==2)begin
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assign WS[i+1] = {WSA[i][`DIVb+2:0], 1'b0};
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@ -174,84 +180,5 @@ module fdivsqrtiter(
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assign StickyWSA = {WSA[0][`DIVb+2:0], 1'b0};
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else
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assign StickyWSA = {WSA[1][`DIVb+2:0], 1'b0};
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endmodule
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////////////////
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// Submodules //
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////////////////
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/* verilator lint_off UNOPTFLAT */
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module divinteration (
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input logic [`DIVN-2:0] D,
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input logic [`DIVb+3:0] DBar, D2, DBar2,
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input logic [`DIVb:0] Q, QM,
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input logic [`DIVb:0] S, SM,
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input logic [`DIVb+3:0] WS, WC,
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input logic [`DIVb-1:0] C,
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input logic SqrtM,
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output logic [`DIVb:0] QNext, QMNext,
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output logic qn,
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output logic [`DIVb:0] SNext, SMNext,
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output logic [`DIVb+3:0] WSA, WCA
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);
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/* verilator lint_on UNOPTFLAT */
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logic [`DIVb+3:0] Dsel;
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logic [3:0] q;
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logic qp, qz;
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logic [`DIVb+3:0] F;
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logic [`DIVb+3:0] AddIn;
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// Qmient Selection logic
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// Given partial remainder, select quotient of +1, 0, or -1 (qp, qz, pm)
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// q encoding:
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// 1000 = +2
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// 0100 = +1
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// 0000 = 0
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// 0010 = -1
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// 0001 = -2
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if(`RADIX == 2) begin : qsel
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qsel2 qsel2(WS[`DIVb+3:`DIVb], WC[`DIVb+3:`DIVb], qp, qz, qn);
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fgen2 fgen2(.sp(qp), .sz(qz), .C, .S, .SM, .F);
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end else begin
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qsel4 qsel4(.D, .WS, .WC, .Sqrt(SqrtM), .q);
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// fgen4 fgen4(.s(q), .C, .S, .SM, .F);
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end
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if(`RADIX == 2) begin : dsel
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assign Dsel = {`DIVb+4{~qz}}&(qp ? DBar : {3'b0, 1'b1, D, {`DIVb-`DIVN+1{1'b0}}});
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end else begin
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always_comb
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case (q)
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4'b1000: Dsel = DBar2;
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4'b0100: Dsel = DBar;
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4'b0000: Dsel = '0;
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4'b0010: Dsel = {3'b0, 1'b1, D, {`DIVb-`DIVN+1{1'b0}}};
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4'b0001: Dsel = D2;
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default: Dsel = 'x;
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endcase
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end
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// Partial Product Generation
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// WSA, WCA = WS + WC - qD
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assign AddIn = SqrtM ? F : Dsel;
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if (`RADIX == 2) begin : csa
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csa #(`DIVb+4) csa(WS, WC, AddIn, qp&~SqrtM, WSA, WCA);
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end else begin
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csa #(`DIVb+4) csa(WS, WC, AddIn, |q[3:2]&~SqrtM, WSA, WCA);
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end
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if (`RADIX == 2) begin : otfc
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otfc2 otfc2(.qp, .qz, .Q, .QM, .QNext, .QMNext);
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sotfc2 sotfc2(.sp(qp), .sz(qz), .C, .S, .SM, .SNext, .SMNext);
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end else begin
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otfc4 otfc4(.q, .Q, .QM, .QNext, .QMNext);
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// sotfc4 sotfc4(.s(q), .SqrtM, .C, .S, .SM, .SNext, .SMNext);
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end
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endmodule
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76
pipelined/src/fpu/fdivsqrtstage2.sv
Normal file
76
pipelined/src/fpu/fdivsqrtstage2.sv
Normal file
@ -0,0 +1,76 @@
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///////////////////////////////////////////
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// fdivsqrtstage2.sv
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//
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// Written: David_Harris@hmc.edu, me@KatherineParry.com, Cedar Turek
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// Modified:13 January 2022
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//
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// Purpose: Combined Divide and Square Root Floating Point and Integer Unit stage
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// MIT LICENSE
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this
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// software and associated documentation files (the "Software"), to deal in the Software
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// without restriction, including without limitation the rights to use, copy, modify, merge,
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// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons
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// to whom the Software is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or
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// substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
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// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
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// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE
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// OR OTHER DEALINGS IN THE SOFTWARE.
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////////////////////////////////////////////////////////////////////////////////////////////////
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`include "wally-config.vh"
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/* verilator lint_off UNOPTFLAT */
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module fdivsqrtstage2 (
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input logic [`DIVN-2:0] D,
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input logic [`DIVb+3:0] DBar, D2, DBar2,
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input logic [`DIVb:0] Q, QM,
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input logic [`DIVb:0] S, SM,
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input logic [`DIVb+3:0] WS, WC,
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input logic [`DIVb-1:0] C,
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input logic SqrtM,
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output logic [`DIVb:0] QNext, QMNext,
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output logic qn,
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output logic [`DIVb:0] SNext, SMNext,
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output logic [`DIVb+3:0] WSA, WCA
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);
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/* verilator lint_on UNOPTFLAT */
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logic [`DIVb+3:0] Dsel;
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logic qp, qz;
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logic [`DIVb+3:0] F;
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logic [`DIVb+3:0] AddIn;
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// Qmient Selection logic
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// Given partial remainder, select quotient of +1, 0, or -1 (qp, qz, pm)
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// q encoding:
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// 1000 = +2
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// 0100 = +1
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// 0000 = 0
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// 0010 = -1
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// 0001 = -2
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qsel2 qsel2(WS[`DIVb+3:`DIVb], WC[`DIVb+3:`DIVb], qp, qz, qn);
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fgen2 fgen2(.sp(qp), .sz(qz), .C, .S, .SM, .F);
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assign Dsel = {`DIVb+4{~qz}}&(qp ? DBar : {3'b0, 1'b1, D, {`DIVb-`DIVN+1{1'b0}}});
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// Partial Product Generation
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// WSA, WCA = WS + WC - qD
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assign AddIn = SqrtM ? F : Dsel;
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csa #(`DIVb+4) csa(WS, WC, AddIn, qp&~SqrtM, WSA, WCA);
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// *** dh 8/29/22: will need to trim down to just sotfc
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otfc2 otfc2(.qp, .qz, .Q, .QM, .QNext, .QMNext);
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sotfc2 sotfc2(.sp(qp), .sz(qz), .C, .S, .SM, .SNext, .SMNext);
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endmodule
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84
pipelined/src/fpu/fdivsqrtstage4.sv
Normal file
84
pipelined/src/fpu/fdivsqrtstage4.sv
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@ -0,0 +1,84 @@
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///////////////////////////////////////////
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// fdivsqrtstage4.sv
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//
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// Written: David_Harris@hmc.edu, me@KatherineParry.com, Cedar Turek
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// Modified:13 January 2022
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//
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// Purpose: Combined Divide and Square Root Floating Point and Integer Unit stage
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// MIT LICENSE
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this
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// software and associated documentation files (the "Software"), to deal in the Software
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// without restriction, including without limitation the rights to use, copy, modify, merge,
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// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons
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// to whom the Software is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or
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// substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
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// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
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// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE
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// OR OTHER DEALINGS IN THE SOFTWARE.
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////////////////////////////////////////////////////////////////////////////////////////////////
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`include "wally-config.vh"
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/* verilator lint_off UNOPTFLAT */
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module fdivsqrtstage4 (
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input logic [`DIVN-2:0] D,
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input logic [`DIVb+3:0] DBar, D2, DBar2,
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input logic [`DIVb:0] Q, QM,
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input logic [`DIVb:0] S, SM,
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input logic [`DIVb+3:0] WS, WC,
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input logic [`DIVb-1:0] C,
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input logic SqrtM,
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output logic [`DIVb:0] QNext, QMNext,
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output logic qn,
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output logic [`DIVb:0] SNext, SMNext,
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output logic [`DIVb+3:0] WSA, WCA
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);
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/* verilator lint_on UNOPTFLAT */
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logic [`DIVb+3:0] Dsel;
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logic [3:0] q;
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logic [`DIVb+3:0] F;
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logic [`DIVb+3:0] AddIn;
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// Qmient Selection logic
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// Given partial remainder, select quotient of +1, 0, or -1 (qp, qz, pm)
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// q encoding:
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// 1000 = +2
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// 0100 = +1
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// 0000 = 0
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// 0010 = -1
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// 0001 = -2
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qsel4 qsel4(.D, .WS, .WC, .Sqrt(SqrtM), .q);
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// fgen4 fgen4(.s(q), .C, .S, .SM, .F);
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always_comb
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case (q)
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4'b1000: Dsel = DBar2;
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4'b0100: Dsel = DBar;
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4'b0000: Dsel = '0;
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4'b0010: Dsel = {3'b0, 1'b1, D, {`DIVb-`DIVN+1{1'b0}}};
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4'b0001: Dsel = D2;
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default: Dsel = 'x;
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endcase
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// Partial Product Generation
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// WSA, WCA = WS + WC - qD
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assign AddIn = SqrtM ? F : Dsel;
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csa #(`DIVb+4) csa(WS, WC, AddIn, |q[3:2]&~SqrtM, WSA, WCA);
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otfc4 otfc4(.q, .Q, .QM, .QNext, .QMNext);
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// sotfc4 sotfc4(.s(q), .SqrtM, .C, .S, .SM, .SNext, .SMNext);
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endmodule
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