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More cleanup

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This commit is contained in:
Limnanthes Serafini 2023-04-13 21:02:30 -07:00
parent 94b686fcf6
commit 28dd41291a
8 changed files with 31 additions and 31 deletions
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2
src/fpu/fdivsqrt/fdivsqrtfgen2.sv
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@ -29,7 +29,7 @@
`include "wally-config.vh"
module fdivsqrtfgen2 (
input logic up, uz,
input logic up, uz,
input logic [`DIVb+3:0] C, U, UM,
output logic [`DIVb+3:0] F
);

2
src/fpu/fdivsqrt/fdivsqrtfgen4.sv
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@ -29,7 +29,7 @@
`include "wally-config.vh"
module fdivsqrtfgen4 (
input logic [3:0] udigit,
input logic [3:0] udigit,
input logic [`DIVb+3:0] C, U, UM,
output logic [`DIVb+3:0] F
);

34
src/fpu/fdivsqrt/fdivsqrtfsm.sv
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@ -29,24 +29,24 @@
`include "wally-config.vh"
module fdivsqrtfsm(
input logic clk,
input logic reset,
input logic clk,
input logic reset,
input logic [`FMTBITS-1:0] FmtE,
input logic XInfE, YInfE,
input logic XZeroE, YZeroE,
input logic XNaNE, YNaNE,
input logic FDivStartE, IDivStartE,
input logic XsE,
input logic SqrtE,
input logic StallM,
input logic FlushE,
input logic WZeroE,
input logic IntDivE,
input logic [`DIVBLEN:0] nE,
input logic ISpecialCaseE,
output logic IFDivStartE,
output logic FDivBusyE, FDivDoneE,
output logic SpecialCaseM
input logic XInfE, YInfE,
input logic XZeroE, YZeroE,
input logic XNaNE, YNaNE,
input logic FDivStartE, IDivStartE,
input logic XsE,
input logic SqrtE,
input logic StallM,
input logic FlushE,
input logic WZeroE,
input logic IntDivE,
input logic [`DIVBLEN:0] nE,
input logic ISpecialCaseE,
output logic IFDivStartE,
output logic FDivBusyE, FDivDoneE,
output logic SpecialCaseM
);
typedef enum logic [1:0] {IDLE, BUSY, DONE} statetype;

8
src/fpu/fdivsqrt/fdivsqrtiter.sv
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@ -29,10 +29,10 @@
`include "wally-config.vh"
module fdivsqrtiter(
input logic clk,
input logic IFDivStartE,
input logic FDivBusyE,
input logic SqrtE,
input logic clk,
input logic IFDivStartE,
input logic FDivBusyE,
input logic SqrtE,
input logic [`DIVb+3:0] X,
input logic [`DIVb-1:0] DPreproc,
output logic [`DIVb-1:0] D,

2
src/fpu/fdivsqrt/fdivsqrtpostproc.sv
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@ -112,7 +112,7 @@ module fdivsqrtpostproc(
// Select quotient or remainder and do normalization shift
mux2 #(`DIVBLEN+1) normshiftmux(((`DIVBLEN+1)'(`DIVb) - (nM * (`DIVBLEN+1)'(`LOGR))), (mM + (`DIVBLEN+1)'(`DIVa)), RemOpM, NormShiftM);
mux2 #(`DIVb+4) presresultmux(NormQuotM, NormRemM, RemOpM, PreResultM);
mux2 #(`DIVb+4) presresultmux(NormQuotM, NormRemM, RemOpM, PreResultM);
assign PreIntResultM = $signed(PreResultM >>> NormShiftM);
// special case logic

2
src/fpu/fdivsqrt/fdivsqrtqsel2.sv
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@ -30,7 +30,7 @@
module fdivsqrtqsel2 (
input logic [3:0] ps, pc,
output logic up, uz, un
output logic up, uz, un
);
logic [3:0] p, g;

6
src/fpu/fdivsqrt/fdivsqrtstage4.sv
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@ -31,7 +31,7 @@
module fdivsqrtstage4 (
input logic [`DIVb-1:0] D,
input logic [`DIVb+3:0] DBar, D2, DBar2,
input logic [`DIVb:0] U,UM,
input logic [`DIVb:0] U,UM,
input logic [`DIVb+3:0] WS, WC,
input logic [`DIVb+1:0] C,
input logic SqrtE, j1,
@ -58,8 +58,8 @@ module fdivsqrtstage4 (
// 0000 = 0
// 0010 = -1
// 0001 = -2
assign Smsbs = U[`DIVb:`DIVb-4];
assign Dmsbs = D[`DIVb-1:`DIVb-3];
assign Smsbs = U[`DIVb:`DIVb-4];
assign Dmsbs = D[`DIVb-1:`DIVb-3];
assign WCmsbs = WC[`DIVb+3:`DIVb-4];
assign WSmsbs = WS[`DIVb+3:`DIVb-4];

6
src/fpu/fdivsqrt/fdivsqrtuotfc2.sv
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@ -32,10 +32,10 @@
// Unified OTFC, Radix 2 //
///////////////////////////////
module fdivsqrtuotfc2(
input logic up, un,
input logic up, un,
input logic [`DIVb+1:0] C,
input logic [`DIVb:0] U, UM,
output logic [`DIVb:0] UNext, UMNext
input logic [`DIVb:0] U, UM,
output logic [`DIVb:0] UNext, UMNext
);
// The on-the-fly converter transfers the divsqrt
// bits to the quotient as they come.