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support more fp -> fp conversions

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This commit is contained in:
David Harris 2023-03-28 10:28:01 -07:00
parent fd2d08f501
commit e5955c5dd8
1 changed files with 8 additions and 4 deletions
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12
src/fpu/fctrl.sv
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@ -150,10 +150,14 @@ module fctrl (
ControlsD = `FCTRLW'b0_1_11_xx_000_0_0_0; // fmv.x.w / fmv.x.d to int register
7'b111100?: if (Funct3D == 3'b000 & Rs2D == 5'b00000)
ControlsD = `FCTRLW'b1_0_00_xx_011_0_0_0; // fmv.w.x / fmv.d.x to fp reg
7'b0100000: if (Rs2D[4:2] == 3'b000)
ControlsD = `FCTRLW'b1_0_01_00_000_0_0_0; // fcvt.s.d
7'b0100001: if (Rs2D[4:2] == 3'b000)
ControlsD = `FCTRLW'b1_0_01_00_001_0_0_0; // fcvt.d.s
7'b0100000: if (Rs2D[4:2] == 3'b000 & SupportedFmt2 & Rs2D[1:0] != 2'b00)
ControlsD = `FCTRLW'b1_0_01_00_000_0_0_0; // fcvt.s.(d/q/h)
7'b0100001: if (Rs2D[4:2] == 3'b000 & SupportedFmt2 & Rs2D[1:0] != 2'b01)
ControlsD = `FCTRLW'b1_0_01_00_001_0_0_0; // fcvt.d.(s/h/q)
7'b0100010: if (Rs2D[4:2] == 3'b000 & SupportedFmt2 & Rs2D[1:0] != 2'b10)
ControlsD = `FCTRLW'b1_0_01_00_000_0_0_0; // fcvt.h.(s/d//h)
7'b0100011: if (Rs2D[4:2] == 3'b000 & SupportedFmt2 & Rs2D[1:0] != 2'b11)
ControlsD = `FCTRLW'b1_0_01_00_001_0_0_0; // fcvt.q.(s/h/d)
// *** other formats here
/* verilator lint_off CASEINCOMPLETE */
7'b1101000: case(Rs2D)