forked from Github_Repos/cvw
Started Integer Preprocessing
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@ -67,7 +67,7 @@ module fdivsqrt(
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fdivsqrtpreproc fdivsqrtpreproc(
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.clk, .DivStartE, .Xm(XmE), .QeM, .Xe(XeE), .Fmt(FmtE), .Ye(YeE),
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.Sqrt(SqrtE), .Ym(YmE), .XZero(XZeroE), .X, .Dpreproc,
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.Sqrt(SqrtE), .Int(MDUE), .Ym(YmE), .XZero(XZeroE), .X, .Dpreproc,
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.ForwardedSrcAE, .ForwardedSrcBE, .Funct3E, .Funct3M, .MDUE, .W64E);
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fdivsqrtfsm fdivsqrtfsm(
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.clk, .reset, .FmtE, .XsE, .SqrtE,
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@ -37,7 +37,8 @@ module fdivsqrtpreproc (
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input logic [`NE-1:0] Xe, Ye,
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input logic [`FMTBITS-1:0] Fmt,
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input logic Sqrt,
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input logic XZero,
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input logic Int,
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input logic XZero,
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input logic [`XLEN-1:0] ForwardedSrcAE, ForwardedSrcBE, // *** these are the src outputs before the mux choosing between them and PCE to put in srcA/B
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input logic [2:0] Funct3E, Funct3M,
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input logic MDUE, W64E,
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@ -49,6 +50,7 @@ module fdivsqrtpreproc (
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// logic [`DIVLEN-1:0] ExtraA, ExtraB, PreprocA, PreprocB, PreprocX, PreprocY;
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logic [`NF-1:0] PreprocA, PreprocX;
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logic [`NF-1:0] PreprocB, PreprocY;
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// logic [`DIVN-1:0] ZeroBufX, ZeroBufY; add after Cedar Commit
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logic [`NF+1:0] SqrtX;
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logic [`DIVb+3:0] DivX;
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logic [$clog2(`NF+2)-1:0] XZeroCnt, YZeroCnt;
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@ -56,6 +58,9 @@ module fdivsqrtpreproc (
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// ***can probably merge X LZC with conversion
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// cout the number of leading zeros
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// Muxes needed for Int; add after Cedar Commit
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// assign ZeroBufX = Int ? {ForwardedSrcAE, {`DIVN-`XLEN{1'b0}}} : {Xm, {`DIVN-`NF{1'b0}}};
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// assign ZeroBufY = Int ? {ForwardedSrcBE, {`DIVN-`XLEN{1'b0}}} : {Ym, {`DIVN-`NF{1'b0}}};
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lzc #(`NF+1) lzcX (Xm, XZeroCnt);
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lzc #(`NF+1) lzcY (Ym, YZeroCnt);
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@ -65,7 +70,7 @@ module fdivsqrtpreproc (
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assign SqrtX = Xe[0]^XZeroCnt[0] ? {1'b0, ~XZero, PreprocX} : {~XZero, PreprocX, 1'b0};
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assign DivX = {3'b000, ~XZero, PreprocX, {`DIVb-`NF{1'b0}}};
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// *** explain why X is shifted between radices
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// *** explain why X is shifted between radices (initial assignment of WS=RX)
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if (`RADIX == 2) assign X = Sqrt ? {3'b111, SqrtX, {`DIVb-1-`NF{1'b0}}} : DivX;
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else assign X = Sqrt ? {2'b11, SqrtX, {`DIVb-1-`NF{1'b0}}, 1'b0} : DivX;
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assign Dpreproc = {PreprocY, {`DIVN-1-`NF{1'b0}}};
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