forked from Github_Repos/cvw
fctrl updated and buildroot working again
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@ -126,18 +126,15 @@ module fctrl (
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3'b000: ControlsD = `FCTRLW'b1_0_00_xx_000_0_0_0; // fsgnj
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3'b001: ControlsD = `FCTRLW'b1_0_00_xx_001_0_0_0; // fsgnjn
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3'b010: ControlsD = `FCTRLW'b1_0_00_xx_010_0_0_0; // fsgnjx
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// default: ControlsD = `FCTRLW'b0_0_00_xx_000_0_1_0; // non-implemented instruction
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endcase
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7'b00101??: case(Funct3D)
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3'b000: ControlsD = `FCTRLW'b1_0_00_xx_110_0_0_0; // fmin
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3'b001: ControlsD = `FCTRLW'b1_0_00_xx_101_0_0_0; // fmax
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// default: ControlsD = `FCTRLW'b0_0_00_xx_000_0_1_0; // non-implemented instruction
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endcase
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7'b10100??: case(Funct3D)
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3'b010: ControlsD = `FCTRLW'b0_1_00_xx_010_0_0_0; // feq
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3'b001: ControlsD = `FCTRLW'b0_1_00_xx_001_0_0_0; // flt
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3'b000: ControlsD = `FCTRLW'b0_1_00_xx_011_0_0_0; // fle
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// default: ControlsD = `FCTRLW'b0_0_00_xx_000__0_1_0; // non-implemented instruction
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endcase
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7'b11100??: if (Funct3D == 3'b001 & Rs2D == 5'b00000)
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ControlsD = `FCTRLW'b0_1_10_xx_000_0_0_0; // fclass
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@ -202,9 +199,7 @@ module fctrl (
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5'b00011: ControlsD = `FCTRLW'b0_1_01_00_010_0_0_1; // fcvt.lu.q q->lu
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endcase
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// default: ControlsD = `FCTRLW'b0_0_00_xx_000_0_1_0; // non-implemented instruction
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endcase
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// default: ControlsD = `FCTRLW'b0_0_00_xx_000_0_1_0; // non-implemented instruction
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endcase
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end
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/* verilator lint_on CASEINCOMPLETE */
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@ -333,7 +328,5 @@ module fctrl (
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flopenrc #(4) MWCtrlReg(clk, reset, FlushW, ~StallW,
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{FRegWriteM, FResSelM, FCvtIntM},
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{FRegWriteW, FResSelW, FCvtIntW});
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//assign FCvtIntW = (FResSelW == 2'b01);
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endmodule
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